2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2010, Pyun YongHyeon <yongari@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 /* Driver for DM&P Electronics, Inc, Vortex86 RDC R6040 FastEthernet. */
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/systm.h>
38 #include <sys/endian.h>
39 #include <sys/kernel.h>
41 #include <sys/malloc.h>
43 #include <sys/module.h>
44 #include <sys/mutex.h>
46 #include <sys/socket.h>
47 #include <sys/sockio.h>
48 #include <sys/sysctl.h>
52 #include <net/if_var.h>
53 #include <net/if_arp.h>
54 #include <net/ethernet.h>
55 #include <net/if_dl.h>
56 #include <net/if_llc.h>
57 #include <net/if_media.h>
58 #include <net/if_types.h>
59 #include <net/if_vlan_var.h>
61 #include <netinet/in.h>
62 #include <netinet/in_systm.h>
64 #include <dev/mii/mii.h>
65 #include <dev/mii/miivar.h>
67 #include <dev/pci/pcireg.h>
68 #include <dev/pci/pcivar.h>
70 #include <machine/bus.h>
72 #include <dev/vte/if_vtereg.h>
73 #include <dev/vte/if_vtevar.h>
75 /* "device miibus" required. See GENERIC if you get errors here. */
76 #include "miibus_if.h"
78 MODULE_DEPEND(vte, pci, 1, 1, 1);
79 MODULE_DEPEND(vte, ether, 1, 1, 1);
80 MODULE_DEPEND(vte, miibus, 1, 1, 1);
83 static int tx_deep_copy = 1;
84 TUNABLE_INT("hw.vte.tx_deep_copy", &tx_deep_copy);
87 * Devices supported by this driver.
89 static const struct vte_ident vte_ident_table[] = {
90 { VENDORID_RDC, DEVICEID_RDC_R6040, "RDC R6040 FastEthernet"},
94 static int vte_attach(device_t);
95 static int vte_detach(device_t);
96 static int vte_dma_alloc(struct vte_softc *);
97 static void vte_dma_free(struct vte_softc *);
98 static void vte_dmamap_cb(void *, bus_dma_segment_t *, int, int);
99 static struct vte_txdesc *
100 vte_encap(struct vte_softc *, struct mbuf **);
101 static const struct vte_ident *
102 vte_find_ident(device_t);
103 #ifndef __NO_STRICT_ALIGNMENT
105 vte_fixup_rx(struct ifnet *, struct mbuf *);
107 static void vte_get_macaddr(struct vte_softc *);
108 static void vte_init(void *);
109 static void vte_init_locked(struct vte_softc *);
110 static int vte_init_rx_ring(struct vte_softc *);
111 static int vte_init_tx_ring(struct vte_softc *);
112 static void vte_intr(void *);
113 static int vte_ioctl(struct ifnet *, u_long, caddr_t);
114 static uint64_t vte_get_counter(struct ifnet *, ift_counter);
115 static void vte_mac_config(struct vte_softc *);
116 static int vte_miibus_readreg(device_t, int, int);
117 static void vte_miibus_statchg(device_t);
118 static int vte_miibus_writereg(device_t, int, int, int);
119 static int vte_mediachange(struct ifnet *);
120 static int vte_mediachange_locked(struct ifnet *);
121 static void vte_mediastatus(struct ifnet *, struct ifmediareq *);
122 static int vte_newbuf(struct vte_softc *, struct vte_rxdesc *);
123 static int vte_probe(device_t);
124 static void vte_reset(struct vte_softc *);
125 static int vte_resume(device_t);
126 static void vte_rxeof(struct vte_softc *);
127 static void vte_rxfilter(struct vte_softc *);
128 static int vte_shutdown(device_t);
129 static void vte_start(struct ifnet *);
130 static void vte_start_locked(struct vte_softc *);
131 static void vte_start_mac(struct vte_softc *);
132 static void vte_stats_clear(struct vte_softc *);
133 static void vte_stats_update(struct vte_softc *);
134 static void vte_stop(struct vte_softc *);
135 static void vte_stop_mac(struct vte_softc *);
136 static int vte_suspend(device_t);
137 static void vte_sysctl_node(struct vte_softc *);
138 static void vte_tick(void *);
139 static void vte_txeof(struct vte_softc *);
140 static void vte_watchdog(struct vte_softc *);
141 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
142 static int sysctl_hw_vte_int_mod(SYSCTL_HANDLER_ARGS);
144 static device_method_t vte_methods[] = {
145 /* Device interface. */
146 DEVMETHOD(device_probe, vte_probe),
147 DEVMETHOD(device_attach, vte_attach),
148 DEVMETHOD(device_detach, vte_detach),
149 DEVMETHOD(device_shutdown, vte_shutdown),
150 DEVMETHOD(device_suspend, vte_suspend),
151 DEVMETHOD(device_resume, vte_resume),
154 DEVMETHOD(miibus_readreg, vte_miibus_readreg),
155 DEVMETHOD(miibus_writereg, vte_miibus_writereg),
156 DEVMETHOD(miibus_statchg, vte_miibus_statchg),
161 static driver_t vte_driver = {
164 sizeof(struct vte_softc)
167 static devclass_t vte_devclass;
169 DRIVER_MODULE(vte, pci, vte_driver, vte_devclass, 0, 0);
170 DRIVER_MODULE(miibus, vte, miibus_driver, miibus_devclass, 0, 0);
173 vte_miibus_readreg(device_t dev, int phy, int reg)
175 struct vte_softc *sc;
178 sc = device_get_softc(dev);
180 CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_READ |
181 (phy << MMDIO_PHY_ADDR_SHIFT) | (reg << MMDIO_REG_ADDR_SHIFT));
182 for (i = VTE_PHY_TIMEOUT; i > 0; i--) {
184 if ((CSR_READ_2(sc, VTE_MMDIO) & MMDIO_READ) == 0)
189 device_printf(sc->vte_dev, "phy read timeout : %d\n", reg);
193 return (CSR_READ_2(sc, VTE_MMRD));
197 vte_miibus_writereg(device_t dev, int phy, int reg, int val)
199 struct vte_softc *sc;
202 sc = device_get_softc(dev);
204 CSR_WRITE_2(sc, VTE_MMWD, val);
205 CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_WRITE |
206 (phy << MMDIO_PHY_ADDR_SHIFT) | (reg << MMDIO_REG_ADDR_SHIFT));
207 for (i = VTE_PHY_TIMEOUT; i > 0; i--) {
209 if ((CSR_READ_2(sc, VTE_MMDIO) & MMDIO_WRITE) == 0)
214 device_printf(sc->vte_dev, "phy write timeout : %d\n", reg);
220 vte_miibus_statchg(device_t dev)
222 struct vte_softc *sc;
223 struct mii_data *mii;
227 sc = device_get_softc(dev);
229 mii = device_get_softc(sc->vte_miibus);
231 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
234 sc->vte_flags &= ~VTE_FLAG_LINK;
235 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
236 (IFM_ACTIVE | IFM_AVALID)) {
237 switch (IFM_SUBTYPE(mii->mii_media_active)) {
240 sc->vte_flags |= VTE_FLAG_LINK;
247 /* Stop RX/TX MACs. */
249 /* Program MACs with resolved duplex and flow control. */
250 if ((sc->vte_flags & VTE_FLAG_LINK) != 0) {
252 * Timer waiting time : (63 + TIMER * 64) MII clock.
253 * MII clock : 25MHz(100Mbps) or 2.5MHz(10Mbps).
255 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX)
256 val = 18 << VTE_IM_TIMER_SHIFT;
258 val = 1 << VTE_IM_TIMER_SHIFT;
259 val |= sc->vte_int_rx_mod << VTE_IM_BUNDLE_SHIFT;
260 /* 48.6us for 100Mbps, 50.8us for 10Mbps */
261 CSR_WRITE_2(sc, VTE_MRICR, val);
263 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX)
264 val = 18 << VTE_IM_TIMER_SHIFT;
266 val = 1 << VTE_IM_TIMER_SHIFT;
267 val |= sc->vte_int_tx_mod << VTE_IM_BUNDLE_SHIFT;
268 /* 48.6us for 100Mbps, 50.8us for 10Mbps */
269 CSR_WRITE_2(sc, VTE_MTICR, val);
277 vte_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
279 struct vte_softc *sc;
280 struct mii_data *mii;
284 if ((ifp->if_flags & IFF_UP) == 0) {
288 mii = device_get_softc(sc->vte_miibus);
291 ifmr->ifm_status = mii->mii_media_status;
292 ifmr->ifm_active = mii->mii_media_active;
297 vte_mediachange(struct ifnet *ifp)
299 struct vte_softc *sc;
304 error = vte_mediachange_locked(ifp);
310 vte_mediachange_locked(struct ifnet *ifp)
312 struct vte_softc *sc;
313 struct mii_data *mii;
314 struct mii_softc *miisc;
318 mii = device_get_softc(sc->vte_miibus);
319 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
321 error = mii_mediachg(mii);
326 static const struct vte_ident *
327 vte_find_ident(device_t dev)
329 const struct vte_ident *ident;
330 uint16_t vendor, devid;
332 vendor = pci_get_vendor(dev);
333 devid = pci_get_device(dev);
334 for (ident = vte_ident_table; ident->name != NULL; ident++) {
335 if (vendor == ident->vendorid && devid == ident->deviceid)
343 vte_probe(device_t dev)
345 const struct vte_ident *ident;
347 ident = vte_find_ident(dev);
349 device_set_desc(dev, ident->name);
350 return (BUS_PROBE_DEFAULT);
357 vte_get_macaddr(struct vte_softc *sc)
362 * It seems there is no way to reload station address and
363 * it is supposed to be set by BIOS.
365 mid = CSR_READ_2(sc, VTE_MID0L);
366 sc->vte_eaddr[0] = (mid >> 0) & 0xFF;
367 sc->vte_eaddr[1] = (mid >> 8) & 0xFF;
368 mid = CSR_READ_2(sc, VTE_MID0M);
369 sc->vte_eaddr[2] = (mid >> 0) & 0xFF;
370 sc->vte_eaddr[3] = (mid >> 8) & 0xFF;
371 mid = CSR_READ_2(sc, VTE_MID0H);
372 sc->vte_eaddr[4] = (mid >> 0) & 0xFF;
373 sc->vte_eaddr[5] = (mid >> 8) & 0xFF;
377 vte_attach(device_t dev)
379 struct vte_softc *sc;
385 sc = device_get_softc(dev);
388 mtx_init(&sc->vte_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
390 callout_init_mtx(&sc->vte_tick_ch, &sc->vte_mtx, 0);
391 sc->vte_ident = vte_find_ident(dev);
393 /* Map the device. */
394 pci_enable_busmaster(dev);
395 sc->vte_res_id = PCIR_BAR(1);
396 sc->vte_res_type = SYS_RES_MEMORY;
397 sc->vte_res = bus_alloc_resource_any(dev, sc->vte_res_type,
398 &sc->vte_res_id, RF_ACTIVE);
399 if (sc->vte_res == NULL) {
400 sc->vte_res_id = PCIR_BAR(0);
401 sc->vte_res_type = SYS_RES_IOPORT;
402 sc->vte_res = bus_alloc_resource_any(dev, sc->vte_res_type,
403 &sc->vte_res_id, RF_ACTIVE);
404 if (sc->vte_res == NULL) {
405 device_printf(dev, "cannot map memory/ports.\n");
406 mtx_destroy(&sc->vte_mtx);
411 device_printf(dev, "using %s space register mapping\n",
412 sc->vte_res_type == SYS_RES_MEMORY ? "memory" : "I/O");
413 device_printf(dev, "MAC Identifier : 0x%04x\n",
414 CSR_READ_2(sc, VTE_MACID));
415 macid = CSR_READ_2(sc, VTE_MACID_REV);
416 device_printf(dev, "MAC Id. 0x%02x, Rev. 0x%02x\n",
417 (macid & VTE_MACID_MASK) >> VTE_MACID_SHIFT,
418 (macid & VTE_MACID_REV_MASK) >> VTE_MACID_REV_SHIFT);
422 sc->vte_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
423 RF_SHAREABLE | RF_ACTIVE);
424 if (sc->vte_irq == NULL) {
425 device_printf(dev, "cannot allocate IRQ resources.\n");
430 /* Reset the ethernet controller. */
433 if ((error = vte_dma_alloc(sc)) != 0)
436 /* Create device sysctl node. */
439 /* Load station address. */
442 ifp = sc->vte_ifp = if_alloc(IFT_ETHER);
444 device_printf(dev, "cannot allocate ifnet structure.\n");
450 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
451 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
452 ifp->if_ioctl = vte_ioctl;
453 ifp->if_start = vte_start;
454 ifp->if_init = vte_init;
455 ifp->if_get_counter = vte_get_counter;
456 ifp->if_snd.ifq_drv_maxlen = VTE_TX_RING_CNT - 1;
457 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
458 IFQ_SET_READY(&ifp->if_snd);
462 * BIOS would have initialized VTE_MPSCCR to catch PHY
463 * status changes so driver may be able to extract
464 * configured PHY address. Since it's common to see BIOS
465 * fails to initialize the register(including the sample
466 * board I have), let mii(4) probe it. This is more
467 * reliable than relying on BIOS's initialization.
469 * Advertising flow control capability to mii(4) was
470 * intentionally disabled due to severe problems in TX
471 * pause frame generation. See vte_rxeof() for more
474 error = mii_attach(dev, &sc->vte_miibus, ifp, vte_mediachange,
475 vte_mediastatus, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
477 device_printf(dev, "attaching PHYs failed\n");
481 ether_ifattach(ifp, sc->vte_eaddr);
483 /* VLAN capability setup. */
484 ifp->if_capabilities |= IFCAP_VLAN_MTU;
485 ifp->if_capenable = ifp->if_capabilities;
486 /* Tell the upper layer we support VLAN over-sized frames. */
487 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
489 error = bus_setup_intr(dev, sc->vte_irq, INTR_TYPE_NET | INTR_MPSAFE,
490 NULL, vte_intr, sc, &sc->vte_intrhand);
492 device_printf(dev, "could not set up interrupt handler.\n");
505 vte_detach(device_t dev)
507 struct vte_softc *sc;
510 sc = device_get_softc(dev);
513 if (device_is_attached(dev)) {
517 callout_drain(&sc->vte_tick_ch);
521 if (sc->vte_miibus != NULL) {
522 device_delete_child(dev, sc->vte_miibus);
523 sc->vte_miibus = NULL;
525 bus_generic_detach(dev);
527 if (sc->vte_intrhand != NULL) {
528 bus_teardown_intr(dev, sc->vte_irq, sc->vte_intrhand);
529 sc->vte_intrhand = NULL;
531 if (sc->vte_irq != NULL) {
532 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vte_irq);
535 if (sc->vte_res != NULL) {
536 bus_release_resource(dev, sc->vte_res_type, sc->vte_res_id,
545 mtx_destroy(&sc->vte_mtx);
550 #define VTE_SYSCTL_STAT_ADD32(c, h, n, p, d) \
551 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
554 vte_sysctl_node(struct vte_softc *sc)
556 struct sysctl_ctx_list *ctx;
557 struct sysctl_oid_list *child, *parent;
558 struct sysctl_oid *tree;
559 struct vte_hw_stats *stats;
562 stats = &sc->vte_stats;
563 ctx = device_get_sysctl_ctx(sc->vte_dev);
564 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->vte_dev));
566 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod",
567 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
568 &sc->vte_int_rx_mod, 0, sysctl_hw_vte_int_mod, "I",
569 "vte RX interrupt moderation");
570 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod",
571 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
572 &sc->vte_int_tx_mod, 0, sysctl_hw_vte_int_mod, "I",
573 "vte TX interrupt moderation");
574 /* Pull in device tunables. */
575 sc->vte_int_rx_mod = VTE_IM_RX_BUNDLE_DEFAULT;
576 error = resource_int_value(device_get_name(sc->vte_dev),
577 device_get_unit(sc->vte_dev), "int_rx_mod", &sc->vte_int_rx_mod);
579 if (sc->vte_int_rx_mod < VTE_IM_BUNDLE_MIN ||
580 sc->vte_int_rx_mod > VTE_IM_BUNDLE_MAX) {
581 device_printf(sc->vte_dev, "int_rx_mod value out of "
582 "range; using default: %d\n",
583 VTE_IM_RX_BUNDLE_DEFAULT);
584 sc->vte_int_rx_mod = VTE_IM_RX_BUNDLE_DEFAULT;
588 sc->vte_int_tx_mod = VTE_IM_TX_BUNDLE_DEFAULT;
589 error = resource_int_value(device_get_name(sc->vte_dev),
590 device_get_unit(sc->vte_dev), "int_tx_mod", &sc->vte_int_tx_mod);
592 if (sc->vte_int_tx_mod < VTE_IM_BUNDLE_MIN ||
593 sc->vte_int_tx_mod > VTE_IM_BUNDLE_MAX) {
594 device_printf(sc->vte_dev, "int_tx_mod value out of "
595 "range; using default: %d\n",
596 VTE_IM_TX_BUNDLE_DEFAULT);
597 sc->vte_int_tx_mod = VTE_IM_TX_BUNDLE_DEFAULT;
601 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats",
602 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "VTE statistics");
603 parent = SYSCTL_CHILDREN(tree);
606 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx",
607 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX MAC statistics");
608 child = SYSCTL_CHILDREN(tree);
609 VTE_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
610 &stats->rx_frames, "Good frames");
611 VTE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
612 &stats->rx_bcast_frames, "Good broadcast frames");
613 VTE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
614 &stats->rx_mcast_frames, "Good multicast frames");
615 VTE_SYSCTL_STAT_ADD32(ctx, child, "runt",
616 &stats->rx_runts, "Too short frames");
617 VTE_SYSCTL_STAT_ADD32(ctx, child, "crc_errs",
618 &stats->rx_crcerrs, "CRC errors");
619 VTE_SYSCTL_STAT_ADD32(ctx, child, "long_frames",
620 &stats->rx_long_frames,
621 "Frames that have longer length than maximum packet length");
622 VTE_SYSCTL_STAT_ADD32(ctx, child, "fifo_full",
623 &stats->rx_fifo_full, "FIFO full");
624 VTE_SYSCTL_STAT_ADD32(ctx, child, "desc_unavail",
625 &stats->rx_desc_unavail, "Descriptor unavailable frames");
626 VTE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames",
627 &stats->rx_pause_frames, "Pause control frames");
630 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx",
631 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX MAC statistics");
632 child = SYSCTL_CHILDREN(tree);
633 VTE_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
634 &stats->tx_frames, "Good frames");
635 VTE_SYSCTL_STAT_ADD32(ctx, child, "underruns",
636 &stats->tx_underruns, "FIFO underruns");
637 VTE_SYSCTL_STAT_ADD32(ctx, child, "late_colls",
638 &stats->tx_late_colls, "Late collisions");
639 VTE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames",
640 &stats->tx_pause_frames, "Pause control frames");
643 #undef VTE_SYSCTL_STAT_ADD32
645 struct vte_dmamap_arg {
646 bus_addr_t vte_busaddr;
650 vte_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
652 struct vte_dmamap_arg *ctx;
657 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
659 ctx = (struct vte_dmamap_arg *)arg;
660 ctx->vte_busaddr = segs[0].ds_addr;
664 vte_dma_alloc(struct vte_softc *sc)
666 struct vte_txdesc *txd;
667 struct vte_rxdesc *rxd;
668 struct vte_dmamap_arg ctx;
671 /* Create parent DMA tag. */
672 error = bus_dma_tag_create(
673 bus_get_dma_tag(sc->vte_dev), /* parent */
674 1, 0, /* alignment, boundary */
675 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
676 BUS_SPACE_MAXADDR, /* highaddr */
677 NULL, NULL, /* filter, filterarg */
678 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
680 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
682 NULL, NULL, /* lockfunc, lockarg */
683 &sc->vte_cdata.vte_parent_tag);
685 device_printf(sc->vte_dev,
686 "could not create parent DMA tag.\n");
690 /* Create DMA tag for TX descriptor ring. */
691 error = bus_dma_tag_create(
692 sc->vte_cdata.vte_parent_tag, /* parent */
693 VTE_TX_RING_ALIGN, 0, /* alignment, boundary */
694 BUS_SPACE_MAXADDR, /* lowaddr */
695 BUS_SPACE_MAXADDR, /* highaddr */
696 NULL, NULL, /* filter, filterarg */
697 VTE_TX_RING_SZ, /* maxsize */
699 VTE_TX_RING_SZ, /* maxsegsize */
701 NULL, NULL, /* lockfunc, lockarg */
702 &sc->vte_cdata.vte_tx_ring_tag);
704 device_printf(sc->vte_dev,
705 "could not create TX ring DMA tag.\n");
709 /* Create DMA tag for RX free descriptor ring. */
710 error = bus_dma_tag_create(
711 sc->vte_cdata.vte_parent_tag, /* parent */
712 VTE_RX_RING_ALIGN, 0, /* alignment, boundary */
713 BUS_SPACE_MAXADDR, /* lowaddr */
714 BUS_SPACE_MAXADDR, /* highaddr */
715 NULL, NULL, /* filter, filterarg */
716 VTE_RX_RING_SZ, /* maxsize */
718 VTE_RX_RING_SZ, /* maxsegsize */
720 NULL, NULL, /* lockfunc, lockarg */
721 &sc->vte_cdata.vte_rx_ring_tag);
723 device_printf(sc->vte_dev,
724 "could not create RX ring DMA tag.\n");
728 /* Allocate DMA'able memory and load the DMA map for TX ring. */
729 error = bus_dmamem_alloc(sc->vte_cdata.vte_tx_ring_tag,
730 (void **)&sc->vte_cdata.vte_tx_ring,
731 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
732 &sc->vte_cdata.vte_tx_ring_map);
734 device_printf(sc->vte_dev,
735 "could not allocate DMA'able memory for TX ring.\n");
739 error = bus_dmamap_load(sc->vte_cdata.vte_tx_ring_tag,
740 sc->vte_cdata.vte_tx_ring_map, sc->vte_cdata.vte_tx_ring,
741 VTE_TX_RING_SZ, vte_dmamap_cb, &ctx, 0);
742 if (error != 0 || ctx.vte_busaddr == 0) {
743 device_printf(sc->vte_dev,
744 "could not load DMA'able memory for TX ring.\n");
747 sc->vte_cdata.vte_tx_ring_paddr = ctx.vte_busaddr;
749 /* Allocate DMA'able memory and load the DMA map for RX ring. */
750 error = bus_dmamem_alloc(sc->vte_cdata.vte_rx_ring_tag,
751 (void **)&sc->vte_cdata.vte_rx_ring,
752 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
753 &sc->vte_cdata.vte_rx_ring_map);
755 device_printf(sc->vte_dev,
756 "could not allocate DMA'able memory for RX ring.\n");
760 error = bus_dmamap_load(sc->vte_cdata.vte_rx_ring_tag,
761 sc->vte_cdata.vte_rx_ring_map, sc->vte_cdata.vte_rx_ring,
762 VTE_RX_RING_SZ, vte_dmamap_cb, &ctx, 0);
763 if (error != 0 || ctx.vte_busaddr == 0) {
764 device_printf(sc->vte_dev,
765 "could not load DMA'able memory for RX ring.\n");
768 sc->vte_cdata.vte_rx_ring_paddr = ctx.vte_busaddr;
770 /* Create TX buffer parent tag. */
771 error = bus_dma_tag_create(
772 bus_get_dma_tag(sc->vte_dev), /* parent */
773 1, 0, /* alignment, boundary */
774 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
775 BUS_SPACE_MAXADDR, /* highaddr */
776 NULL, NULL, /* filter, filterarg */
777 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
779 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
781 NULL, NULL, /* lockfunc, lockarg */
782 &sc->vte_cdata.vte_buffer_tag);
784 device_printf(sc->vte_dev,
785 "could not create parent buffer DMA tag.\n");
789 /* Create DMA tag for TX buffers. */
790 error = bus_dma_tag_create(
791 sc->vte_cdata.vte_buffer_tag, /* parent */
792 1, 0, /* alignment, boundary */
793 BUS_SPACE_MAXADDR, /* lowaddr */
794 BUS_SPACE_MAXADDR, /* highaddr */
795 NULL, NULL, /* filter, filterarg */
796 MCLBYTES, /* maxsize */
798 MCLBYTES, /* maxsegsize */
800 NULL, NULL, /* lockfunc, lockarg */
801 &sc->vte_cdata.vte_tx_tag);
803 device_printf(sc->vte_dev, "could not create TX DMA tag.\n");
807 /* Create DMA tag for RX buffers. */
808 error = bus_dma_tag_create(
809 sc->vte_cdata.vte_buffer_tag, /* parent */
810 VTE_RX_BUF_ALIGN, 0, /* alignment, boundary */
811 BUS_SPACE_MAXADDR, /* lowaddr */
812 BUS_SPACE_MAXADDR, /* highaddr */
813 NULL, NULL, /* filter, filterarg */
814 MCLBYTES, /* maxsize */
816 MCLBYTES, /* maxsegsize */
818 NULL, NULL, /* lockfunc, lockarg */
819 &sc->vte_cdata.vte_rx_tag);
821 device_printf(sc->vte_dev, "could not create RX DMA tag.\n");
824 /* Create DMA maps for TX buffers. */
825 for (i = 0; i < VTE_TX_RING_CNT; i++) {
826 txd = &sc->vte_cdata.vte_txdesc[i];
828 txd->tx_dmamap = NULL;
829 error = bus_dmamap_create(sc->vte_cdata.vte_tx_tag, 0,
832 device_printf(sc->vte_dev,
833 "could not create TX dmamap.\n");
837 /* Create DMA maps for RX buffers. */
838 if ((error = bus_dmamap_create(sc->vte_cdata.vte_rx_tag, 0,
839 &sc->vte_cdata.vte_rx_sparemap)) != 0) {
840 device_printf(sc->vte_dev,
841 "could not create spare RX dmamap.\n");
844 for (i = 0; i < VTE_RX_RING_CNT; i++) {
845 rxd = &sc->vte_cdata.vte_rxdesc[i];
847 rxd->rx_dmamap = NULL;
848 error = bus_dmamap_create(sc->vte_cdata.vte_rx_tag, 0,
851 device_printf(sc->vte_dev,
852 "could not create RX dmamap.\n");
862 vte_dma_free(struct vte_softc *sc)
864 struct vte_txdesc *txd;
865 struct vte_rxdesc *rxd;
869 if (sc->vte_cdata.vte_tx_tag != NULL) {
870 for (i = 0; i < VTE_TX_RING_CNT; i++) {
871 txd = &sc->vte_cdata.vte_txdesc[i];
872 if (txd->tx_dmamap != NULL) {
873 bus_dmamap_destroy(sc->vte_cdata.vte_tx_tag,
875 txd->tx_dmamap = NULL;
878 bus_dma_tag_destroy(sc->vte_cdata.vte_tx_tag);
879 sc->vte_cdata.vte_tx_tag = NULL;
882 if (sc->vte_cdata.vte_rx_tag != NULL) {
883 for (i = 0; i < VTE_RX_RING_CNT; i++) {
884 rxd = &sc->vte_cdata.vte_rxdesc[i];
885 if (rxd->rx_dmamap != NULL) {
886 bus_dmamap_destroy(sc->vte_cdata.vte_rx_tag,
888 rxd->rx_dmamap = NULL;
891 if (sc->vte_cdata.vte_rx_sparemap != NULL) {
892 bus_dmamap_destroy(sc->vte_cdata.vte_rx_tag,
893 sc->vte_cdata.vte_rx_sparemap);
894 sc->vte_cdata.vte_rx_sparemap = NULL;
896 bus_dma_tag_destroy(sc->vte_cdata.vte_rx_tag);
897 sc->vte_cdata.vte_rx_tag = NULL;
899 /* TX descriptor ring. */
900 if (sc->vte_cdata.vte_tx_ring_tag != NULL) {
901 if (sc->vte_cdata.vte_tx_ring_paddr != 0)
902 bus_dmamap_unload(sc->vte_cdata.vte_tx_ring_tag,
903 sc->vte_cdata.vte_tx_ring_map);
904 if (sc->vte_cdata.vte_tx_ring != NULL)
905 bus_dmamem_free(sc->vte_cdata.vte_tx_ring_tag,
906 sc->vte_cdata.vte_tx_ring,
907 sc->vte_cdata.vte_tx_ring_map);
908 sc->vte_cdata.vte_tx_ring = NULL;
909 sc->vte_cdata.vte_tx_ring_paddr = 0;
910 bus_dma_tag_destroy(sc->vte_cdata.vte_tx_ring_tag);
911 sc->vte_cdata.vte_tx_ring_tag = NULL;
914 if (sc->vte_cdata.vte_rx_ring_tag != NULL) {
915 if (sc->vte_cdata.vte_rx_ring_paddr != 0)
916 bus_dmamap_unload(sc->vte_cdata.vte_rx_ring_tag,
917 sc->vte_cdata.vte_rx_ring_map);
918 if (sc->vte_cdata.vte_rx_ring != NULL)
919 bus_dmamem_free(sc->vte_cdata.vte_rx_ring_tag,
920 sc->vte_cdata.vte_rx_ring,
921 sc->vte_cdata.vte_rx_ring_map);
922 sc->vte_cdata.vte_rx_ring = NULL;
923 sc->vte_cdata.vte_rx_ring_paddr = 0;
924 bus_dma_tag_destroy(sc->vte_cdata.vte_rx_ring_tag);
925 sc->vte_cdata.vte_rx_ring_tag = NULL;
927 if (sc->vte_cdata.vte_buffer_tag != NULL) {
928 bus_dma_tag_destroy(sc->vte_cdata.vte_buffer_tag);
929 sc->vte_cdata.vte_buffer_tag = NULL;
931 if (sc->vte_cdata.vte_parent_tag != NULL) {
932 bus_dma_tag_destroy(sc->vte_cdata.vte_parent_tag);
933 sc->vte_cdata.vte_parent_tag = NULL;
938 vte_shutdown(device_t dev)
941 return (vte_suspend(dev));
945 vte_suspend(device_t dev)
947 struct vte_softc *sc;
950 sc = device_get_softc(dev);
954 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
962 vte_resume(device_t dev)
964 struct vte_softc *sc;
967 sc = device_get_softc(dev);
971 if ((ifp->if_flags & IFF_UP) != 0) {
972 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
980 static struct vte_txdesc *
981 vte_encap(struct vte_softc *sc, struct mbuf **m_head)
983 struct vte_txdesc *txd;
985 bus_dma_segment_t txsegs[1];
986 int copy, error, nsegs, padlen;
990 M_ASSERTPKTHDR((*m_head));
992 txd = &sc->vte_cdata.vte_txdesc[sc->vte_cdata.vte_tx_prod];
995 * Controller doesn't auto-pad, so we have to make sure pad
996 * short frames out to the minimum frame length.
998 if (m->m_pkthdr.len < VTE_MIN_FRAMELEN)
999 padlen = VTE_MIN_FRAMELEN - m->m_pkthdr.len;
1004 * Controller does not support multi-fragmented TX buffers.
1005 * Controller spends most of its TX processing time in
1006 * de-fragmenting TX buffers. Either faster CPU or more
1007 * advanced controller DMA engine is required to speed up
1008 * TX path processing.
1009 * To mitigate the de-fragmenting issue, perform deep copy
1010 * from fragmented mbuf chains to a pre-allocated mbuf
1011 * cluster with extra cost of kernel memory. For frames
1012 * that is composed of single TX buffer, the deep copy is
1015 if (tx_deep_copy != 0) {
1017 if (m->m_next != NULL)
1019 if (padlen > 0 && (M_WRITABLE(m) == 0 ||
1020 padlen > M_TRAILINGSPACE(m)))
1023 /* Avoid expensive m_defrag(9) and do deep copy. */
1024 n = sc->vte_cdata.vte_txmbufs[sc->vte_cdata.vte_tx_prod];
1025 m_copydata(m, 0, m->m_pkthdr.len, mtod(n, char *));
1026 n->m_pkthdr.len = m->m_pkthdr.len;
1027 n->m_len = m->m_pkthdr.len;
1029 txd->tx_flags |= VTE_TXMBUF;
1033 /* Zero out the bytes in the pad area. */
1034 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen);
1035 m->m_pkthdr.len += padlen;
1036 m->m_len = m->m_pkthdr.len;
1039 if (M_WRITABLE(m) == 0) {
1040 if (m->m_next != NULL || padlen > 0) {
1041 /* Get a writable copy. */
1042 m = m_dup(*m_head, M_NOWAIT);
1043 /* Release original mbuf chains. */
1053 if (m->m_next != NULL) {
1054 m = m_defrag(*m_head, M_NOWAIT);
1064 if (M_TRAILINGSPACE(m) < padlen) {
1065 m = m_defrag(*m_head, M_NOWAIT);
1073 /* Zero out the bytes in the pad area. */
1074 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen);
1075 m->m_pkthdr.len += padlen;
1076 m->m_len = m->m_pkthdr.len;
1080 error = bus_dmamap_load_mbuf_sg(sc->vte_cdata.vte_tx_tag,
1081 txd->tx_dmamap, m, txsegs, &nsegs, 0);
1083 txd->tx_flags &= ~VTE_TXMBUF;
1086 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1087 bus_dmamap_sync(sc->vte_cdata.vte_tx_tag, txd->tx_dmamap,
1088 BUS_DMASYNC_PREWRITE);
1090 txd->tx_desc->dtlen = htole16(VTE_TX_LEN(txsegs[0].ds_len));
1091 txd->tx_desc->dtbp = htole32(txsegs[0].ds_addr);
1092 sc->vte_cdata.vte_tx_cnt++;
1093 /* Update producer index. */
1094 VTE_DESC_INC(sc->vte_cdata.vte_tx_prod, VTE_TX_RING_CNT);
1096 /* Finally hand over ownership to controller. */
1097 txd->tx_desc->dtst = htole16(VTE_DTST_TX_OWN);
1104 vte_start(struct ifnet *ifp)
1106 struct vte_softc *sc;
1110 vte_start_locked(sc);
1115 vte_start_locked(struct vte_softc *sc)
1118 struct vte_txdesc *txd;
1119 struct mbuf *m_head;
1124 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1125 IFF_DRV_RUNNING || (sc->vte_flags & VTE_FLAG_LINK) == 0)
1128 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) {
1129 /* Reserve one free TX descriptor. */
1130 if (sc->vte_cdata.vte_tx_cnt >= VTE_TX_RING_CNT - 1) {
1131 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1134 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1138 * Pack the data into the transmit ring. If we
1139 * don't have room, set the OACTIVE flag and wait
1140 * for the NIC to drain the ring.
1142 if ((txd = vte_encap(sc, &m_head)) == NULL) {
1144 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1150 * If there's a BPF listener, bounce a copy of this frame
1153 ETHER_BPF_MTAP(ifp, m_head);
1154 /* Free consumed TX frame. */
1155 if ((txd->tx_flags & VTE_TXMBUF) != 0)
1160 bus_dmamap_sync(sc->vte_cdata.vte_tx_ring_tag,
1161 sc->vte_cdata.vte_tx_ring_map, BUS_DMASYNC_PREREAD |
1162 BUS_DMASYNC_PREWRITE);
1163 CSR_WRITE_2(sc, VTE_TX_POLL, TX_POLL_START);
1164 sc->vte_watchdog_timer = VTE_TX_TIMEOUT;
1169 vte_watchdog(struct vte_softc *sc)
1173 VTE_LOCK_ASSERT(sc);
1175 if (sc->vte_watchdog_timer == 0 || --sc->vte_watchdog_timer)
1179 if_printf(sc->vte_ifp, "watchdog timeout -- resetting\n");
1180 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1181 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1182 vte_init_locked(sc);
1183 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1184 vte_start_locked(sc);
1188 vte_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1190 struct vte_softc *sc;
1192 struct mii_data *mii;
1196 ifr = (struct ifreq *)data;
1201 if ((ifp->if_flags & IFF_UP) != 0) {
1202 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
1203 ((ifp->if_flags ^ sc->vte_if_flags) &
1204 (IFF_PROMISC | IFF_ALLMULTI)) != 0)
1207 vte_init_locked(sc);
1208 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1210 sc->vte_if_flags = ifp->if_flags;
1216 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1222 mii = device_get_softc(sc->vte_miibus);
1223 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1226 error = ether_ioctl(ifp, cmd, data);
1234 vte_mac_config(struct vte_softc *sc)
1236 struct mii_data *mii;
1239 VTE_LOCK_ASSERT(sc);
1241 mii = device_get_softc(sc->vte_miibus);
1242 mcr = CSR_READ_2(sc, VTE_MCR0);
1243 mcr &= ~(MCR0_FC_ENB | MCR0_FULL_DUPLEX);
1244 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1245 mcr |= MCR0_FULL_DUPLEX;
1247 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
1250 * The data sheet is not clear whether the controller
1251 * honors received pause frames or not. The is no
1252 * separate control bit for RX pause frame so just
1253 * enable MCR0_FC_ENB bit.
1255 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
1259 CSR_WRITE_2(sc, VTE_MCR0, mcr);
1263 vte_stats_clear(struct vte_softc *sc)
1266 /* Reading counter registers clears its contents. */
1267 CSR_READ_2(sc, VTE_CNT_RX_DONE);
1268 CSR_READ_2(sc, VTE_CNT_MECNT0);
1269 CSR_READ_2(sc, VTE_CNT_MECNT1);
1270 CSR_READ_2(sc, VTE_CNT_MECNT2);
1271 CSR_READ_2(sc, VTE_CNT_MECNT3);
1272 CSR_READ_2(sc, VTE_CNT_TX_DONE);
1273 CSR_READ_2(sc, VTE_CNT_MECNT4);
1274 CSR_READ_2(sc, VTE_CNT_PAUSE);
1278 vte_stats_update(struct vte_softc *sc)
1280 struct vte_hw_stats *stat;
1283 VTE_LOCK_ASSERT(sc);
1285 stat = &sc->vte_stats;
1287 CSR_READ_2(sc, VTE_MECISR);
1289 stat->rx_frames += CSR_READ_2(sc, VTE_CNT_RX_DONE);
1290 value = CSR_READ_2(sc, VTE_CNT_MECNT0);
1291 stat->rx_bcast_frames += (value >> 8);
1292 stat->rx_mcast_frames += (value & 0xFF);
1293 value = CSR_READ_2(sc, VTE_CNT_MECNT1);
1294 stat->rx_runts += (value >> 8);
1295 stat->rx_crcerrs += (value & 0xFF);
1296 value = CSR_READ_2(sc, VTE_CNT_MECNT2);
1297 stat->rx_long_frames += (value & 0xFF);
1298 value = CSR_READ_2(sc, VTE_CNT_MECNT3);
1299 stat->rx_fifo_full += (value >> 8);
1300 stat->rx_desc_unavail += (value & 0xFF);
1303 stat->tx_frames += CSR_READ_2(sc, VTE_CNT_TX_DONE);
1304 value = CSR_READ_2(sc, VTE_CNT_MECNT4);
1305 stat->tx_underruns += (value >> 8);
1306 stat->tx_late_colls += (value & 0xFF);
1308 value = CSR_READ_2(sc, VTE_CNT_PAUSE);
1309 stat->tx_pause_frames += (value >> 8);
1310 stat->rx_pause_frames += (value & 0xFF);
1314 vte_get_counter(struct ifnet *ifp, ift_counter cnt)
1316 struct vte_softc *sc;
1317 struct vte_hw_stats *stat;
1319 sc = if_getsoftc(ifp);
1320 stat = &sc->vte_stats;
1323 case IFCOUNTER_OPACKETS:
1324 return (stat->tx_frames);
1325 case IFCOUNTER_COLLISIONS:
1326 return (stat->tx_late_colls);
1327 case IFCOUNTER_OERRORS:
1328 return (stat->tx_late_colls + stat->tx_underruns);
1329 case IFCOUNTER_IPACKETS:
1330 return (stat->rx_frames);
1331 case IFCOUNTER_IERRORS:
1332 return (stat->rx_crcerrs + stat->rx_runts +
1333 stat->rx_long_frames + stat->rx_fifo_full);
1335 return (if_get_counter_default(ifp, cnt));
1342 struct vte_softc *sc;
1347 sc = (struct vte_softc *)arg;
1351 /* Reading VTE_MISR acknowledges interrupts. */
1352 status = CSR_READ_2(sc, VTE_MISR);
1353 if ((status & VTE_INTRS) == 0) {
1359 /* Disable interrupts. */
1360 CSR_WRITE_2(sc, VTE_MIER, 0);
1361 for (n = 8; (status & VTE_INTRS) != 0;) {
1362 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1364 if ((status & (MISR_RX_DONE | MISR_RX_DESC_UNAVAIL |
1365 MISR_RX_FIFO_FULL)) != 0)
1367 if ((status & MISR_TX_DONE) != 0)
1369 if ((status & MISR_EVENT_CNT_OFLOW) != 0)
1370 vte_stats_update(sc);
1371 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1372 vte_start_locked(sc);
1374 status = CSR_READ_2(sc, VTE_MISR);
1379 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1380 /* Re-enable interrupts. */
1381 CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS);
1387 vte_txeof(struct vte_softc *sc)
1390 struct vte_txdesc *txd;
1394 VTE_LOCK_ASSERT(sc);
1398 if (sc->vte_cdata.vte_tx_cnt == 0)
1400 bus_dmamap_sync(sc->vte_cdata.vte_tx_ring_tag,
1401 sc->vte_cdata.vte_tx_ring_map, BUS_DMASYNC_POSTREAD |
1402 BUS_DMASYNC_POSTWRITE);
1403 cons = sc->vte_cdata.vte_tx_cons;
1405 * Go through our TX list and free mbufs for those
1406 * frames which have been transmitted.
1408 for (prog = 0; sc->vte_cdata.vte_tx_cnt > 0; prog++) {
1409 txd = &sc->vte_cdata.vte_txdesc[cons];
1410 status = le16toh(txd->tx_desc->dtst);
1411 if ((status & VTE_DTST_TX_OWN) != 0)
1413 sc->vte_cdata.vte_tx_cnt--;
1414 /* Reclaim transmitted mbufs. */
1415 bus_dmamap_sync(sc->vte_cdata.vte_tx_tag, txd->tx_dmamap,
1416 BUS_DMASYNC_POSTWRITE);
1417 bus_dmamap_unload(sc->vte_cdata.vte_tx_tag, txd->tx_dmamap);
1418 if ((txd->tx_flags & VTE_TXMBUF) == 0)
1420 txd->tx_flags &= ~VTE_TXMBUF;
1423 VTE_DESC_INC(cons, VTE_TX_RING_CNT);
1427 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1428 sc->vte_cdata.vte_tx_cons = cons;
1430 * Unarm watchdog timer only when there is no pending
1431 * frames in TX queue.
1433 if (sc->vte_cdata.vte_tx_cnt == 0)
1434 sc->vte_watchdog_timer = 0;
1439 vte_newbuf(struct vte_softc *sc, struct vte_rxdesc *rxd)
1442 bus_dma_segment_t segs[1];
1446 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1449 m->m_len = m->m_pkthdr.len = MCLBYTES;
1450 m_adj(m, sizeof(uint32_t));
1452 if (bus_dmamap_load_mbuf_sg(sc->vte_cdata.vte_rx_tag,
1453 sc->vte_cdata.vte_rx_sparemap, m, segs, &nsegs, 0) != 0) {
1457 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1459 if (rxd->rx_m != NULL) {
1460 bus_dmamap_sync(sc->vte_cdata.vte_rx_tag, rxd->rx_dmamap,
1461 BUS_DMASYNC_POSTREAD);
1462 bus_dmamap_unload(sc->vte_cdata.vte_rx_tag, rxd->rx_dmamap);
1464 map = rxd->rx_dmamap;
1465 rxd->rx_dmamap = sc->vte_cdata.vte_rx_sparemap;
1466 sc->vte_cdata.vte_rx_sparemap = map;
1467 bus_dmamap_sync(sc->vte_cdata.vte_rx_tag, rxd->rx_dmamap,
1468 BUS_DMASYNC_PREREAD);
1470 rxd->rx_desc->drbp = htole32(segs[0].ds_addr);
1471 rxd->rx_desc->drlen = htole16(VTE_RX_LEN(segs[0].ds_len));
1472 rxd->rx_desc->drst = htole16(VTE_DRST_RX_OWN);
1478 * It's not supposed to see this controller on strict-alignment
1479 * architectures but make it work for completeness.
1481 #ifndef __NO_STRICT_ALIGNMENT
1482 static struct mbuf *
1483 vte_fixup_rx(struct ifnet *ifp, struct mbuf *m)
1485 uint16_t *src, *dst;
1488 src = mtod(m, uint16_t *);
1491 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
1493 m->m_data -= ETHER_ALIGN;
1499 vte_rxeof(struct vte_softc *sc)
1502 struct vte_rxdesc *rxd;
1504 uint16_t status, total_len;
1507 bus_dmamap_sync(sc->vte_cdata.vte_rx_ring_tag,
1508 sc->vte_cdata.vte_rx_ring_map, BUS_DMASYNC_POSTREAD |
1509 BUS_DMASYNC_POSTWRITE);
1510 cons = sc->vte_cdata.vte_rx_cons;
1512 for (prog = 0; (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0; prog++,
1513 VTE_DESC_INC(cons, VTE_RX_RING_CNT)) {
1514 rxd = &sc->vte_cdata.vte_rxdesc[cons];
1515 status = le16toh(rxd->rx_desc->drst);
1516 if ((status & VTE_DRST_RX_OWN) != 0)
1518 total_len = VTE_RX_LEN(le16toh(rxd->rx_desc->drlen));
1520 if ((status & VTE_DRST_RX_OK) == 0) {
1521 /* Discard errored frame. */
1522 rxd->rx_desc->drlen =
1523 htole16(MCLBYTES - sizeof(uint32_t));
1524 rxd->rx_desc->drst = htole16(VTE_DRST_RX_OWN);
1527 if (vte_newbuf(sc, rxd) != 0) {
1528 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1529 rxd->rx_desc->drlen =
1530 htole16(MCLBYTES - sizeof(uint32_t));
1531 rxd->rx_desc->drst = htole16(VTE_DRST_RX_OWN);
1536 * It seems there is no way to strip FCS bytes.
1538 m->m_pkthdr.len = m->m_len = total_len - ETHER_CRC_LEN;
1539 m->m_pkthdr.rcvif = ifp;
1540 #ifndef __NO_STRICT_ALIGNMENT
1541 vte_fixup_rx(ifp, m);
1544 (*ifp->if_input)(ifp, m);
1549 /* Update the consumer index. */
1550 sc->vte_cdata.vte_rx_cons = cons;
1552 * Sync updated RX descriptors such that controller see
1553 * modified RX buffer addresses.
1555 bus_dmamap_sync(sc->vte_cdata.vte_rx_ring_tag,
1556 sc->vte_cdata.vte_rx_ring_map,
1557 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1560 * Update residue counter. Controller does not
1561 * keep track of number of available RX descriptors
1562 * such that driver should have to update VTE_MRDCR
1563 * to make controller know how many free RX
1564 * descriptors were added to controller. This is
1565 * a similar mechanism used in VIA velocity
1566 * controllers and it indicates controller just
1567 * polls OWN bit of current RX descriptor pointer.
1568 * A couple of severe issues were seen on sample
1569 * board where the controller continuously emits TX
1570 * pause frames once RX pause threshold crossed.
1571 * Once triggered it never recovered form that
1572 * state, I couldn't find a way to make it back to
1573 * work at least. This issue effectively
1574 * disconnected the system from network. Also, the
1575 * controller used 00:00:00:00:00:00 as source
1576 * station address of TX pause frame. Probably this
1577 * is one of reason why vendor recommends not to
1578 * enable flow control on R6040 controller.
1580 CSR_WRITE_2(sc, VTE_MRDCR, prog |
1581 (((VTE_RX_RING_CNT * 2) / 10) <<
1582 VTE_MRDCR_RX_PAUSE_THRESH_SHIFT));
1590 struct vte_softc *sc;
1591 struct mii_data *mii;
1593 sc = (struct vte_softc *)arg;
1595 VTE_LOCK_ASSERT(sc);
1597 mii = device_get_softc(sc->vte_miibus);
1599 vte_stats_update(sc);
1602 callout_reset(&sc->vte_tick_ch, hz, vte_tick, sc);
1606 vte_reset(struct vte_softc *sc)
1611 mcr = CSR_READ_2(sc, VTE_MCR1);
1612 CSR_WRITE_2(sc, VTE_MCR1, mcr | MCR1_MAC_RESET);
1613 for (i = VTE_RESET_TIMEOUT; i > 0; i--) {
1615 if ((CSR_READ_2(sc, VTE_MCR1) & MCR1_MAC_RESET) == 0)
1619 device_printf(sc->vte_dev, "reset timeout(0x%04x)!\n", mcr);
1621 * Follow the guide of vendor recommended way to reset MAC.
1622 * Vendor confirms relying on MCR1_MAC_RESET of VTE_MCR1 is
1623 * not reliable so manually reset internal state machine.
1625 CSR_WRITE_2(sc, VTE_MACSM, 0x0002);
1626 CSR_WRITE_2(sc, VTE_MACSM, 0);
1633 struct vte_softc *sc;
1635 sc = (struct vte_softc *)xsc;
1637 vte_init_locked(sc);
1642 vte_init_locked(struct vte_softc *sc)
1648 VTE_LOCK_ASSERT(sc);
1652 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1655 * Cancel any pending I/O.
1659 * Reset the chip to a known state.
1663 /* Initialize RX descriptors. */
1664 if (vte_init_rx_ring(sc) != 0) {
1665 device_printf(sc->vte_dev, "no memory for RX buffers.\n");
1669 if (vte_init_tx_ring(sc) != 0) {
1670 device_printf(sc->vte_dev, "no memory for TX buffers.\n");
1676 * Reprogram the station address. Controller supports up
1677 * to 4 different station addresses so driver programs the
1678 * first station address as its own ethernet address and
1679 * configure the remaining three addresses as perfect
1680 * multicast addresses.
1682 eaddr = IF_LLADDR(sc->vte_ifp);
1683 CSR_WRITE_2(sc, VTE_MID0L, eaddr[1] << 8 | eaddr[0]);
1684 CSR_WRITE_2(sc, VTE_MID0M, eaddr[3] << 8 | eaddr[2]);
1685 CSR_WRITE_2(sc, VTE_MID0H, eaddr[5] << 8 | eaddr[4]);
1687 /* Set TX descriptor base addresses. */
1688 paddr = sc->vte_cdata.vte_tx_ring_paddr;
1689 CSR_WRITE_2(sc, VTE_MTDSA1, paddr >> 16);
1690 CSR_WRITE_2(sc, VTE_MTDSA0, paddr & 0xFFFF);
1691 /* Set RX descriptor base addresses. */
1692 paddr = sc->vte_cdata.vte_rx_ring_paddr;
1693 CSR_WRITE_2(sc, VTE_MRDSA1, paddr >> 16);
1694 CSR_WRITE_2(sc, VTE_MRDSA0, paddr & 0xFFFF);
1696 * Initialize RX descriptor residue counter and set RX
1697 * pause threshold to 20% of available RX descriptors.
1698 * See comments on vte_rxeof() for details on flow control
1701 CSR_WRITE_2(sc, VTE_MRDCR, (VTE_RX_RING_CNT & VTE_MRDCR_RESIDUE_MASK) |
1702 (((VTE_RX_RING_CNT * 2) / 10) << VTE_MRDCR_RX_PAUSE_THRESH_SHIFT));
1705 * Always use maximum frame size that controller can
1706 * support. Otherwise received frames that has longer
1707 * frame length than vte(4) MTU would be silently dropped
1708 * in controller. This would break path-MTU discovery as
1709 * sender wouldn't get any responses from receiver. The
1710 * RX buffer size should be multiple of 4.
1711 * Note, jumbo frames are silently ignored by controller
1712 * and even MAC counters do not detect them.
1714 CSR_WRITE_2(sc, VTE_MRBSR, VTE_RX_BUF_SIZE_MAX);
1716 /* Configure FIFO. */
1717 CSR_WRITE_2(sc, VTE_MBCR, MBCR_FIFO_XFER_LENGTH_16 |
1718 MBCR_TX_FIFO_THRESH_64 | MBCR_RX_FIFO_THRESH_16 |
1719 MBCR_SDRAM_BUS_REQ_TIMER_DEFAULT);
1722 * Configure TX/RX MACs. Actual resolved duplex and flow
1723 * control configuration is done after detecting a valid
1724 * link. Note, we don't generate early interrupt here
1725 * as well since FreeBSD does not have interrupt latency
1726 * problems like Windows.
1728 CSR_WRITE_2(sc, VTE_MCR0, MCR0_ACCPT_LONG_PKT);
1730 * We manually keep track of PHY status changes to
1731 * configure resolved duplex and flow control since only
1732 * duplex configuration can be automatically reflected to
1735 CSR_WRITE_2(sc, VTE_MCR1, MCR1_PKT_LENGTH_1537 |
1736 MCR1_EXCESS_COL_RETRY_16);
1738 /* Initialize RX filter. */
1741 /* Disable TX/RX interrupt moderation control. */
1742 CSR_WRITE_2(sc, VTE_MRICR, 0);
1743 CSR_WRITE_2(sc, VTE_MTICR, 0);
1745 /* Enable MAC event counter interrupts. */
1746 CSR_WRITE_2(sc, VTE_MECIER, VTE_MECIER_INTRS);
1747 /* Clear MAC statistics. */
1748 vte_stats_clear(sc);
1750 /* Acknowledge all pending interrupts and clear it. */
1751 CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS);
1752 CSR_WRITE_2(sc, VTE_MISR, 0);
1754 sc->vte_flags &= ~VTE_FLAG_LINK;
1755 /* Switch to the current media. */
1756 vte_mediachange_locked(ifp);
1758 callout_reset(&sc->vte_tick_ch, hz, vte_tick, sc);
1760 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1761 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1765 vte_stop(struct vte_softc *sc)
1768 struct vte_txdesc *txd;
1769 struct vte_rxdesc *rxd;
1772 VTE_LOCK_ASSERT(sc);
1774 * Mark the interface down and cancel the watchdog timer.
1777 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1778 sc->vte_flags &= ~VTE_FLAG_LINK;
1779 callout_stop(&sc->vte_tick_ch);
1780 sc->vte_watchdog_timer = 0;
1781 vte_stats_update(sc);
1782 /* Disable interrupts. */
1783 CSR_WRITE_2(sc, VTE_MIER, 0);
1784 CSR_WRITE_2(sc, VTE_MECIER, 0);
1785 /* Stop RX/TX MACs. */
1787 /* Clear interrupts. */
1788 CSR_READ_2(sc, VTE_MISR);
1790 * Free TX/RX mbufs still in the queues.
1792 for (i = 0; i < VTE_RX_RING_CNT; i++) {
1793 rxd = &sc->vte_cdata.vte_rxdesc[i];
1794 if (rxd->rx_m != NULL) {
1795 bus_dmamap_sync(sc->vte_cdata.vte_rx_tag,
1796 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
1797 bus_dmamap_unload(sc->vte_cdata.vte_rx_tag,
1803 for (i = 0; i < VTE_TX_RING_CNT; i++) {
1804 txd = &sc->vte_cdata.vte_txdesc[i];
1805 if (txd->tx_m != NULL) {
1806 bus_dmamap_sync(sc->vte_cdata.vte_tx_tag,
1807 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
1808 bus_dmamap_unload(sc->vte_cdata.vte_tx_tag,
1810 if ((txd->tx_flags & VTE_TXMBUF) == 0)
1813 txd->tx_flags &= ~VTE_TXMBUF;
1816 /* Free TX mbuf pools used for deep copy. */
1817 for (i = 0; i < VTE_TX_RING_CNT; i++) {
1818 if (sc->vte_cdata.vte_txmbufs[i] != NULL) {
1819 m_freem(sc->vte_cdata.vte_txmbufs[i]);
1820 sc->vte_cdata.vte_txmbufs[i] = NULL;
1826 vte_start_mac(struct vte_softc *sc)
1831 VTE_LOCK_ASSERT(sc);
1833 /* Enable RX/TX MACs. */
1834 mcr = CSR_READ_2(sc, VTE_MCR0);
1835 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) !=
1836 (MCR0_RX_ENB | MCR0_TX_ENB)) {
1837 mcr |= MCR0_RX_ENB | MCR0_TX_ENB;
1838 CSR_WRITE_2(sc, VTE_MCR0, mcr);
1839 for (i = VTE_TIMEOUT; i > 0; i--) {
1840 mcr = CSR_READ_2(sc, VTE_MCR0);
1841 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) ==
1842 (MCR0_RX_ENB | MCR0_TX_ENB))
1847 device_printf(sc->vte_dev,
1848 "could not enable RX/TX MAC(0x%04x)!\n", mcr);
1853 vte_stop_mac(struct vte_softc *sc)
1858 VTE_LOCK_ASSERT(sc);
1860 /* Disable RX/TX MACs. */
1861 mcr = CSR_READ_2(sc, VTE_MCR0);
1862 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) != 0) {
1863 mcr &= ~(MCR0_RX_ENB | MCR0_TX_ENB);
1864 CSR_WRITE_2(sc, VTE_MCR0, mcr);
1865 for (i = VTE_TIMEOUT; i > 0; i--) {
1866 mcr = CSR_READ_2(sc, VTE_MCR0);
1867 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) == 0)
1872 device_printf(sc->vte_dev,
1873 "could not disable RX/TX MAC(0x%04x)!\n", mcr);
1878 vte_init_tx_ring(struct vte_softc *sc)
1880 struct vte_tx_desc *desc;
1881 struct vte_txdesc *txd;
1885 VTE_LOCK_ASSERT(sc);
1887 sc->vte_cdata.vte_tx_prod = 0;
1888 sc->vte_cdata.vte_tx_cons = 0;
1889 sc->vte_cdata.vte_tx_cnt = 0;
1891 /* Pre-allocate TX mbufs for deep copy. */
1892 if (tx_deep_copy != 0) {
1893 for (i = 0; i < VTE_TX_RING_CNT; i++) {
1894 sc->vte_cdata.vte_txmbufs[i] = m_getcl(M_NOWAIT,
1896 if (sc->vte_cdata.vte_txmbufs[i] == NULL)
1898 sc->vte_cdata.vte_txmbufs[i]->m_pkthdr.len = MCLBYTES;
1899 sc->vte_cdata.vte_txmbufs[i]->m_len = MCLBYTES;
1902 desc = sc->vte_cdata.vte_tx_ring;
1903 bzero(desc, VTE_TX_RING_SZ);
1904 for (i = 0; i < VTE_TX_RING_CNT; i++) {
1905 txd = &sc->vte_cdata.vte_txdesc[i];
1907 if (i != VTE_TX_RING_CNT - 1)
1908 addr = sc->vte_cdata.vte_tx_ring_paddr +
1909 sizeof(struct vte_tx_desc) * (i + 1);
1911 addr = sc->vte_cdata.vte_tx_ring_paddr +
1912 sizeof(struct vte_tx_desc) * 0;
1913 desc = &sc->vte_cdata.vte_tx_ring[i];
1914 desc->dtnp = htole32(addr);
1915 txd->tx_desc = desc;
1918 bus_dmamap_sync(sc->vte_cdata.vte_tx_ring_tag,
1919 sc->vte_cdata.vte_tx_ring_map, BUS_DMASYNC_PREREAD |
1920 BUS_DMASYNC_PREWRITE);
1925 vte_init_rx_ring(struct vte_softc *sc)
1927 struct vte_rx_desc *desc;
1928 struct vte_rxdesc *rxd;
1932 VTE_LOCK_ASSERT(sc);
1934 sc->vte_cdata.vte_rx_cons = 0;
1935 desc = sc->vte_cdata.vte_rx_ring;
1936 bzero(desc, VTE_RX_RING_SZ);
1937 for (i = 0; i < VTE_RX_RING_CNT; i++) {
1938 rxd = &sc->vte_cdata.vte_rxdesc[i];
1940 if (i != VTE_RX_RING_CNT - 1)
1941 addr = sc->vte_cdata.vte_rx_ring_paddr +
1942 sizeof(struct vte_rx_desc) * (i + 1);
1944 addr = sc->vte_cdata.vte_rx_ring_paddr +
1945 sizeof(struct vte_rx_desc) * 0;
1946 desc = &sc->vte_cdata.vte_rx_ring[i];
1947 desc->drnp = htole32(addr);
1948 rxd->rx_desc = desc;
1949 if (vte_newbuf(sc, rxd) != 0)
1953 bus_dmamap_sync(sc->vte_cdata.vte_rx_ring_tag,
1954 sc->vte_cdata.vte_rx_ring_map, BUS_DMASYNC_PREREAD |
1955 BUS_DMASYNC_PREWRITE);
1960 struct vte_maddr_ctx {
1961 uint16_t rxfilt_perf[VTE_RXFILT_PERFECT_CNT][3];
1967 vte_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
1969 struct vte_maddr_ctx *ctx = arg;
1974 * Program the first 3 multicast groups into the perfect filter.
1975 * For all others, use the hash table.
1977 if (ctx->nperf < VTE_RXFILT_PERFECT_CNT) {
1978 eaddr = LLADDR(sdl);
1979 ctx->rxfilt_perf[ctx->nperf][0] = eaddr[1] << 8 | eaddr[0];
1980 ctx->rxfilt_perf[ctx->nperf][1] = eaddr[3] << 8 | eaddr[2];
1981 ctx->rxfilt_perf[ctx->nperf][2] = eaddr[5] << 8 | eaddr[4];
1986 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN);
1987 ctx->mchash[crc >> 30] |= 1 << ((crc >> 26) & 0x0F);
1993 vte_rxfilter(struct vte_softc *sc)
1996 struct vte_maddr_ctx ctx;
2000 VTE_LOCK_ASSERT(sc);
2004 bzero(ctx.mchash, sizeof(ctx.mchash));
2005 for (i = 0; i < VTE_RXFILT_PERFECT_CNT; i++) {
2006 ctx.rxfilt_perf[i][0] = 0xFFFF;
2007 ctx.rxfilt_perf[i][1] = 0xFFFF;
2008 ctx.rxfilt_perf[i][2] = 0xFFFF;
2012 mcr = CSR_READ_2(sc, VTE_MCR0);
2013 mcr &= ~(MCR0_PROMISC | MCR0_MULTICAST);
2014 mcr |= MCR0_BROADCAST_DIS;
2015 if ((ifp->if_flags & IFF_BROADCAST) != 0)
2016 mcr &= ~MCR0_BROADCAST_DIS;
2017 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
2018 if ((ifp->if_flags & IFF_PROMISC) != 0)
2019 mcr |= MCR0_PROMISC;
2020 if ((ifp->if_flags & IFF_ALLMULTI) != 0)
2021 mcr |= MCR0_MULTICAST;
2022 ctx.mchash[0] = 0xFFFF;
2023 ctx.mchash[1] = 0xFFFF;
2024 ctx.mchash[2] = 0xFFFF;
2025 ctx.mchash[3] = 0xFFFF;
2029 if_foreach_llmaddr(ifp, vte_hash_maddr, &ctx);
2030 if (ctx.mchash[0] != 0 || ctx.mchash[1] != 0 ||
2031 ctx.mchash[2] != 0 || ctx.mchash[3] != 0)
2032 mcr |= MCR0_MULTICAST;
2035 /* Program multicast hash table. */
2036 CSR_WRITE_2(sc, VTE_MAR0, ctx.mchash[0]);
2037 CSR_WRITE_2(sc, VTE_MAR1, ctx.mchash[1]);
2038 CSR_WRITE_2(sc, VTE_MAR2, ctx.mchash[2]);
2039 CSR_WRITE_2(sc, VTE_MAR3, ctx.mchash[3]);
2040 /* Program perfect filter table. */
2041 for (i = 0; i < VTE_RXFILT_PERFECT_CNT; i++) {
2042 CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 0,
2043 ctx.rxfilt_perf[i][0]);
2044 CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 2,
2045 ctx.rxfilt_perf[i][1]);
2046 CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 4,
2047 ctx.rxfilt_perf[i][2]);
2049 CSR_WRITE_2(sc, VTE_MCR0, mcr);
2050 CSR_READ_2(sc, VTE_MCR0);
2054 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
2060 value = *(int *)arg1;
2061 error = sysctl_handle_int(oidp, &value, 0, req);
2062 if (error || req->newptr == NULL)
2064 if (value < low || value > high)
2066 *(int *)arg1 = value;
2072 sysctl_hw_vte_int_mod(SYSCTL_HANDLER_ARGS)
2075 return (sysctl_int_range(oidp, arg1, arg2, req,
2076 VTE_IM_BUNDLE_MIN, VTE_IM_BUNDLE_MAX));