2 * Copyright (c) 2010, Pyun YongHyeon <yongari@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 /* Driver for DM&P Electronics, Inc, Vortex86 RDC R6040 FastEthernet. */
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
36 #include <sys/endian.h>
37 #include <sys/kernel.h>
39 #include <sys/malloc.h>
41 #include <sys/module.h>
42 #include <sys/mutex.h>
44 #include <sys/socket.h>
45 #include <sys/sockio.h>
46 #include <sys/sysctl.h>
50 #include <net/if_var.h>
51 #include <net/if_arp.h>
52 #include <net/ethernet.h>
53 #include <net/if_dl.h>
54 #include <net/if_llc.h>
55 #include <net/if_media.h>
56 #include <net/if_types.h>
57 #include <net/if_vlan_var.h>
59 #include <netinet/in.h>
60 #include <netinet/in_systm.h>
62 #include <dev/mii/mii.h>
63 #include <dev/mii/miivar.h>
65 #include <dev/pci/pcireg.h>
66 #include <dev/pci/pcivar.h>
68 #include <machine/bus.h>
70 #include <dev/vte/if_vtereg.h>
71 #include <dev/vte/if_vtevar.h>
73 /* "device miibus" required. See GENERIC if you get errors here. */
74 #include "miibus_if.h"
76 MODULE_DEPEND(vte, pci, 1, 1, 1);
77 MODULE_DEPEND(vte, ether, 1, 1, 1);
78 MODULE_DEPEND(vte, miibus, 1, 1, 1);
81 static int tx_deep_copy = 1;
82 TUNABLE_INT("hw.vte.tx_deep_copy", &tx_deep_copy);
85 * Devices supported by this driver.
87 static const struct vte_ident vte_ident_table[] = {
88 { VENDORID_RDC, DEVICEID_RDC_R6040, "RDC R6040 FastEthernet"},
92 static int vte_attach(device_t);
93 static int vte_detach(device_t);
94 static int vte_dma_alloc(struct vte_softc *);
95 static void vte_dma_free(struct vte_softc *);
96 static void vte_dmamap_cb(void *, bus_dma_segment_t *, int, int);
97 static struct vte_txdesc *
98 vte_encap(struct vte_softc *, struct mbuf **);
99 static const struct vte_ident *
100 vte_find_ident(device_t);
101 #ifndef __NO_STRICT_ALIGNMENT
103 vte_fixup_rx(struct ifnet *, struct mbuf *);
105 static void vte_get_macaddr(struct vte_softc *);
106 static void vte_init(void *);
107 static void vte_init_locked(struct vte_softc *);
108 static int vte_init_rx_ring(struct vte_softc *);
109 static int vte_init_tx_ring(struct vte_softc *);
110 static void vte_intr(void *);
111 static int vte_ioctl(struct ifnet *, u_long, caddr_t);
112 static uint64_t vte_get_counter(struct ifnet *, ift_counter);
113 static void vte_mac_config(struct vte_softc *);
114 static int vte_miibus_readreg(device_t, int, int);
115 static void vte_miibus_statchg(device_t);
116 static int vte_miibus_writereg(device_t, int, int, int);
117 static int vte_mediachange(struct ifnet *);
118 static int vte_mediachange_locked(struct ifnet *);
119 static void vte_mediastatus(struct ifnet *, struct ifmediareq *);
120 static int vte_newbuf(struct vte_softc *, struct vte_rxdesc *);
121 static int vte_probe(device_t);
122 static void vte_reset(struct vte_softc *);
123 static int vte_resume(device_t);
124 static void vte_rxeof(struct vte_softc *);
125 static void vte_rxfilter(struct vte_softc *);
126 static int vte_shutdown(device_t);
127 static void vte_start(struct ifnet *);
128 static void vte_start_locked(struct vte_softc *);
129 static void vte_start_mac(struct vte_softc *);
130 static void vte_stats_clear(struct vte_softc *);
131 static void vte_stats_update(struct vte_softc *);
132 static void vte_stop(struct vte_softc *);
133 static void vte_stop_mac(struct vte_softc *);
134 static int vte_suspend(device_t);
135 static void vte_sysctl_node(struct vte_softc *);
136 static void vte_tick(void *);
137 static void vte_txeof(struct vte_softc *);
138 static void vte_watchdog(struct vte_softc *);
139 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
140 static int sysctl_hw_vte_int_mod(SYSCTL_HANDLER_ARGS);
142 static device_method_t vte_methods[] = {
143 /* Device interface. */
144 DEVMETHOD(device_probe, vte_probe),
145 DEVMETHOD(device_attach, vte_attach),
146 DEVMETHOD(device_detach, vte_detach),
147 DEVMETHOD(device_shutdown, vte_shutdown),
148 DEVMETHOD(device_suspend, vte_suspend),
149 DEVMETHOD(device_resume, vte_resume),
152 DEVMETHOD(miibus_readreg, vte_miibus_readreg),
153 DEVMETHOD(miibus_writereg, vte_miibus_writereg),
154 DEVMETHOD(miibus_statchg, vte_miibus_statchg),
159 static driver_t vte_driver = {
162 sizeof(struct vte_softc)
165 static devclass_t vte_devclass;
167 DRIVER_MODULE(vte, pci, vte_driver, vte_devclass, 0, 0);
168 DRIVER_MODULE(miibus, vte, miibus_driver, miibus_devclass, 0, 0);
171 vte_miibus_readreg(device_t dev, int phy, int reg)
173 struct vte_softc *sc;
176 sc = device_get_softc(dev);
178 CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_READ |
179 (phy << MMDIO_PHY_ADDR_SHIFT) | (reg << MMDIO_REG_ADDR_SHIFT));
180 for (i = VTE_PHY_TIMEOUT; i > 0; i--) {
182 if ((CSR_READ_2(sc, VTE_MMDIO) & MMDIO_READ) == 0)
187 device_printf(sc->vte_dev, "phy read timeout : %d\n", reg);
191 return (CSR_READ_2(sc, VTE_MMRD));
195 vte_miibus_writereg(device_t dev, int phy, int reg, int val)
197 struct vte_softc *sc;
200 sc = device_get_softc(dev);
202 CSR_WRITE_2(sc, VTE_MMWD, val);
203 CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_WRITE |
204 (phy << MMDIO_PHY_ADDR_SHIFT) | (reg << MMDIO_REG_ADDR_SHIFT));
205 for (i = VTE_PHY_TIMEOUT; i > 0; i--) {
207 if ((CSR_READ_2(sc, VTE_MMDIO) & MMDIO_WRITE) == 0)
212 device_printf(sc->vte_dev, "phy write timeout : %d\n", reg);
218 vte_miibus_statchg(device_t dev)
220 struct vte_softc *sc;
221 struct mii_data *mii;
225 sc = device_get_softc(dev);
227 mii = device_get_softc(sc->vte_miibus);
229 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
232 sc->vte_flags &= ~VTE_FLAG_LINK;
233 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
234 (IFM_ACTIVE | IFM_AVALID)) {
235 switch (IFM_SUBTYPE(mii->mii_media_active)) {
238 sc->vte_flags |= VTE_FLAG_LINK;
245 /* Stop RX/TX MACs. */
247 /* Program MACs with resolved duplex and flow control. */
248 if ((sc->vte_flags & VTE_FLAG_LINK) != 0) {
250 * Timer waiting time : (63 + TIMER * 64) MII clock.
251 * MII clock : 25MHz(100Mbps) or 2.5MHz(10Mbps).
253 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX)
254 val = 18 << VTE_IM_TIMER_SHIFT;
256 val = 1 << VTE_IM_TIMER_SHIFT;
257 val |= sc->vte_int_rx_mod << VTE_IM_BUNDLE_SHIFT;
258 /* 48.6us for 100Mbps, 50.8us for 10Mbps */
259 CSR_WRITE_2(sc, VTE_MRICR, val);
261 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX)
262 val = 18 << VTE_IM_TIMER_SHIFT;
264 val = 1 << VTE_IM_TIMER_SHIFT;
265 val |= sc->vte_int_tx_mod << VTE_IM_BUNDLE_SHIFT;
266 /* 48.6us for 100Mbps, 50.8us for 10Mbps */
267 CSR_WRITE_2(sc, VTE_MTICR, val);
275 vte_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
277 struct vte_softc *sc;
278 struct mii_data *mii;
282 if ((ifp->if_flags & IFF_UP) == 0) {
286 mii = device_get_softc(sc->vte_miibus);
289 ifmr->ifm_status = mii->mii_media_status;
290 ifmr->ifm_active = mii->mii_media_active;
295 vte_mediachange(struct ifnet *ifp)
297 struct vte_softc *sc;
302 error = vte_mediachange_locked(ifp);
308 vte_mediachange_locked(struct ifnet *ifp)
310 struct vte_softc *sc;
311 struct mii_data *mii;
312 struct mii_softc *miisc;
316 mii = device_get_softc(sc->vte_miibus);
317 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
319 error = mii_mediachg(mii);
324 static const struct vte_ident *
325 vte_find_ident(device_t dev)
327 const struct vte_ident *ident;
328 uint16_t vendor, devid;
330 vendor = pci_get_vendor(dev);
331 devid = pci_get_device(dev);
332 for (ident = vte_ident_table; ident->name != NULL; ident++) {
333 if (vendor == ident->vendorid && devid == ident->deviceid)
341 vte_probe(device_t dev)
343 const struct vte_ident *ident;
345 ident = vte_find_ident(dev);
347 device_set_desc(dev, ident->name);
348 return (BUS_PROBE_DEFAULT);
355 vte_get_macaddr(struct vte_softc *sc)
360 * It seems there is no way to reload station address and
361 * it is supposed to be set by BIOS.
363 mid = CSR_READ_2(sc, VTE_MID0L);
364 sc->vte_eaddr[0] = (mid >> 0) & 0xFF;
365 sc->vte_eaddr[1] = (mid >> 8) & 0xFF;
366 mid = CSR_READ_2(sc, VTE_MID0M);
367 sc->vte_eaddr[2] = (mid >> 0) & 0xFF;
368 sc->vte_eaddr[3] = (mid >> 8) & 0xFF;
369 mid = CSR_READ_2(sc, VTE_MID0H);
370 sc->vte_eaddr[4] = (mid >> 0) & 0xFF;
371 sc->vte_eaddr[5] = (mid >> 8) & 0xFF;
375 vte_attach(device_t dev)
377 struct vte_softc *sc;
383 sc = device_get_softc(dev);
386 mtx_init(&sc->vte_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
388 callout_init_mtx(&sc->vte_tick_ch, &sc->vte_mtx, 0);
389 sc->vte_ident = vte_find_ident(dev);
391 /* Map the device. */
392 pci_enable_busmaster(dev);
393 sc->vte_res_id = PCIR_BAR(1);
394 sc->vte_res_type = SYS_RES_MEMORY;
395 sc->vte_res = bus_alloc_resource_any(dev, sc->vte_res_type,
396 &sc->vte_res_id, RF_ACTIVE);
397 if (sc->vte_res == NULL) {
398 sc->vte_res_id = PCIR_BAR(0);
399 sc->vte_res_type = SYS_RES_IOPORT;
400 sc->vte_res = bus_alloc_resource_any(dev, sc->vte_res_type,
401 &sc->vte_res_id, RF_ACTIVE);
402 if (sc->vte_res == NULL) {
403 device_printf(dev, "cannot map memory/ports.\n");
404 mtx_destroy(&sc->vte_mtx);
409 device_printf(dev, "using %s space register mapping\n",
410 sc->vte_res_type == SYS_RES_MEMORY ? "memory" : "I/O");
411 device_printf(dev, "MAC Identifier : 0x%04x\n",
412 CSR_READ_2(sc, VTE_MACID));
413 macid = CSR_READ_2(sc, VTE_MACID_REV);
414 device_printf(dev, "MAC Id. 0x%02x, Rev. 0x%02x\n",
415 (macid & VTE_MACID_MASK) >> VTE_MACID_SHIFT,
416 (macid & VTE_MACID_REV_MASK) >> VTE_MACID_REV_SHIFT);
420 sc->vte_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
421 RF_SHAREABLE | RF_ACTIVE);
422 if (sc->vte_irq == NULL) {
423 device_printf(dev, "cannot allocate IRQ resources.\n");
428 /* Reset the ethernet controller. */
431 if ((error = vte_dma_alloc(sc) != 0))
434 /* Create device sysctl node. */
437 /* Load station address. */
440 ifp = sc->vte_ifp = if_alloc(IFT_ETHER);
442 device_printf(dev, "cannot allocate ifnet structure.\n");
448 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
449 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
450 ifp->if_ioctl = vte_ioctl;
451 ifp->if_start = vte_start;
452 ifp->if_init = vte_init;
453 ifp->if_get_counter = vte_get_counter;
454 ifp->if_snd.ifq_drv_maxlen = VTE_TX_RING_CNT - 1;
455 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
456 IFQ_SET_READY(&ifp->if_snd);
460 * BIOS would have initialized VTE_MPSCCR to catch PHY
461 * status changes so driver may be able to extract
462 * configured PHY address. Since it's common to see BIOS
463 * fails to initialize the register(including the sample
464 * board I have), let mii(4) probe it. This is more
465 * reliable than relying on BIOS's initialization.
467 * Advertising flow control capability to mii(4) was
468 * intentionally disabled due to severe problems in TX
469 * pause frame generation. See vte_rxeof() for more
472 error = mii_attach(dev, &sc->vte_miibus, ifp, vte_mediachange,
473 vte_mediastatus, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
475 device_printf(dev, "attaching PHYs failed\n");
479 ether_ifattach(ifp, sc->vte_eaddr);
481 /* VLAN capability setup. */
482 ifp->if_capabilities |= IFCAP_VLAN_MTU;
483 ifp->if_capenable = ifp->if_capabilities;
484 /* Tell the upper layer we support VLAN over-sized frames. */
485 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
487 error = bus_setup_intr(dev, sc->vte_irq, INTR_TYPE_NET | INTR_MPSAFE,
488 NULL, vte_intr, sc, &sc->vte_intrhand);
490 device_printf(dev, "could not set up interrupt handler.\n");
503 vte_detach(device_t dev)
505 struct vte_softc *sc;
508 sc = device_get_softc(dev);
511 if (device_is_attached(dev)) {
515 callout_drain(&sc->vte_tick_ch);
519 if (sc->vte_miibus != NULL) {
520 device_delete_child(dev, sc->vte_miibus);
521 sc->vte_miibus = NULL;
523 bus_generic_detach(dev);
525 if (sc->vte_intrhand != NULL) {
526 bus_teardown_intr(dev, sc->vte_irq, sc->vte_intrhand);
527 sc->vte_intrhand = NULL;
529 if (sc->vte_irq != NULL) {
530 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vte_irq);
533 if (sc->vte_res != NULL) {
534 bus_release_resource(dev, sc->vte_res_type, sc->vte_res_id,
543 mtx_destroy(&sc->vte_mtx);
548 #define VTE_SYSCTL_STAT_ADD32(c, h, n, p, d) \
549 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
552 vte_sysctl_node(struct vte_softc *sc)
554 struct sysctl_ctx_list *ctx;
555 struct sysctl_oid_list *child, *parent;
556 struct sysctl_oid *tree;
557 struct vte_hw_stats *stats;
560 stats = &sc->vte_stats;
561 ctx = device_get_sysctl_ctx(sc->vte_dev);
562 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->vte_dev));
564 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod",
565 CTLTYPE_INT | CTLFLAG_RW, &sc->vte_int_rx_mod, 0,
566 sysctl_hw_vte_int_mod, "I", "vte RX interrupt moderation");
567 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod",
568 CTLTYPE_INT | CTLFLAG_RW, &sc->vte_int_tx_mod, 0,
569 sysctl_hw_vte_int_mod, "I", "vte TX interrupt moderation");
570 /* Pull in device tunables. */
571 sc->vte_int_rx_mod = VTE_IM_RX_BUNDLE_DEFAULT;
572 error = resource_int_value(device_get_name(sc->vte_dev),
573 device_get_unit(sc->vte_dev), "int_rx_mod", &sc->vte_int_rx_mod);
575 if (sc->vte_int_rx_mod < VTE_IM_BUNDLE_MIN ||
576 sc->vte_int_rx_mod > VTE_IM_BUNDLE_MAX) {
577 device_printf(sc->vte_dev, "int_rx_mod value out of "
578 "range; using default: %d\n",
579 VTE_IM_RX_BUNDLE_DEFAULT);
580 sc->vte_int_rx_mod = VTE_IM_RX_BUNDLE_DEFAULT;
584 sc->vte_int_tx_mod = VTE_IM_TX_BUNDLE_DEFAULT;
585 error = resource_int_value(device_get_name(sc->vte_dev),
586 device_get_unit(sc->vte_dev), "int_tx_mod", &sc->vte_int_tx_mod);
588 if (sc->vte_int_tx_mod < VTE_IM_BUNDLE_MIN ||
589 sc->vte_int_tx_mod > VTE_IM_BUNDLE_MAX) {
590 device_printf(sc->vte_dev, "int_tx_mod value out of "
591 "range; using default: %d\n",
592 VTE_IM_TX_BUNDLE_DEFAULT);
593 sc->vte_int_tx_mod = VTE_IM_TX_BUNDLE_DEFAULT;
597 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD,
598 NULL, "VTE statistics");
599 parent = SYSCTL_CHILDREN(tree);
602 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD,
603 NULL, "RX MAC statistics");
604 child = SYSCTL_CHILDREN(tree);
605 VTE_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
606 &stats->rx_frames, "Good frames");
607 VTE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
608 &stats->rx_bcast_frames, "Good broadcast frames");
609 VTE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
610 &stats->rx_mcast_frames, "Good multicast frames");
611 VTE_SYSCTL_STAT_ADD32(ctx, child, "runt",
612 &stats->rx_runts, "Too short frames");
613 VTE_SYSCTL_STAT_ADD32(ctx, child, "crc_errs",
614 &stats->rx_crcerrs, "CRC errors");
615 VTE_SYSCTL_STAT_ADD32(ctx, child, "long_frames",
616 &stats->rx_long_frames,
617 "Frames that have longer length than maximum packet length");
618 VTE_SYSCTL_STAT_ADD32(ctx, child, "fifo_full",
619 &stats->rx_fifo_full, "FIFO full");
620 VTE_SYSCTL_STAT_ADD32(ctx, child, "desc_unavail",
621 &stats->rx_desc_unavail, "Descriptor unavailable frames");
622 VTE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames",
623 &stats->rx_pause_frames, "Pause control frames");
626 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD,
627 NULL, "TX MAC statistics");
628 child = SYSCTL_CHILDREN(tree);
629 VTE_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
630 &stats->tx_frames, "Good frames");
631 VTE_SYSCTL_STAT_ADD32(ctx, child, "underruns",
632 &stats->tx_underruns, "FIFO underruns");
633 VTE_SYSCTL_STAT_ADD32(ctx, child, "late_colls",
634 &stats->tx_late_colls, "Late collisions");
635 VTE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames",
636 &stats->tx_pause_frames, "Pause control frames");
639 #undef VTE_SYSCTL_STAT_ADD32
641 struct vte_dmamap_arg {
642 bus_addr_t vte_busaddr;
646 vte_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
648 struct vte_dmamap_arg *ctx;
653 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
655 ctx = (struct vte_dmamap_arg *)arg;
656 ctx->vte_busaddr = segs[0].ds_addr;
660 vte_dma_alloc(struct vte_softc *sc)
662 struct vte_txdesc *txd;
663 struct vte_rxdesc *rxd;
664 struct vte_dmamap_arg ctx;
667 /* Create parent DMA tag. */
668 error = bus_dma_tag_create(
669 bus_get_dma_tag(sc->vte_dev), /* parent */
670 1, 0, /* alignment, boundary */
671 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
672 BUS_SPACE_MAXADDR, /* highaddr */
673 NULL, NULL, /* filter, filterarg */
674 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
676 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
678 NULL, NULL, /* lockfunc, lockarg */
679 &sc->vte_cdata.vte_parent_tag);
681 device_printf(sc->vte_dev,
682 "could not create parent DMA tag.\n");
686 /* Create DMA tag for TX descriptor ring. */
687 error = bus_dma_tag_create(
688 sc->vte_cdata.vte_parent_tag, /* parent */
689 VTE_TX_RING_ALIGN, 0, /* alignment, boundary */
690 BUS_SPACE_MAXADDR, /* lowaddr */
691 BUS_SPACE_MAXADDR, /* highaddr */
692 NULL, NULL, /* filter, filterarg */
693 VTE_TX_RING_SZ, /* maxsize */
695 VTE_TX_RING_SZ, /* maxsegsize */
697 NULL, NULL, /* lockfunc, lockarg */
698 &sc->vte_cdata.vte_tx_ring_tag);
700 device_printf(sc->vte_dev,
701 "could not create TX ring DMA tag.\n");
705 /* Create DMA tag for RX free descriptor ring. */
706 error = bus_dma_tag_create(
707 sc->vte_cdata.vte_parent_tag, /* parent */
708 VTE_RX_RING_ALIGN, 0, /* alignment, boundary */
709 BUS_SPACE_MAXADDR, /* lowaddr */
710 BUS_SPACE_MAXADDR, /* highaddr */
711 NULL, NULL, /* filter, filterarg */
712 VTE_RX_RING_SZ, /* maxsize */
714 VTE_RX_RING_SZ, /* maxsegsize */
716 NULL, NULL, /* lockfunc, lockarg */
717 &sc->vte_cdata.vte_rx_ring_tag);
719 device_printf(sc->vte_dev,
720 "could not create RX ring DMA tag.\n");
724 /* Allocate DMA'able memory and load the DMA map for TX ring. */
725 error = bus_dmamem_alloc(sc->vte_cdata.vte_tx_ring_tag,
726 (void **)&sc->vte_cdata.vte_tx_ring,
727 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
728 &sc->vte_cdata.vte_tx_ring_map);
730 device_printf(sc->vte_dev,
731 "could not allocate DMA'able memory for TX ring.\n");
735 error = bus_dmamap_load(sc->vte_cdata.vte_tx_ring_tag,
736 sc->vte_cdata.vte_tx_ring_map, sc->vte_cdata.vte_tx_ring,
737 VTE_TX_RING_SZ, vte_dmamap_cb, &ctx, 0);
738 if (error != 0 || ctx.vte_busaddr == 0) {
739 device_printf(sc->vte_dev,
740 "could not load DMA'able memory for TX ring.\n");
743 sc->vte_cdata.vte_tx_ring_paddr = ctx.vte_busaddr;
745 /* Allocate DMA'able memory and load the DMA map for RX ring. */
746 error = bus_dmamem_alloc(sc->vte_cdata.vte_rx_ring_tag,
747 (void **)&sc->vte_cdata.vte_rx_ring,
748 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
749 &sc->vte_cdata.vte_rx_ring_map);
751 device_printf(sc->vte_dev,
752 "could not allocate DMA'able memory for RX ring.\n");
756 error = bus_dmamap_load(sc->vte_cdata.vte_rx_ring_tag,
757 sc->vte_cdata.vte_rx_ring_map, sc->vte_cdata.vte_rx_ring,
758 VTE_RX_RING_SZ, vte_dmamap_cb, &ctx, 0);
759 if (error != 0 || ctx.vte_busaddr == 0) {
760 device_printf(sc->vte_dev,
761 "could not load DMA'able memory for RX ring.\n");
764 sc->vte_cdata.vte_rx_ring_paddr = ctx.vte_busaddr;
766 /* Create TX buffer parent tag. */
767 error = bus_dma_tag_create(
768 bus_get_dma_tag(sc->vte_dev), /* parent */
769 1, 0, /* alignment, boundary */
770 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
771 BUS_SPACE_MAXADDR, /* highaddr */
772 NULL, NULL, /* filter, filterarg */
773 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
775 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
777 NULL, NULL, /* lockfunc, lockarg */
778 &sc->vte_cdata.vte_buffer_tag);
780 device_printf(sc->vte_dev,
781 "could not create parent buffer DMA tag.\n");
785 /* Create DMA tag for TX buffers. */
786 error = bus_dma_tag_create(
787 sc->vte_cdata.vte_buffer_tag, /* parent */
788 1, 0, /* alignment, boundary */
789 BUS_SPACE_MAXADDR, /* lowaddr */
790 BUS_SPACE_MAXADDR, /* highaddr */
791 NULL, NULL, /* filter, filterarg */
792 MCLBYTES, /* maxsize */
794 MCLBYTES, /* maxsegsize */
796 NULL, NULL, /* lockfunc, lockarg */
797 &sc->vte_cdata.vte_tx_tag);
799 device_printf(sc->vte_dev, "could not create TX DMA tag.\n");
803 /* Create DMA tag for RX buffers. */
804 error = bus_dma_tag_create(
805 sc->vte_cdata.vte_buffer_tag, /* parent */
806 VTE_RX_BUF_ALIGN, 0, /* alignment, boundary */
807 BUS_SPACE_MAXADDR, /* lowaddr */
808 BUS_SPACE_MAXADDR, /* highaddr */
809 NULL, NULL, /* filter, filterarg */
810 MCLBYTES, /* maxsize */
812 MCLBYTES, /* maxsegsize */
814 NULL, NULL, /* lockfunc, lockarg */
815 &sc->vte_cdata.vte_rx_tag);
817 device_printf(sc->vte_dev, "could not create RX DMA tag.\n");
820 /* Create DMA maps for TX buffers. */
821 for (i = 0; i < VTE_TX_RING_CNT; i++) {
822 txd = &sc->vte_cdata.vte_txdesc[i];
824 txd->tx_dmamap = NULL;
825 error = bus_dmamap_create(sc->vte_cdata.vte_tx_tag, 0,
828 device_printf(sc->vte_dev,
829 "could not create TX dmamap.\n");
833 /* Create DMA maps for RX buffers. */
834 if ((error = bus_dmamap_create(sc->vte_cdata.vte_rx_tag, 0,
835 &sc->vte_cdata.vte_rx_sparemap)) != 0) {
836 device_printf(sc->vte_dev,
837 "could not create spare RX dmamap.\n");
840 for (i = 0; i < VTE_RX_RING_CNT; i++) {
841 rxd = &sc->vte_cdata.vte_rxdesc[i];
843 rxd->rx_dmamap = NULL;
844 error = bus_dmamap_create(sc->vte_cdata.vte_rx_tag, 0,
847 device_printf(sc->vte_dev,
848 "could not create RX dmamap.\n");
858 vte_dma_free(struct vte_softc *sc)
860 struct vte_txdesc *txd;
861 struct vte_rxdesc *rxd;
865 if (sc->vte_cdata.vte_tx_tag != NULL) {
866 for (i = 0; i < VTE_TX_RING_CNT; i++) {
867 txd = &sc->vte_cdata.vte_txdesc[i];
868 if (txd->tx_dmamap != NULL) {
869 bus_dmamap_destroy(sc->vte_cdata.vte_tx_tag,
871 txd->tx_dmamap = NULL;
874 bus_dma_tag_destroy(sc->vte_cdata.vte_tx_tag);
875 sc->vte_cdata.vte_tx_tag = NULL;
878 if (sc->vte_cdata.vte_rx_tag != NULL) {
879 for (i = 0; i < VTE_RX_RING_CNT; i++) {
880 rxd = &sc->vte_cdata.vte_rxdesc[i];
881 if (rxd->rx_dmamap != NULL) {
882 bus_dmamap_destroy(sc->vte_cdata.vte_rx_tag,
884 rxd->rx_dmamap = NULL;
887 if (sc->vte_cdata.vte_rx_sparemap != NULL) {
888 bus_dmamap_destroy(sc->vte_cdata.vte_rx_tag,
889 sc->vte_cdata.vte_rx_sparemap);
890 sc->vte_cdata.vte_rx_sparemap = NULL;
892 bus_dma_tag_destroy(sc->vte_cdata.vte_rx_tag);
893 sc->vte_cdata.vte_rx_tag = NULL;
895 /* TX descriptor ring. */
896 if (sc->vte_cdata.vte_tx_ring_tag != NULL) {
897 if (sc->vte_cdata.vte_tx_ring_paddr != 0)
898 bus_dmamap_unload(sc->vte_cdata.vte_tx_ring_tag,
899 sc->vte_cdata.vte_tx_ring_map);
900 if (sc->vte_cdata.vte_tx_ring != NULL)
901 bus_dmamem_free(sc->vte_cdata.vte_tx_ring_tag,
902 sc->vte_cdata.vte_tx_ring,
903 sc->vte_cdata.vte_tx_ring_map);
904 sc->vte_cdata.vte_tx_ring = NULL;
905 sc->vte_cdata.vte_tx_ring_paddr = 0;
906 bus_dma_tag_destroy(sc->vte_cdata.vte_tx_ring_tag);
907 sc->vte_cdata.vte_tx_ring_tag = NULL;
910 if (sc->vte_cdata.vte_rx_ring_tag != NULL) {
911 if (sc->vte_cdata.vte_rx_ring_paddr != 0)
912 bus_dmamap_unload(sc->vte_cdata.vte_rx_ring_tag,
913 sc->vte_cdata.vte_rx_ring_map);
914 if (sc->vte_cdata.vte_rx_ring != NULL)
915 bus_dmamem_free(sc->vte_cdata.vte_rx_ring_tag,
916 sc->vte_cdata.vte_rx_ring,
917 sc->vte_cdata.vte_rx_ring_map);
918 sc->vte_cdata.vte_rx_ring = NULL;
919 sc->vte_cdata.vte_rx_ring_paddr = 0;
920 bus_dma_tag_destroy(sc->vte_cdata.vte_rx_ring_tag);
921 sc->vte_cdata.vte_rx_ring_tag = NULL;
923 if (sc->vte_cdata.vte_buffer_tag != NULL) {
924 bus_dma_tag_destroy(sc->vte_cdata.vte_buffer_tag);
925 sc->vte_cdata.vte_buffer_tag = NULL;
927 if (sc->vte_cdata.vte_parent_tag != NULL) {
928 bus_dma_tag_destroy(sc->vte_cdata.vte_parent_tag);
929 sc->vte_cdata.vte_parent_tag = NULL;
934 vte_shutdown(device_t dev)
937 return (vte_suspend(dev));
941 vte_suspend(device_t dev)
943 struct vte_softc *sc;
946 sc = device_get_softc(dev);
950 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
958 vte_resume(device_t dev)
960 struct vte_softc *sc;
963 sc = device_get_softc(dev);
967 if ((ifp->if_flags & IFF_UP) != 0) {
968 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
976 static struct vte_txdesc *
977 vte_encap(struct vte_softc *sc, struct mbuf **m_head)
979 struct vte_txdesc *txd;
981 bus_dma_segment_t txsegs[1];
982 int copy, error, nsegs, padlen;
986 M_ASSERTPKTHDR((*m_head));
988 txd = &sc->vte_cdata.vte_txdesc[sc->vte_cdata.vte_tx_prod];
991 * Controller doesn't auto-pad, so we have to make sure pad
992 * short frames out to the minimum frame length.
994 if (m->m_pkthdr.len < VTE_MIN_FRAMELEN)
995 padlen = VTE_MIN_FRAMELEN - m->m_pkthdr.len;
1000 * Controller does not support multi-fragmented TX buffers.
1001 * Controller spends most of its TX processing time in
1002 * de-fragmenting TX buffers. Either faster CPU or more
1003 * advanced controller DMA engine is required to speed up
1004 * TX path processing.
1005 * To mitigate the de-fragmenting issue, perform deep copy
1006 * from fragmented mbuf chains to a pre-allocated mbuf
1007 * cluster with extra cost of kernel memory. For frames
1008 * that is composed of single TX buffer, the deep copy is
1011 if (tx_deep_copy != 0) {
1013 if (m->m_next != NULL)
1015 if (padlen > 0 && (M_WRITABLE(m) == 0 ||
1016 padlen > M_TRAILINGSPACE(m)))
1019 /* Avoid expensive m_defrag(9) and do deep copy. */
1020 n = sc->vte_cdata.vte_txmbufs[sc->vte_cdata.vte_tx_prod];
1021 m_copydata(m, 0, m->m_pkthdr.len, mtod(n, char *));
1022 n->m_pkthdr.len = m->m_pkthdr.len;
1023 n->m_len = m->m_pkthdr.len;
1025 txd->tx_flags |= VTE_TXMBUF;
1029 /* Zero out the bytes in the pad area. */
1030 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen);
1031 m->m_pkthdr.len += padlen;
1032 m->m_len = m->m_pkthdr.len;
1035 if (M_WRITABLE(m) == 0) {
1036 if (m->m_next != NULL || padlen > 0) {
1037 /* Get a writable copy. */
1038 m = m_dup(*m_head, M_NOWAIT);
1039 /* Release original mbuf chains. */
1049 if (m->m_next != NULL) {
1050 m = m_defrag(*m_head, M_NOWAIT);
1060 if (M_TRAILINGSPACE(m) < padlen) {
1061 m = m_defrag(*m_head, M_NOWAIT);
1069 /* Zero out the bytes in the pad area. */
1070 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen);
1071 m->m_pkthdr.len += padlen;
1072 m->m_len = m->m_pkthdr.len;
1076 error = bus_dmamap_load_mbuf_sg(sc->vte_cdata.vte_tx_tag,
1077 txd->tx_dmamap, m, txsegs, &nsegs, 0);
1079 txd->tx_flags &= ~VTE_TXMBUF;
1082 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1083 bus_dmamap_sync(sc->vte_cdata.vte_tx_tag, txd->tx_dmamap,
1084 BUS_DMASYNC_PREWRITE);
1086 txd->tx_desc->dtlen = htole16(VTE_TX_LEN(txsegs[0].ds_len));
1087 txd->tx_desc->dtbp = htole32(txsegs[0].ds_addr);
1088 sc->vte_cdata.vte_tx_cnt++;
1089 /* Update producer index. */
1090 VTE_DESC_INC(sc->vte_cdata.vte_tx_prod, VTE_TX_RING_CNT);
1092 /* Finally hand over ownership to controller. */
1093 txd->tx_desc->dtst = htole16(VTE_DTST_TX_OWN);
1100 vte_start(struct ifnet *ifp)
1102 struct vte_softc *sc;
1106 vte_start_locked(sc);
1111 vte_start_locked(struct vte_softc *sc)
1114 struct vte_txdesc *txd;
1115 struct mbuf *m_head;
1120 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1121 IFF_DRV_RUNNING || (sc->vte_flags & VTE_FLAG_LINK) == 0)
1124 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) {
1125 /* Reserve one free TX descriptor. */
1126 if (sc->vte_cdata.vte_tx_cnt >= VTE_TX_RING_CNT - 1) {
1127 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1130 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1134 * Pack the data into the transmit ring. If we
1135 * don't have room, set the OACTIVE flag and wait
1136 * for the NIC to drain the ring.
1138 if ((txd = vte_encap(sc, &m_head)) == NULL) {
1140 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1146 * If there's a BPF listener, bounce a copy of this frame
1149 ETHER_BPF_MTAP(ifp, m_head);
1150 /* Free consumed TX frame. */
1151 if ((txd->tx_flags & VTE_TXMBUF) != 0)
1156 bus_dmamap_sync(sc->vte_cdata.vte_tx_ring_tag,
1157 sc->vte_cdata.vte_tx_ring_map, BUS_DMASYNC_PREREAD |
1158 BUS_DMASYNC_PREWRITE);
1159 CSR_WRITE_2(sc, VTE_TX_POLL, TX_POLL_START);
1160 sc->vte_watchdog_timer = VTE_TX_TIMEOUT;
1165 vte_watchdog(struct vte_softc *sc)
1169 VTE_LOCK_ASSERT(sc);
1171 if (sc->vte_watchdog_timer == 0 || --sc->vte_watchdog_timer)
1175 if_printf(sc->vte_ifp, "watchdog timeout -- resetting\n");
1176 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1177 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1178 vte_init_locked(sc);
1179 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1180 vte_start_locked(sc);
1184 vte_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1186 struct vte_softc *sc;
1188 struct mii_data *mii;
1192 ifr = (struct ifreq *)data;
1197 if ((ifp->if_flags & IFF_UP) != 0) {
1198 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
1199 ((ifp->if_flags ^ sc->vte_if_flags) &
1200 (IFF_PROMISC | IFF_ALLMULTI)) != 0)
1203 vte_init_locked(sc);
1204 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1206 sc->vte_if_flags = ifp->if_flags;
1212 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1218 mii = device_get_softc(sc->vte_miibus);
1219 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1222 error = ether_ioctl(ifp, cmd, data);
1230 vte_mac_config(struct vte_softc *sc)
1232 struct mii_data *mii;
1235 VTE_LOCK_ASSERT(sc);
1237 mii = device_get_softc(sc->vte_miibus);
1238 mcr = CSR_READ_2(sc, VTE_MCR0);
1239 mcr &= ~(MCR0_FC_ENB | MCR0_FULL_DUPLEX);
1240 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1241 mcr |= MCR0_FULL_DUPLEX;
1243 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
1246 * The data sheet is not clear whether the controller
1247 * honors received pause frames or not. The is no
1248 * separate control bit for RX pause frame so just
1249 * enable MCR0_FC_ENB bit.
1251 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
1255 CSR_WRITE_2(sc, VTE_MCR0, mcr);
1259 vte_stats_clear(struct vte_softc *sc)
1262 /* Reading counter registers clears its contents. */
1263 CSR_READ_2(sc, VTE_CNT_RX_DONE);
1264 CSR_READ_2(sc, VTE_CNT_MECNT0);
1265 CSR_READ_2(sc, VTE_CNT_MECNT1);
1266 CSR_READ_2(sc, VTE_CNT_MECNT2);
1267 CSR_READ_2(sc, VTE_CNT_MECNT3);
1268 CSR_READ_2(sc, VTE_CNT_TX_DONE);
1269 CSR_READ_2(sc, VTE_CNT_MECNT4);
1270 CSR_READ_2(sc, VTE_CNT_PAUSE);
1274 vte_stats_update(struct vte_softc *sc)
1276 struct vte_hw_stats *stat;
1279 VTE_LOCK_ASSERT(sc);
1281 stat = &sc->vte_stats;
1283 CSR_READ_2(sc, VTE_MECISR);
1285 stat->rx_frames += CSR_READ_2(sc, VTE_CNT_RX_DONE);
1286 value = CSR_READ_2(sc, VTE_CNT_MECNT0);
1287 stat->rx_bcast_frames += (value >> 8);
1288 stat->rx_mcast_frames += (value & 0xFF);
1289 value = CSR_READ_2(sc, VTE_CNT_MECNT1);
1290 stat->rx_runts += (value >> 8);
1291 stat->rx_crcerrs += (value & 0xFF);
1292 value = CSR_READ_2(sc, VTE_CNT_MECNT2);
1293 stat->rx_long_frames += (value & 0xFF);
1294 value = CSR_READ_2(sc, VTE_CNT_MECNT3);
1295 stat->rx_fifo_full += (value >> 8);
1296 stat->rx_desc_unavail += (value & 0xFF);
1299 stat->tx_frames += CSR_READ_2(sc, VTE_CNT_TX_DONE);
1300 value = CSR_READ_2(sc, VTE_CNT_MECNT4);
1301 stat->tx_underruns += (value >> 8);
1302 stat->tx_late_colls += (value & 0xFF);
1304 value = CSR_READ_2(sc, VTE_CNT_PAUSE);
1305 stat->tx_pause_frames += (value >> 8);
1306 stat->rx_pause_frames += (value & 0xFF);
1310 vte_get_counter(struct ifnet *ifp, ift_counter cnt)
1312 struct vte_softc *sc;
1313 struct vte_hw_stats *stat;
1315 sc = if_getsoftc(ifp);
1316 stat = &sc->vte_stats;
1319 case IFCOUNTER_OPACKETS:
1320 return (stat->tx_frames);
1321 case IFCOUNTER_COLLISIONS:
1322 return (stat->tx_late_colls);
1323 case IFCOUNTER_OERRORS:
1324 return (stat->tx_late_colls + stat->tx_underruns);
1325 case IFCOUNTER_IPACKETS:
1326 return (stat->rx_frames);
1327 case IFCOUNTER_IERRORS:
1328 return (stat->rx_crcerrs + stat->rx_runts +
1329 stat->rx_long_frames + stat->rx_fifo_full);
1331 return (if_get_counter_default(ifp, cnt));
1338 struct vte_softc *sc;
1343 sc = (struct vte_softc *)arg;
1347 /* Reading VTE_MISR acknowledges interrupts. */
1348 status = CSR_READ_2(sc, VTE_MISR);
1349 if ((status & VTE_INTRS) == 0) {
1355 /* Disable interrupts. */
1356 CSR_WRITE_2(sc, VTE_MIER, 0);
1357 for (n = 8; (status & VTE_INTRS) != 0;) {
1358 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1360 if ((status & (MISR_RX_DONE | MISR_RX_DESC_UNAVAIL |
1361 MISR_RX_FIFO_FULL)) != 0)
1363 if ((status & MISR_TX_DONE) != 0)
1365 if ((status & MISR_EVENT_CNT_OFLOW) != 0)
1366 vte_stats_update(sc);
1367 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1368 vte_start_locked(sc);
1370 status = CSR_READ_2(sc, VTE_MISR);
1375 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1376 /* Re-enable interrupts. */
1377 CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS);
1383 vte_txeof(struct vte_softc *sc)
1386 struct vte_txdesc *txd;
1390 VTE_LOCK_ASSERT(sc);
1394 if (sc->vte_cdata.vte_tx_cnt == 0)
1396 bus_dmamap_sync(sc->vte_cdata.vte_tx_ring_tag,
1397 sc->vte_cdata.vte_tx_ring_map, BUS_DMASYNC_POSTREAD |
1398 BUS_DMASYNC_POSTWRITE);
1399 cons = sc->vte_cdata.vte_tx_cons;
1401 * Go through our TX list and free mbufs for those
1402 * frames which have been transmitted.
1404 for (prog = 0; sc->vte_cdata.vte_tx_cnt > 0; prog++) {
1405 txd = &sc->vte_cdata.vte_txdesc[cons];
1406 status = le16toh(txd->tx_desc->dtst);
1407 if ((status & VTE_DTST_TX_OWN) != 0)
1409 sc->vte_cdata.vte_tx_cnt--;
1410 /* Reclaim transmitted mbufs. */
1411 bus_dmamap_sync(sc->vte_cdata.vte_tx_tag, txd->tx_dmamap,
1412 BUS_DMASYNC_POSTWRITE);
1413 bus_dmamap_unload(sc->vte_cdata.vte_tx_tag, txd->tx_dmamap);
1414 if ((txd->tx_flags & VTE_TXMBUF) == 0)
1416 txd->tx_flags &= ~VTE_TXMBUF;
1419 VTE_DESC_INC(cons, VTE_TX_RING_CNT);
1423 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1424 sc->vte_cdata.vte_tx_cons = cons;
1426 * Unarm watchdog timer only when there is no pending
1427 * frames in TX queue.
1429 if (sc->vte_cdata.vte_tx_cnt == 0)
1430 sc->vte_watchdog_timer = 0;
1435 vte_newbuf(struct vte_softc *sc, struct vte_rxdesc *rxd)
1438 bus_dma_segment_t segs[1];
1442 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1445 m->m_len = m->m_pkthdr.len = MCLBYTES;
1446 m_adj(m, sizeof(uint32_t));
1448 if (bus_dmamap_load_mbuf_sg(sc->vte_cdata.vte_rx_tag,
1449 sc->vte_cdata.vte_rx_sparemap, m, segs, &nsegs, 0) != 0) {
1453 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1455 if (rxd->rx_m != NULL) {
1456 bus_dmamap_sync(sc->vte_cdata.vte_rx_tag, rxd->rx_dmamap,
1457 BUS_DMASYNC_POSTREAD);
1458 bus_dmamap_unload(sc->vte_cdata.vte_rx_tag, rxd->rx_dmamap);
1460 map = rxd->rx_dmamap;
1461 rxd->rx_dmamap = sc->vte_cdata.vte_rx_sparemap;
1462 sc->vte_cdata.vte_rx_sparemap = map;
1463 bus_dmamap_sync(sc->vte_cdata.vte_rx_tag, rxd->rx_dmamap,
1464 BUS_DMASYNC_PREREAD);
1466 rxd->rx_desc->drbp = htole32(segs[0].ds_addr);
1467 rxd->rx_desc->drlen = htole16(VTE_RX_LEN(segs[0].ds_len));
1468 rxd->rx_desc->drst = htole16(VTE_DRST_RX_OWN);
1474 * It's not supposed to see this controller on strict-alignment
1475 * architectures but make it work for completeness.
1477 #ifndef __NO_STRICT_ALIGNMENT
1478 static struct mbuf *
1479 vte_fixup_rx(struct ifnet *ifp, struct mbuf *m)
1481 uint16_t *src, *dst;
1484 src = mtod(m, uint16_t *);
1487 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
1489 m->m_data -= ETHER_ALIGN;
1495 vte_rxeof(struct vte_softc *sc)
1498 struct vte_rxdesc *rxd;
1500 uint16_t status, total_len;
1503 bus_dmamap_sync(sc->vte_cdata.vte_rx_ring_tag,
1504 sc->vte_cdata.vte_rx_ring_map, BUS_DMASYNC_POSTREAD |
1505 BUS_DMASYNC_POSTWRITE);
1506 cons = sc->vte_cdata.vte_rx_cons;
1508 for (prog = 0; (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0; prog++,
1509 VTE_DESC_INC(cons, VTE_RX_RING_CNT)) {
1510 rxd = &sc->vte_cdata.vte_rxdesc[cons];
1511 status = le16toh(rxd->rx_desc->drst);
1512 if ((status & VTE_DRST_RX_OWN) != 0)
1514 total_len = VTE_RX_LEN(le16toh(rxd->rx_desc->drlen));
1516 if ((status & VTE_DRST_RX_OK) == 0) {
1517 /* Discard errored frame. */
1518 rxd->rx_desc->drlen =
1519 htole16(MCLBYTES - sizeof(uint32_t));
1520 rxd->rx_desc->drst = htole16(VTE_DRST_RX_OWN);
1523 if (vte_newbuf(sc, rxd) != 0) {
1524 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1525 rxd->rx_desc->drlen =
1526 htole16(MCLBYTES - sizeof(uint32_t));
1527 rxd->rx_desc->drst = htole16(VTE_DRST_RX_OWN);
1532 * It seems there is no way to strip FCS bytes.
1534 m->m_pkthdr.len = m->m_len = total_len - ETHER_CRC_LEN;
1535 m->m_pkthdr.rcvif = ifp;
1536 #ifndef __NO_STRICT_ALIGNMENT
1537 vte_fixup_rx(ifp, m);
1540 (*ifp->if_input)(ifp, m);
1545 /* Update the consumer index. */
1546 sc->vte_cdata.vte_rx_cons = cons;
1548 * Sync updated RX descriptors such that controller see
1549 * modified RX buffer addresses.
1551 bus_dmamap_sync(sc->vte_cdata.vte_rx_ring_tag,
1552 sc->vte_cdata.vte_rx_ring_map,
1553 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1556 * Update residue counter. Controller does not
1557 * keep track of number of available RX descriptors
1558 * such that driver should have to update VTE_MRDCR
1559 * to make controller know how many free RX
1560 * descriptors were added to controller. This is
1561 * a similar mechanism used in VIA velocity
1562 * controllers and it indicates controller just
1563 * polls OWN bit of current RX descriptor pointer.
1564 * A couple of severe issues were seen on sample
1565 * board where the controller continuously emits TX
1566 * pause frames once RX pause threshold crossed.
1567 * Once triggered it never recovered form that
1568 * state, I couldn't find a way to make it back to
1569 * work at least. This issue effectively
1570 * disconnected the system from network. Also, the
1571 * controller used 00:00:00:00:00:00 as source
1572 * station address of TX pause frame. Probably this
1573 * is one of reason why vendor recommends not to
1574 * enable flow control on R6040 controller.
1576 CSR_WRITE_2(sc, VTE_MRDCR, prog |
1577 (((VTE_RX_RING_CNT * 2) / 10) <<
1578 VTE_MRDCR_RX_PAUSE_THRESH_SHIFT));
1586 struct vte_softc *sc;
1587 struct mii_data *mii;
1589 sc = (struct vte_softc *)arg;
1591 VTE_LOCK_ASSERT(sc);
1593 mii = device_get_softc(sc->vte_miibus);
1595 vte_stats_update(sc);
1598 callout_reset(&sc->vte_tick_ch, hz, vte_tick, sc);
1602 vte_reset(struct vte_softc *sc)
1607 mcr = CSR_READ_2(sc, VTE_MCR1);
1608 CSR_WRITE_2(sc, VTE_MCR1, mcr | MCR1_MAC_RESET);
1609 for (i = VTE_RESET_TIMEOUT; i > 0; i--) {
1611 if ((CSR_READ_2(sc, VTE_MCR1) & MCR1_MAC_RESET) == 0)
1615 device_printf(sc->vte_dev, "reset timeout(0x%04x)!\n", mcr);
1617 * Follow the guide of vendor recommended way to reset MAC.
1618 * Vendor confirms relying on MCR1_MAC_RESET of VTE_MCR1 is
1619 * not reliable so manually reset internal state machine.
1621 CSR_WRITE_2(sc, VTE_MACSM, 0x0002);
1622 CSR_WRITE_2(sc, VTE_MACSM, 0);
1629 struct vte_softc *sc;
1631 sc = (struct vte_softc *)xsc;
1633 vte_init_locked(sc);
1638 vte_init_locked(struct vte_softc *sc)
1644 VTE_LOCK_ASSERT(sc);
1648 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1651 * Cancel any pending I/O.
1655 * Reset the chip to a known state.
1659 /* Initialize RX descriptors. */
1660 if (vte_init_rx_ring(sc) != 0) {
1661 device_printf(sc->vte_dev, "no memory for RX buffers.\n");
1665 if (vte_init_tx_ring(sc) != 0) {
1666 device_printf(sc->vte_dev, "no memory for TX buffers.\n");
1672 * Reprogram the station address. Controller supports up
1673 * to 4 different station addresses so driver programs the
1674 * first station address as its own ethernet address and
1675 * configure the remaining three addresses as perfect
1676 * multicast addresses.
1678 eaddr = IF_LLADDR(sc->vte_ifp);
1679 CSR_WRITE_2(sc, VTE_MID0L, eaddr[1] << 8 | eaddr[0]);
1680 CSR_WRITE_2(sc, VTE_MID0M, eaddr[3] << 8 | eaddr[2]);
1681 CSR_WRITE_2(sc, VTE_MID0H, eaddr[5] << 8 | eaddr[4]);
1683 /* Set TX descriptor base addresses. */
1684 paddr = sc->vte_cdata.vte_tx_ring_paddr;
1685 CSR_WRITE_2(sc, VTE_MTDSA1, paddr >> 16);
1686 CSR_WRITE_2(sc, VTE_MTDSA0, paddr & 0xFFFF);
1687 /* Set RX descriptor base addresses. */
1688 paddr = sc->vte_cdata.vte_rx_ring_paddr;
1689 CSR_WRITE_2(sc, VTE_MRDSA1, paddr >> 16);
1690 CSR_WRITE_2(sc, VTE_MRDSA0, paddr & 0xFFFF);
1692 * Initialize RX descriptor residue counter and set RX
1693 * pause threshold to 20% of available RX descriptors.
1694 * See comments on vte_rxeof() for details on flow control
1697 CSR_WRITE_2(sc, VTE_MRDCR, (VTE_RX_RING_CNT & VTE_MRDCR_RESIDUE_MASK) |
1698 (((VTE_RX_RING_CNT * 2) / 10) << VTE_MRDCR_RX_PAUSE_THRESH_SHIFT));
1701 * Always use maximum frame size that controller can
1702 * support. Otherwise received frames that has longer
1703 * frame length than vte(4) MTU would be silently dropped
1704 * in controller. This would break path-MTU discovery as
1705 * sender wouldn't get any responses from receiver. The
1706 * RX buffer size should be multiple of 4.
1707 * Note, jumbo frames are silently ignored by controller
1708 * and even MAC counters do not detect them.
1710 CSR_WRITE_2(sc, VTE_MRBSR, VTE_RX_BUF_SIZE_MAX);
1712 /* Configure FIFO. */
1713 CSR_WRITE_2(sc, VTE_MBCR, MBCR_FIFO_XFER_LENGTH_16 |
1714 MBCR_TX_FIFO_THRESH_64 | MBCR_RX_FIFO_THRESH_16 |
1715 MBCR_SDRAM_BUS_REQ_TIMER_DEFAULT);
1718 * Configure TX/RX MACs. Actual resolved duplex and flow
1719 * control configuration is done after detecting a valid
1720 * link. Note, we don't generate early interrupt here
1721 * as well since FreeBSD does not have interrupt latency
1722 * problems like Windows.
1724 CSR_WRITE_2(sc, VTE_MCR0, MCR0_ACCPT_LONG_PKT);
1726 * We manually keep track of PHY status changes to
1727 * configure resolved duplex and flow control since only
1728 * duplex configuration can be automatically reflected to
1731 CSR_WRITE_2(sc, VTE_MCR1, MCR1_PKT_LENGTH_1537 |
1732 MCR1_EXCESS_COL_RETRY_16);
1734 /* Initialize RX filter. */
1737 /* Disable TX/RX interrupt moderation control. */
1738 CSR_WRITE_2(sc, VTE_MRICR, 0);
1739 CSR_WRITE_2(sc, VTE_MTICR, 0);
1741 /* Enable MAC event counter interrupts. */
1742 CSR_WRITE_2(sc, VTE_MECIER, VTE_MECIER_INTRS);
1743 /* Clear MAC statistics. */
1744 vte_stats_clear(sc);
1746 /* Acknowledge all pending interrupts and clear it. */
1747 CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS);
1748 CSR_WRITE_2(sc, VTE_MISR, 0);
1750 sc->vte_flags &= ~VTE_FLAG_LINK;
1751 /* Switch to the current media. */
1752 vte_mediachange_locked(ifp);
1754 callout_reset(&sc->vte_tick_ch, hz, vte_tick, sc);
1756 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1757 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1761 vte_stop(struct vte_softc *sc)
1764 struct vte_txdesc *txd;
1765 struct vte_rxdesc *rxd;
1768 VTE_LOCK_ASSERT(sc);
1770 * Mark the interface down and cancel the watchdog timer.
1773 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1774 sc->vte_flags &= ~VTE_FLAG_LINK;
1775 callout_stop(&sc->vte_tick_ch);
1776 sc->vte_watchdog_timer = 0;
1777 vte_stats_update(sc);
1778 /* Disable interrupts. */
1779 CSR_WRITE_2(sc, VTE_MIER, 0);
1780 CSR_WRITE_2(sc, VTE_MECIER, 0);
1781 /* Stop RX/TX MACs. */
1783 /* Clear interrupts. */
1784 CSR_READ_2(sc, VTE_MISR);
1786 * Free TX/RX mbufs still in the queues.
1788 for (i = 0; i < VTE_RX_RING_CNT; i++) {
1789 rxd = &sc->vte_cdata.vte_rxdesc[i];
1790 if (rxd->rx_m != NULL) {
1791 bus_dmamap_sync(sc->vte_cdata.vte_rx_tag,
1792 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
1793 bus_dmamap_unload(sc->vte_cdata.vte_rx_tag,
1799 for (i = 0; i < VTE_TX_RING_CNT; i++) {
1800 txd = &sc->vte_cdata.vte_txdesc[i];
1801 if (txd->tx_m != NULL) {
1802 bus_dmamap_sync(sc->vte_cdata.vte_tx_tag,
1803 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
1804 bus_dmamap_unload(sc->vte_cdata.vte_tx_tag,
1806 if ((txd->tx_flags & VTE_TXMBUF) == 0)
1809 txd->tx_flags &= ~VTE_TXMBUF;
1812 /* Free TX mbuf pools used for deep copy. */
1813 for (i = 0; i < VTE_TX_RING_CNT; i++) {
1814 if (sc->vte_cdata.vte_txmbufs[i] != NULL) {
1815 m_freem(sc->vte_cdata.vte_txmbufs[i]);
1816 sc->vte_cdata.vte_txmbufs[i] = NULL;
1822 vte_start_mac(struct vte_softc *sc)
1827 VTE_LOCK_ASSERT(sc);
1829 /* Enable RX/TX MACs. */
1830 mcr = CSR_READ_2(sc, VTE_MCR0);
1831 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) !=
1832 (MCR0_RX_ENB | MCR0_TX_ENB)) {
1833 mcr |= MCR0_RX_ENB | MCR0_TX_ENB;
1834 CSR_WRITE_2(sc, VTE_MCR0, mcr);
1835 for (i = VTE_TIMEOUT; i > 0; i--) {
1836 mcr = CSR_READ_2(sc, VTE_MCR0);
1837 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) ==
1838 (MCR0_RX_ENB | MCR0_TX_ENB))
1843 device_printf(sc->vte_dev,
1844 "could not enable RX/TX MAC(0x%04x)!\n", mcr);
1849 vte_stop_mac(struct vte_softc *sc)
1854 VTE_LOCK_ASSERT(sc);
1856 /* Disable RX/TX MACs. */
1857 mcr = CSR_READ_2(sc, VTE_MCR0);
1858 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) != 0) {
1859 mcr &= ~(MCR0_RX_ENB | MCR0_TX_ENB);
1860 CSR_WRITE_2(sc, VTE_MCR0, mcr);
1861 for (i = VTE_TIMEOUT; i > 0; i--) {
1862 mcr = CSR_READ_2(sc, VTE_MCR0);
1863 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) == 0)
1868 device_printf(sc->vte_dev,
1869 "could not disable RX/TX MAC(0x%04x)!\n", mcr);
1874 vte_init_tx_ring(struct vte_softc *sc)
1876 struct vte_tx_desc *desc;
1877 struct vte_txdesc *txd;
1881 VTE_LOCK_ASSERT(sc);
1883 sc->vte_cdata.vte_tx_prod = 0;
1884 sc->vte_cdata.vte_tx_cons = 0;
1885 sc->vte_cdata.vte_tx_cnt = 0;
1887 /* Pre-allocate TX mbufs for deep copy. */
1888 if (tx_deep_copy != 0) {
1889 for (i = 0; i < VTE_TX_RING_CNT; i++) {
1890 sc->vte_cdata.vte_txmbufs[i] = m_getcl(M_NOWAIT,
1892 if (sc->vte_cdata.vte_txmbufs[i] == NULL)
1894 sc->vte_cdata.vte_txmbufs[i]->m_pkthdr.len = MCLBYTES;
1895 sc->vte_cdata.vte_txmbufs[i]->m_len = MCLBYTES;
1898 desc = sc->vte_cdata.vte_tx_ring;
1899 bzero(desc, VTE_TX_RING_SZ);
1900 for (i = 0; i < VTE_TX_RING_CNT; i++) {
1901 txd = &sc->vte_cdata.vte_txdesc[i];
1903 if (i != VTE_TX_RING_CNT - 1)
1904 addr = sc->vte_cdata.vte_tx_ring_paddr +
1905 sizeof(struct vte_tx_desc) * (i + 1);
1907 addr = sc->vte_cdata.vte_tx_ring_paddr +
1908 sizeof(struct vte_tx_desc) * 0;
1909 desc = &sc->vte_cdata.vte_tx_ring[i];
1910 desc->dtnp = htole32(addr);
1911 txd->tx_desc = desc;
1914 bus_dmamap_sync(sc->vte_cdata.vte_tx_ring_tag,
1915 sc->vte_cdata.vte_tx_ring_map, BUS_DMASYNC_PREREAD |
1916 BUS_DMASYNC_PREWRITE);
1921 vte_init_rx_ring(struct vte_softc *sc)
1923 struct vte_rx_desc *desc;
1924 struct vte_rxdesc *rxd;
1928 VTE_LOCK_ASSERT(sc);
1930 sc->vte_cdata.vte_rx_cons = 0;
1931 desc = sc->vte_cdata.vte_rx_ring;
1932 bzero(desc, VTE_RX_RING_SZ);
1933 for (i = 0; i < VTE_RX_RING_CNT; i++) {
1934 rxd = &sc->vte_cdata.vte_rxdesc[i];
1936 if (i != VTE_RX_RING_CNT - 1)
1937 addr = sc->vte_cdata.vte_rx_ring_paddr +
1938 sizeof(struct vte_rx_desc) * (i + 1);
1940 addr = sc->vte_cdata.vte_rx_ring_paddr +
1941 sizeof(struct vte_rx_desc) * 0;
1942 desc = &sc->vte_cdata.vte_rx_ring[i];
1943 desc->drnp = htole32(addr);
1944 rxd->rx_desc = desc;
1945 if (vte_newbuf(sc, rxd) != 0)
1949 bus_dmamap_sync(sc->vte_cdata.vte_rx_ring_tag,
1950 sc->vte_cdata.vte_rx_ring_map, BUS_DMASYNC_PREREAD |
1951 BUS_DMASYNC_PREWRITE);
1957 vte_rxfilter(struct vte_softc *sc)
1960 struct ifmultiaddr *ifma;
1963 uint16_t rxfilt_perf[VTE_RXFILT_PERFECT_CNT][3];
1964 uint16_t mchash[4], mcr;
1967 VTE_LOCK_ASSERT(sc);
1971 bzero(mchash, sizeof(mchash));
1972 for (i = 0; i < VTE_RXFILT_PERFECT_CNT; i++) {
1973 rxfilt_perf[i][0] = 0xFFFF;
1974 rxfilt_perf[i][1] = 0xFFFF;
1975 rxfilt_perf[i][2] = 0xFFFF;
1978 mcr = CSR_READ_2(sc, VTE_MCR0);
1979 mcr &= ~(MCR0_PROMISC | MCR0_MULTICAST);
1980 mcr |= MCR0_BROADCAST_DIS;
1981 if ((ifp->if_flags & IFF_BROADCAST) != 0)
1982 mcr &= ~MCR0_BROADCAST_DIS;
1983 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
1984 if ((ifp->if_flags & IFF_PROMISC) != 0)
1985 mcr |= MCR0_PROMISC;
1986 if ((ifp->if_flags & IFF_ALLMULTI) != 0)
1987 mcr |= MCR0_MULTICAST;
1996 if_maddr_rlock(ifp);
1997 TAILQ_FOREACH(ifma, &sc->vte_ifp->if_multiaddrs, ifma_link) {
1998 if (ifma->ifma_addr->sa_family != AF_LINK)
2001 * Program the first 3 multicast groups into
2002 * the perfect filter. For all others, use the
2005 if (nperf < VTE_RXFILT_PERFECT_CNT) {
2006 eaddr = LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
2007 rxfilt_perf[nperf][0] = eaddr[1] << 8 | eaddr[0];
2008 rxfilt_perf[nperf][1] = eaddr[3] << 8 | eaddr[2];
2009 rxfilt_perf[nperf][2] = eaddr[5] << 8 | eaddr[4];
2013 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
2014 ifma->ifma_addr), ETHER_ADDR_LEN);
2015 mchash[crc >> 30] |= 1 << ((crc >> 26) & 0x0F);
2017 if_maddr_runlock(ifp);
2018 if (mchash[0] != 0 || mchash[1] != 0 || mchash[2] != 0 ||
2020 mcr |= MCR0_MULTICAST;
2023 /* Program multicast hash table. */
2024 CSR_WRITE_2(sc, VTE_MAR0, mchash[0]);
2025 CSR_WRITE_2(sc, VTE_MAR1, mchash[1]);
2026 CSR_WRITE_2(sc, VTE_MAR2, mchash[2]);
2027 CSR_WRITE_2(sc, VTE_MAR3, mchash[3]);
2028 /* Program perfect filter table. */
2029 for (i = 0; i < VTE_RXFILT_PERFECT_CNT; i++) {
2030 CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 0,
2032 CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 2,
2034 CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 4,
2037 CSR_WRITE_2(sc, VTE_MCR0, mcr);
2038 CSR_READ_2(sc, VTE_MCR0);
2042 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
2048 value = *(int *)arg1;
2049 error = sysctl_handle_int(oidp, &value, 0, req);
2050 if (error || req->newptr == NULL)
2052 if (value < low || value > high)
2054 *(int *)arg1 = value;
2060 sysctl_hw_vte_int_mod(SYSCTL_HANDLER_ARGS)
2063 return (sysctl_int_range(oidp, arg1, arg2, req,
2064 VTE_IM_BUNDLE_MIN, VTE_IM_BUNDLE_MAX));