2 * Copyright(c) 2002-2011 Exar Corp.
5 * Redistribution and use in source and binary forms, with or without
6 * modification are permitted provided the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of the Exar Corporation nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
33 #ifndef VXGE_HAL_REGDEFS_H
34 #define VXGE_HAL_REGDEFS_H
38 #define VXGE_HAL_TITAN_ASIC_ID_GET_INITIAL_DEVICE_ID(bits) bVAL16(bits, 0)
39 #define VXGE_HAL_TITAN_ASIC_ID_GET_INITIAL_MAJOR_REVISION(bits) bVAL8(bits, 48)
40 #define VXGE_HAL_TITAN_ASIC_ID_GET_INITIAL_MINOR_REVISION(bits) bVAL8(bits, 56)
42 #define VXGE_HAL_VPD_LEN 80
43 #define VXGE_HAL_CARD_TITAN_VPD_ADDR 0x80
44 #define VPD_READ_COMPLETE 0x80
46 #define VXGE_HAL_VPATH_TO_FUNC_MAP_CFG1_GET_CFG1(bits) bVAL5(bits, 3)
48 #define VXGE_HAL_DEBUG_ASSIGNMENTS_GET_VHLABEL(bits) bVAL5(bits, 3)
49 #define VXGE_HAL_DEBUG_ASSIGNMENTS_GET_VPLANE(bits) bVAL5(bits, 11)
50 #define VXGE_HAL_DEBUG_ASSIGNMENTS_GET_FUNC(bits) bVAL5(bits, 19)
52 #define VXGE_HAL_HOST_TYPE_ASSIGNMENTS_GET_HOST_TYPE_ASSIGNMENTS(bits)\
54 #define VXGE_HAL_VPLANE_ASSIGNMENTS_GET_VPLANE_ASSIGNMENTS(bits) \
57 #define VXGE_HAL_PF_SW_RESET_COMMAND 0xA5
59 #define VXGE_HAL_TITAN_PCICFGMGMT_REG_SPACES 17
60 #define VXGE_HAL_TITAN_SRPCIM_REG_SPACES 17
61 #define VXGE_HAL_TITAN_VPMGMT_REG_SPACES 17
62 #define VXGE_HAL_TITAN_VPATH_REG_SPACES 17
64 #define VXGE_HAL_PRIV_VPATH_ACTION 5
65 #define VXGE_HAL_BW_CONTROL 12
66 #define VXGE_HAL_RTS_ACCESS_FW_MEMO_ACTION_NON_PRIV_BANDWIDTH_CTRL 32
67 #define VXGE_HAL_RTS_ACCESS_FW_MEMO_ACTION_PRIV_NWIF 17
68 #define VXGE_HAL_API_FUNC_MODE_COMMIT 21
70 #define VXGE_HAL_ASIC_MODE_RESERVED 0
71 #define VXGE_HAL_ASIC_MODE_NO_IOV 1
72 #define VXGE_HAL_ASIC_MODE_SR_IOV 2
73 #define VXGE_HAL_ASIC_MODE_MR_IOV 3
75 #define VXGE_HAL_TXMAC_GEN_CFG1_TMAC_PERMA_STOP_EN mBIT(3)
76 #define VXGE_HAL_TXMAC_GEN_CFG1_BLOCK_BCAST_TO_WIRE mBIT(19)
77 #define VXGE_HAL_TXMAC_GEN_CFG1_BLOCK_BCAST_TO_SWITCH mBIT(23)
78 #define VXGE_HAL_TXMAC_GEN_CFG1_HOST_APPEND_FCS mBIT(31)
80 #define VXGE_HAL_VPATH_IS_FIRST_GET_VPATH_IS_FIRST(bits) bVAL1(bits, 3)
82 #define VXGE_HAL_TIM_VPATH_ASSIGNMENT_GET_BMAP_ROOT(bits) bVAL32(bits, 0)
84 #define VXGE_HAL_RXMAC_CFG0_PORT_VPMGMT_CLONE_GET_MAX_PYLD_LEN(bits)\
87 #define VXGE_HAL_XMAC_VSPORT_CHOICES_VP_GET_VSPORT_VECTOR(bits) bVAL17(bits, 0)
89 #define VXGE_HAL_XMAC_VPATH_TO_VSPORT_VPMGMT_CLONE_GET_VSPORT_NUMBER(bits)\
92 #define VXGE_HAL_KDFC_DRBL_TRIPLET_TOTAL_GET_KDFC_MAX_SIZE(bits)\
95 #define VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_MODE_LEGACY_MODE 0
96 #define VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_MODE_NON_OFFLOAD_ONLY 1
97 #define VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_MODE_MULTI_OP_MODE 2
99 #define VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_MODE_MESSAGES_ONLY 0
100 #define VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_MODE_MULTI_OP_MODE 1
102 #define VXGE_HAL_TOC_GET_KDFC_INITIAL_OFFSET(val)\
103 (val&~VXGE_HAL_TOC_KDFC_INITIAL_BIR(7))
104 #define VXGE_HAL_TOC_GET_KDFC_INITIAL_BIR(val) bVAL3(val, 61)
105 #define VXGE_HAL_TOC_GET_USDC_INITIAL_OFFSET(val)\
106 (val&~VXGE_HAL_TOC_USDC_INITIAL_BIR(7))
107 #define VXGE_HAL_TOC_GET_USDC_INITIAL_BIR(val) bVAL3(val, 61)
109 #define VXGE_HAL_LAG_CFG_GET_MODE(bits) bVAL2(bits, 6)
110 #define VXGE_HAL_LAG_TX_CFG_GET_DISTRIB_ALG_SEL(bits) bVAL2(bits, 6)
112 #define VXGE_HAL_TOC_KDFC_VPATH_STRIDE_GET_TOC_KDFC_VPATH_STRIDE(bits) bits
113 #define VXGE_HAL_TOC_KDFC_FIFO_STRIDE_GET_TOC_KDFC_FIFO_STRIDE(bits) bits
115 #define VXGE_HAL_KDFC_TRPL_FIFO_OFFSET_GET_KDFC_RCTR0(bits) bVAL15(bits, 1)
116 #define VXGE_HAL_KDFC_TRPL_FIFO_OFFSET_GET_KDFC_RCTR1(bits) bVAL15(bits, 17)
117 #define VXGE_HAL_KDFC_TRPL_FIFO_OFFSET_GET_KDFC_RCTR2(bits) bVAL15(bits, 33)
119 #define VXGE_HAL_KDFC_TRPL_FIFO_OFFSET_KDFC_VAPTH_NUM(val) vBIT(val, 42, 5)
120 #define VXGE_HAL_KDFC_TRPL_FIFO_OFFSET_KDFC_FIFO_NUM(val) vBIT(val, 47, 2)
121 #define VXGE_HAL_KDFC_TRPL_FIFO_OFFSET_KDFC_FIFO_OFFSET(val) vBIT(val, 49, 15)
123 #define VXGE_HAL_PRC_CFG4_RING_MODE_ONE_BUFFER 0
124 #define VXGE_HAL_PRC_CFG4_RING_MODE_THREE_BUFFER 1
125 #define VXGE_HAL_PRC_CFG4_RING_MODE_FIVE_BUFFER 2
127 #define VXGE_HAL_PRC_CFG7_SCATTER_MODE_A 0
128 #define VXGE_HAL_PRC_CFG7_SCATTER_MODE_B 2
129 #define VXGE_HAL_PRC_CFG7_SCATTER_MODE_C 1
131 #define VXGE_HAL_RTDMA_BW_CTRL_GET_DESIRED_BW(bits) bVAL18(bits, 46)
133 #define VXGE_HAL_RTS_MGR_STEER_CTRL_WE_READ 0
134 #define VXGE_HAL_RTS_MGR_STEER_CTRL_WE_WRITE 1
136 #define VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_DA 0
137 #define VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_VID 1
138 #define VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_ETYPE 2
139 #define VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_PN 3
140 #define VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RANGE_PN 4
141 #define VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_GEN_CFG 5
142 #define VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT 6
143 #define VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_JHASH_CFG 7
144 #define VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_MASK 8
145 #define VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_KEY 9
146 #define VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_QOS 10
147 #define VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_DS 11
148 #define VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT 12
149 #define VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO 13
151 #define VXGE_HAL_RTS_MGR_STEER_DATA0_GET_DA_MAC_ADDR(bits) bVAL48(bits, 0)
152 #define VXGE_HAL_RTS_MGR_STEER_DATA0_DA_MAC_ADDR(val) vBIT(val, 0, 48)
154 #define VXGE_HAL_RTS_MGR_STEER_DATA1_GET_DA_MAC_ADDR_MASK(bits) bVAL48(bits, 0)
155 #define VXGE_HAL_RTS_MGR_STEER_DATA1_DA_MAC_ADDR_MASK(val) vBIT(val, 0, 48)
156 #define VXGE_HAL_RTS_MGR_STEER_DATA1_DA_MAC_ADDR_ADD_PRIVILEGED_MODE mBIT(54)
157 #define VXGE_HAL_RTS_MGR_STEER_DATA1_GET_DA_MAC_ADDR_ADD_VPATH(bits)\
159 #define VXGE_HAL_RTS_MGR_STEER_DATA1_DA_MAC_ADDR_ADD_VPATH(val) vBIT(val, 55, 5)
160 #define VXGE_HAL_RTS_MGR_STEER_DATA1_GET_DA_MAC_ADDR_ADD_MODE(bits)\
162 #define VXGE_HAL_RTS_MGR_STEER_DATA1_DA_MAC_ADDR_MODE(val) vBIT(val, 62, 2)
164 #define VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_ADD_ENTRY 0
165 #define VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_DELETE_ENTRY 1
166 #define VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_LIST_FIRST_ENTRY 2
167 #define VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_LIST_NEXT_ENTRY 3
168 #define VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_READ_ENTRY 0
169 #define VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY 1
170 #define VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_CLEAR_TABLE 2
171 #define VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_FW_MEMO_VERSION 0
172 #define VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_FW_MEMO_CARD_INFO 3
173 #define VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_LED_CONTROL 4
174 #define VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_VPATH_MAP 5
175 #define VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_PCI_CONFIG 6
176 #define VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_UDP_RTH 10
177 #define VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_FUNC_MODE 11
178 #define VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_SEND_MSG 15
179 #define VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_FW_UPGRADE 16
180 #define VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_PORT_CTRL 17
181 #define VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_PORT_INFO 18
182 #define VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_COMMIT 21
183 #define VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_GET_FUNC_COUNT 24
184 #define VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_GET_FUNC_MODE 29
185 #define VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_ALL_CLEAR 172
187 #define VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA 0
188 #define VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_VID 1
189 #define VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_ETYPE 2
190 #define VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_PN 3
191 #define VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_GEN_CFG 5
192 #define VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT 6
193 #define VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_JHASH_CFG 7
194 #define VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MASK 8
195 #define VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_KEY 9
196 #define VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_QOS 10
197 #define VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DS 11
198 #define VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT 12
199 #define VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO 13
200 #define VXGE_HAL_MSG_SEND_TO_VPATH_MASK 0xFFFFFFFFUL
201 #define VXGE_HAL_MSG_SEND_RETRY 100
203 #define VXGE_HAL_RTS_ACCESS_STEER_CTRL_OFFSET_FW_UPGRADE_MODE 2
204 #define VXGE_HAL_RTS_ACCESS_STEER_CTRL_OFFSET_FW_UPGRADE_DATA 3
205 #define VXGE_HAL_RTS_ACCESS_STEER_CTRL_OFFSET_FW_UPGRADE_COMMIT 4
207 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_UPGRADE_STREAM_SKIP mBIT(63)
208 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_UPGRADE_GET_RET_CODE(bits) \
210 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_UPGRADE_GET_RET_CODE_OK 0
211 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_UPGRADE_GET_RET_CODE_DONE 1
212 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_UPGRADE_GET_RET_CODE_ERROR 2
213 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_UPGRADE_GET_RET_CODE_SKIP 3
214 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_UPGRADE_GET_SUB_CODE(bits) \
216 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_UPGRADE_GET_SUB_SUB_CODE(bits) \
218 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_UPGRADE_GET_SKIP_BYTES(bits) \
220 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_FW_UPGRADE_GET_TOTAL_STEPS(bits) \
222 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_FW_UPGRADE_GET_COMPL_STEPS(bits) \
225 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_DA_MAC_ADDR(bits) bVAL48(bits, 0)
226 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_DA_MAC_ADDR(val) vBIT(val, 0, 48)
228 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_VLAN_ID(bits) bVAL11(bits, 0)
229 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_VLAN_ID(val) vBIT(val, 0, 12)
231 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_ETYPE(bits) bVAL11(bits, 0)
232 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_ETYPE(val) vBIT(val, 0, 16)
234 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_SEND_MSG_TYPE(val) vBIT(val, 0, 8)
235 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_SEND_MSG_DEST(val) vBIT(val, 8, 8)
236 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_SEND_MSG_SRC(val) vBIT(val, 16, 8)
237 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_SEND_MSG_DATA(val) vBIT(val, 32, 32)
239 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_PN_SRC_DEST_SEL(bits) bVAL1(bits, 3)
240 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_PN_SRC_DEST_SEL mBIT(3)
241 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_PN_TCP_UDP_SEL(bits) bVAL1(bits, 7)
242 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_PN_TCP_UDP_SEL mBIT(7)
243 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_PN_PORT_NUM(bits) bVAL16(bits, 8)
244 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_PN_PORT_NUM(val) vBIT(val, 8, 16)
246 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_EN(bits) bVAL1(bits, 3)
247 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_EN mBIT(3)
248 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_BUCKET_SIZE(bits)\
250 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_BUCKET_SIZE(val) vBIT(val, 4, 4)
251 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_ALG_SEL(bits)\
253 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL(val) vBIT(val, 10, 2)
254 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL_JENKINS 0
255 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL_MS_RSS 1
256 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL_CRC32C 2
257 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_TCP_IPV4_EN(bits)\
259 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV4_EN mBIT(15)
260 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_IPV4_EN(bits)\
262 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV4_EN mBIT(19)
263 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_TCP_IPV6_EN(bits)\
265 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV6_EN mBIT(23)
266 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_IPV6_EN(bits)\
268 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV6_EN mBIT(27)
269 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_TCP_IPV6_EX_EN(bits)\
271 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV6_EX_EN mBIT(31)
272 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_IPV6_EX_EN(bits)\
274 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV6_EX_EN mBIT(35)
275 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_ACTIVE_TABLE(bits)\
277 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_ACTIVE_TABLE mBIT(39)
278 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_REPL_ENTRY_EN(bits)\
280 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_REPL_ENTRY_EN mBIT(43)
282 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_SOLO_IT_ENTRY_EN(bits)\
284 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_ENTRY_EN mBIT(3)
285 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_SOLO_IT_BUCKET_DATA(bits)\
287 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_BUCKET_DATA(val)\
290 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM0_BUCKET_NUM(bits)\
292 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_NUM(val)\
294 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM0_ENTRY_EN(bits)\
296 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_ENTRY_EN mBIT(8)
297 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM0_BUCKET_DATA(bits)\
299 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_DATA(val)\
301 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM1_BUCKET_NUM(bits)\
303 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_NUM(val)\
305 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM1_ENTRY_EN(bits)\
307 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_ENTRY_EN mBIT(24)
308 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM1_BUCKET_DATA(bits)\
310 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_DATA(val)\
312 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM0_BUCKET_NUM(bits)\
314 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_NUM(val)\
316 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM0_ENTRY_EN(bits)\
318 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_ENTRY_EN mBIT(8)
319 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM0_BUCKET_DATA(bits)\
321 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_DATA(val)\
323 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM1_BUCKET_NUM(bits)\
325 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_NUM(val)\
327 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM1_ENTRY_EN(bits)\
329 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_ENTRY_EN mBIT(24)
330 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM1_BUCKET_DATA(bits)\
332 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_DATA(val)\
335 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_JHASH_CFG_GOLDEN_RATIO(bits)\
337 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_JHASH_CFG_GOLDEN_RATIO(val)\
339 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_JHASH_CFG_INIT_VALUE(bits)\
341 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_JHASH_CFG_INIT_VALUE(val)\
344 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_IPV6_SA_MASK(bits)\
346 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV6_SA_MASK(val)\
348 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_IPV6_DA_MASK(bits)\
350 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV6_DA_MASK(val)\
352 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_IPV4_SA_MASK(bits)\
354 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV4_SA_MASK(val)\
356 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_IPV4_DA_MASK(bits)\
358 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV4_DA_MASK(val)\
360 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_L4SP_MASK(bits)\
362 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_MASK_L4SP_MASK(val) vBIT(val, 40, 2)
363 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_L4DP_MASK(bits)\
365 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_MASK_L4DP_MASK(val) vBIT(val, 42, 2)
367 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_KEY_KEY(bits) bVAL64(bits, 0)
368 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_KEY_KEY vBIT(val, 0, 64)
370 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_QOS_ENTRY_EN(bits) bVAL1(bits, 3)
371 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_QOS_ENTRY_EN mBIT(3)
373 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_DS_ENTRY_EN(bits) bVAL1(bits, 3)
374 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_DS_ENTRY_EN mBIT(3)
376 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_DA_MAC_ADDR_MASK(bits)\
378 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_DA_MAC_ADDR_MASK(val) vBIT(val, 0, 48)
379 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_DA_MAC_ADDR_ADD_PRIVILEGED_MODE mBIT(54)
380 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_DA_MAC_ADDR_ADD_VPATH(bits)\
382 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_DA_MAC_ADDR_ADD_VPATH(val)\
384 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_DA_MAC_ADDR_ADD_MODE(bits)\
386 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_DA_MAC_ADDR_MODE(val) vBIT(val, 62, 2)
388 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM4_BUCKET_NUM(bits)\
390 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM4_BUCKET_NUM(val)\
392 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM4_ENTRY_EN(bits)\
394 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM4_ENTRY_EN mBIT(8)
395 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM4_BUCKET_DATA(bits)\
397 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM4_BUCKET_DATA(val)\
399 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM5_BUCKET_NUM(bits)\
401 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM5_BUCKET_NUM(val)\
403 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM5_ENTRY_EN(bits)\
405 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM5_ENTRY_EN mBIT(24)
406 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM5_BUCKET_DATA(bits)\
408 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM5_BUCKET_DATA(val)\
410 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM6_BUCKET_NUM(bits)\
412 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM6_BUCKET_NUM(val)\
414 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM6_ENTRY_EN(bits)\
416 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM6_ENTRY_EN mBIT(40)
417 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM6_BUCKET_DATA(bits)\
419 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM6_BUCKET_DATA(val)\
421 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM7_BUCKET_NUM(bits)\
423 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM7_BUCKET_NUM(val)\
425 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM7_ENTRY_EN(bits)\
427 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM7_ENTRY_EN mBIT(56)
428 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM7_BUCKET_DATA(bits)\
430 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM7_BUCKET_DATA(val)\
433 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_FW_VERSION 0
434 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PART_NUMBER 0
435 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_SERIAL_NUMBER 1
436 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_FLASH_VERSION 2
437 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PCI_MODE 3
438 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_0 4
439 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_1 5
440 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_2 6
441 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_3 7
442 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORTS 8
444 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORT0_PMD_TYPE 10
445 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORT0_PMD_VENDOR 11
446 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORT0_PMD_PARTNO 13
447 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORT0_PMD_SERNO 14
449 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORT1_PMD_TYPE 20
450 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORT1_PMD_VENDOR 21
451 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORT1_PMD_PARTNO 23
452 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORT1_PMD_SERNO 24
454 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_LAG_MODE 1
455 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_ACTIVE_PORT 2
457 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_MEMO_ITEM_STATUS(bits) \
459 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_STATUS(val) \
461 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_STATUS_SUCCESS 1
462 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_STATUS_FAIL 0
464 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_MEMO_ITEM_GET_LAG_MODE(bits) \
466 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_MEMO_ITEM_LAG_MODE(val) \
469 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_MEMO_ITEM_PREFFERRED_PORT mBIT(62)
470 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_MEMO_ITEM_ACTIVE_PORT mBIT(63)
472 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_LED_CONTROL_ON 1
473 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_LED_CONTROL_OFF 0
475 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_PCI_ADDR(bits) bVAL16(bits, 16)
476 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_PCI_ADDR(val) vBIT(val, 16, 16)
477 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_PCI_CONFIG_READ 0
478 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_PCI_CONFIG_WRITE mBIT(39)
479 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_BYTE_COUNT(bits) bVAL8(bits, 40)
480 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_BYTE_COUNT(val) vBIT(val, 40, 8)
482 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_VH(bits) bVAL8(bits, 48)
483 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_VH(val) vBIT(val, 48, 8)
484 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FUNCTION(bits) bVAL8(bits, 56)
485 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNCTION(val) vBIT(val, 56, 8)
487 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_PCI_DATA(bits) bVAL32(bits, 32)
488 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_PCI_DATA(val) vBIT(val, 32, 32)
490 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_PCI_DATA(bits) bVAL32(bits, 32)
491 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_PCI_DATA(val) vBIT(val, 32, 32)
493 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_IS_VPATH_ASSIGNED(vpid) mBIT((63-vpid))
495 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_IGNORE_IN_SVC_CHECK mBIT(0)
496 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_MSG_TYPE(bits) bVAL7(bits, 1)
497 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE(val) vBIT(val, 1, 7)
498 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_UNKNOWN 0
499 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_DEVICE_RESET_BEGIN 1
500 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_DEVICE_RESET_END 2
501 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_VPATH_RESET_BEGIN 3
502 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_VPATH_RESET_END 4
503 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_PRIV_DRIVER_UP 5
504 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_PRIV_DRIVER_DOWN 6
505 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_ACK 127
506 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_MSG_DEST(bits) bVAL8(bits, 8)
507 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_DEST(val) vBIT(val, 8, 8)
508 #define VXGE_HAL_RTS_ACCESS_STEER_MSG_DEST_MRPCIM 0xfe
509 #define VXGE_HAL_RTS_ACCESS_STEER_MSG_DEST_BROADCAST 0xff
510 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_MSG_SRC(bits) bVAL8(bits, 16)
511 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_SRC(val) vBIT(val, 16, 8)
512 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_SEQ_NUM(bits) bVAL32(bits, 16)
513 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_SEQ_NUM(val) vBIT(val, 32, 16)
514 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_MSG_DATA(bits) bVAL16(bits, 48)
515 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_DATA(val) vBIT(val, 48, 16)
517 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_ERROR_PENDING 0
518 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_ERROR_NOT_IN_SVC 1
520 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_UDP_RTH_ENABLE mBIT(63)
522 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_VHN(val) vBIT(val, 48, 8)
523 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_VFID(val) vBIT(val, 56, 8)
525 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RX_PRIORITY(bits) bVAL3(bits, 45)
526 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RX_MIN_BW(bits) bVAL8(bits, 48)
527 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RX_MAX_BW(bits) bVAL8(bits, 56)
529 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_SET_RX_PRIORITY(val) vBIT(val, 45, 3)
530 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_SET_RX_MIN_BW(val) vBIT(val, 48, 8)
531 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_SET_RX_MAX_BW(val) vBIT(val, 56, 8)
532 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_SET_VPATH_OR_FUNC(val) vBIT(val, 0, 8)
534 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_TX_PRIORITY(bits) bVAL3(bits, 21)
535 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_TX_MIN_BW(bits) bVAL8(bits, 24)
536 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_TX_MAX_BW(bits) bVAL8(bits, 32)
538 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_SET_TX_PRIORITY(val) vBIT(val, 21, 3)
539 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_SET_TX_MIN_BW(val) vBIT(val, 24, 8)
540 #define VXGE_HAL_RTS_ACCESS_STEER_DATA1_SET_TX_MAX_BW(val) vBIT(val, 32, 8)
542 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_NUM_FUNC(bits) bVAL8(bits, 32)
543 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FUNC_MODE(bits) bVAL8(bits, 56)
544 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE(val) vBIT(val, 56, 8)
545 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_SF1_VP17 0
546 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_MF8_VP2 1
547 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_SR17_VP1 2
548 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_MR17_VP1 3
549 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_MR8_VP2 4
550 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_MF17_VP1 5
551 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_SR8_VP2 6
552 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_SR4_VP4 7
553 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_MF2_VP8 8
554 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_MF4_VP4 9
555 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_MR4_VP4 10
556 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_MF8P_VP2 11
558 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FW_VER_DAY(bits)\
560 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_VER_DAY(val) vBIT(val, 0, 8)
561 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MONTH(bits)\
563 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_VER_MONTH(val) vBIT(val, 8, 8)
564 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FW_VER_YEAR(bits) bVAL16(bits, 16)
565 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_VER_YEAR(val) vBIT(val, 16, 16)
567 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MAJOR(bits)\
569 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_VER_MAJOR vBIT(val, 32, 8)
570 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MINOR(bits)\
572 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_VER_MINOR vBIT(val, 40, 8)
573 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FW_VER_BUILD(bits)\
575 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_VER_BUILD vBIT(val, 48, 16)
577 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FLASH_VER_DAY(bits)\
579 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FLASH_VER_DAY(val) vBIT(val, 0, 8)
580 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FLASH_VER_MONTH(bits)\
582 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FLASH_VER_MONTH(val) vBIT(val, 8, 8)
583 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FLASH_VER_YEAR(bits)\
585 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FLASH_VER_YEAR(val) vBIT(val, 16, 16)
587 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FLASH_VER_MAJOR(bits)\
589 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FLASH_VER_MAJOR vBIT(val, 32, 8)
590 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FLASH_VER_MINOR(bits)\
592 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FLASH_VER_MINOR vBIT(val, 40, 8)
593 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FLASH_VER_BUILD(bits)\
595 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_FLASH_VER_BUILD vBIT(val, 48, 16)
597 /* Netork port control API related */
598 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_SET_NWIF_CMD(val) vBIT(val, 0, 8)
600 /* Bandwidth & priority related MACROS */
601 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_API_VER(bits) \
602 vxge_bVALn(bits, 0, 8)
604 #define VXGE_HAL_ASIC_NTWK_VP_CTRL_GET_XMACJ_SHOW_PORT_INFO(bits)\
606 #define VXGE_HAL_ASIC_NTWK_VP_CTRL_GET_XMACJ_PORT_NUM(bits) bVAL1(bits, 63)
608 #define VXGE_HAL_SRPCIM_TO_VPATH_ALARM_REG_GET_ALARM(bits) bVAL17(bits, 0)
610 #define VXGE_HAL_RX_MULTI_CAST_STATS_GET_FRAME_DISCARD(bits) bVAL16(bits, 48)
611 #define VXGE_HAL_RX_FRM_TRANSFERRED_GET_RX_FRM_TRANSFERRED(bits)\
613 #define VXGE_HAL_RXD_RETURNED_GET_RXD_RETURNED(bits) bVAL16(bits, 48)
614 #define VXGE_HAL_PRC_RXD_DOORBELL_GET_NEW_QW_CNT(bits) bVAL16(bits, 48)
615 #define VXGE_HAL_PRC_CFG6_GET_RXD_SPAT(bits) bVAL9(bits, 36)
616 #define VXGE_HAL_VPATH_DEBUG_STATS0_GET_INI_NUM_MWR_SENT(bits) bVAL32(bits, 0)
617 #define VXGE_HAL_VPATH_DEBUG_STATS1_GET_INI_NUM_MRD_SENT(bits) bVAL32(bits, 0)
618 #define VXGE_HAL_VPATH_DEBUG_STATS2_GET_INI_NUM_CPL_RCVD(bits) bVAL32(bits, 0)
619 #define VXGE_HAL_VPATH_DEBUG_STATS3_GET_INI_NUM_MWR_BYTE_SENT(bits) (bits)
620 #define VXGE_HAL_VPATH_DEBUG_STATS4_GET_INI_NUM_CPL_BYTE_RCVD(bits) (bits)
621 #define VXGE_HAL_VPATH_DEBUG_STATS5_GET_WRCRDTARB_XOFF(bits) bVAL32(bits, 32)
622 #define VXGE_HAL_VPATH_DEBUG_STATS6_GET_RDCRDTARB_XOFF(bits) bVAL32(bits, 32)
623 #define VXGE_HAL_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT1(bits)\
625 #define VXGE_HAL_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT0(bits)\
627 #define VXGE_HAL_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT3(bits)\
629 #define VXGE_HAL_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT2(bits)\
631 #define VXGE_HAL_VPATH_GENSTATS_COUNT4_GET_PPIF_VPATH_GENSTATS_COUNT4(bits)\
633 #define VXGE_HAL_VPATH_GENSTATS_COUNT5_GET_PPIF_VPATH_GENSTATS_COUNT5(bits)\
636 VXGE_HAL_TX_VP_RESET_DISCARDED_FRMS_GET_TX_VP_RESET_DISCARDED_FRMS(bits)\
638 #define VXGE_HAL_DBG_STATS_GET_RX_MPA_CRC_FAIL_FRMS(bits) bVAL16(bits, 0)
639 #define VXGE_HAL_DBG_STATS_GET_RX_MPA_MRK_FAIL_FRMS(bits) bVAL16(bits, 16)
640 #define VXGE_HAL_DBG_STATS_GET_RX_MPA_LEN_FAIL_FRMS(bits) bVAL16(bits, 32)
641 #define VXGE_HAL_DBG_STATS_GET_RX_FAU_RX_WOL_FRMS(bits) bVAL16(bits, 0)
642 #define VXGE_HAL_DBG_STATS_GET_RX_FAU_RX_VP_RESET_DISCARDED_FRMS(bits)\
644 #define VXGE_HAL_DBG_STATS_GET_RX_FAU_RX_PERMITTED_FRMS(bits) bVAL16(bits, 32)
646 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_ADDR 0x0
647 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_WRITE 0x1
648 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_READ_INCR 0x2
649 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_READ 0x3
650 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_RESERVED 0x4
651 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_ADDR_WRITE 0x5
652 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_ADDR_READ_INCR 0x6
653 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_ADDR_READ 0x7
655 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_PMA_CONTROL_1 0x0000
656 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_PMA_CONTROL_1_LOOPBACK 0x01
658 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_CONTROL 0x8000
659 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_CONTROL_1_BYTE 0x02
660 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_CONTROL_256_BYTES 0x03
661 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_CONTROL_COMPLETE 0x04
662 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_CONTROL_PROGRESS 0x08
663 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_CONTROL_FAILED 0x0C
664 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_CONTROL_STAT_MASK 0x0C
665 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_CONTROL_READ 0x00
666 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_CONTROL_WRITE 0x20
667 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_CONTROL_ADDR(val) (val<<8)
669 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_DATA_XFP_TEMP_1 0x8067
670 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_DATA_XFP_TEMP_2 0x8068
671 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_DATA_DATA(val)\
674 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_ALARM_FLAG 0xA070
675 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_ALARM_FLAG_PWR_LOW 0x01
676 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_ALARM_FLAG_PWR_HIGH 0x02
677 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_ALARM_FLAG_CUR_LOW 0x04
678 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_ALARM_FLAG_CUR_HIGH 0x08
679 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_ALARM_FLAG_TEMP_LOW 0x40
680 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_ALARM_FLAG_TEMP_HIGH 0x80
682 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_WARN_FLAG 0xA074
683 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_WARN_FLAG_PWR_LOW 0x01
684 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_WARN_FLAG_PWR_HIGH 0x02
685 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_WARN_FLAG_CUR_LOW 0x04
686 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_WARN_FLAG_CUR_HIGH 0x08
687 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_WARN_FLAG_TEMP_LOW 0x40
688 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_WARN_FLAG_TEMP_HIGH 0x80
690 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_CMD_STAT 0xA100
691 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_CMD_STAT_SINGLE_UPDATE 0x0000
692 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_CMD_STAT_SLOW_PER_UPDATE 0x0001
693 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_CMD_STAT_INT_PER_UPDATE 0x0002
694 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_CMD_STAT_FAST_PER_UPDATE 0x0003
695 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_CMD_STAT_READ_IDLE 0x0000
696 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_CMD_STAT_READ_COMPLETE 0x0004
697 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_CMD_STAT_READ_PROGRESS 0x0008
698 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_CMD_STAT_READ_FAILED 0x000C
699 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_CMD_STAT_UPLOAD_EN 0x0010
700 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_CMD_STAT_256_BYTES 0x0000
701 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_CMD_STAT_1_BYTES 0x0100
702 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_CMD_STAT_WRITE_IDLE 0x0000
703 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_CMD_STAT_WRITE_COMPLETE 0x1000
704 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_CMD_STAT_WRITE_PROGRESS 0x2000
705 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_CMD_STAT_WRITE_FAILED 0x3000
708 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_TX_LED 0xD006
709 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_RX_LED 0xD007
710 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_LINK_LED 0xD008
712 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_DEVAD_PMA_PMD 1
713 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_DEVAD_PCS 3
714 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_DEVAD_PHY_XS 4
715 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_DEVAD_DTE_XS 5
716 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_DEVAD_AN 7
718 #define VXGE_HAL_MDIO_GEN_CFG_PORT_GET_MDIO_PHY_PRTAD(bits) bVAL5(bits, 19)
719 #define VXGE_HAL_MDIO_GEN_CFG_PORT_MDIO_PHY_PRTAD(val) vBIT(val, 19, 5)
721 #define VXGE_HAL_XGXS_STATIC_CFG_PORT_GET_MDIO_DTE_PRTAD(bits) bVAL5(bits, 7)
722 #define VXGE_HAL_XGXS_STATIC_CFG_PORT_MDIO_DTE_PRTAD(val) vBIT(val, 7, 5)
724 #define VXGE_HAL_MDIO_MGR_ACCESS_GET_PORT_DATA(bits) bVAL16(bits, 32)
726 #define VXGE_HAL_MRPCIM_DEBUG_STATS0_GET_INI_WR_DROP(bits) bVAL32(bits, 0)
727 #define VXGE_HAL_MRPCIM_DEBUG_STATS0_GET_INI_RD_DROP(bits) bVAL32(bits, 32)
729 VXGE_HAL_MRPCIM_DEBUG_STATS1_GET_VPLANE_WRCRDTARB_PH_CRDT_DEPLETED(bits)\
732 VXGE_HAL_MRPCIM_DEBUG_STATS2_GET_VPLANE_WRCRDTARB_PD_CRDT_DEPLETED(bits)\
735 VXGE_HAL_MRPCIM_DEBUG_STATS3_GET_VPLANE_RDCRDTARB_NPH_CRDT_DEPLETED(bits)\
737 #define VXGE_HAL_MRPCIM_DEBUG_STATS4_GET_INI_WR_VPIN_DROP(bits) bVAL32(bits, 0)
738 #define VXGE_HAL_MRPCIM_DEBUG_STATS4_GET_INI_RD_VPIN_DROP(bits) bVAL32(bits, 32)
739 #define VXGE_HAL_GENSTATS_COUNT01_GET_GENSTATS_COUNT1(bits) bVAL32(bits, 0)
740 #define VXGE_HAL_GENSTATS_COUNT01_GET_GENSTATS_COUNT0(bits) bVAL32(bits, 32)
741 #define VXGE_HAL_GENSTATS_COUNT23_GET_GENSTATS_COUNT3(bits) bVAL32(bits, 0)
742 #define VXGE_HAL_GENSTATS_COUNT23_GET_GENSTATS_COUNT2(bits) bVAL32(bits, 32)
743 #define VXGE_HAL_GENSTATS_COUNT4_GET_GENSTATS_COUNT4(bits) bVAL32(bits, 32)
744 #define VXGE_HAL_GENSTATS_COUNT5_GET_GENSTATS_COUNT5(bits) bVAL32(bits, 32)
746 #define VXGE_HAL_DEBUG_STATS0_GET_RSTDROP_MSG(bits) bVAL32(bits, 0)
747 #define VXGE_HAL_DEBUG_STATS0_GET_RSTDROP_CPL(bits) bVAL32(bits, 32)
748 #define VXGE_HAL_DEBUG_STATS1_GET_RSTDROP_CLIENT0(bits) bVAL32(bits, 0)
749 #define VXGE_HAL_DEBUG_STATS1_GET_RSTDROP_CLIENT1(bits) bVAL32(bits, 32)
750 #define VXGE_HAL_DEBUG_STATS2_GET_RSTDROP_CLIENT2(bits) bVAL32(bits, 0)
751 #define VXGE_HAL_DEBUG_STATS3_GET_VPLANE_DEPL_PH(bits) bVAL16(bits, 0)
752 #define VXGE_HAL_DEBUG_STATS3_GET_VPLANE_DEPL_NPH(bits) bVAL16(bits, 16)
753 #define VXGE_HAL_DEBUG_STATS3_GET_VPLANE_DEPL_CPLH(bits) bVAL16(bits, 32)
754 #define VXGE_HAL_DEBUG_STATS4_GET_VPLANE_DEPL_PD(bits) bVAL16(bits, 0)
755 #define VXGE_HAL_DEBUG_STATS4_GET_VPLANE_DEPL_NPD(bits) bVAL16(bits, 16)
756 #define VXGE_HAL_DEBUG_STATS4_GET_VPLANE_DEPL_CPLD(bits) bVAL16(bits, 32)
758 #define VXGE_HAL_ORP_LRO_EVENTS_GET_ORP_LRO_EVENTS(bits) (bits)
759 #define VXGE_HAL_ORP_BS_EVENTS_GET_ORP_BS_EVENTS(bits) (bits)
760 #define VXGE_HAL_ORP_IWARP_EVENTS_GET_ORP_IWARP_EVENTS(bits) (bits)
761 #define VXGE_HAL_DBG_STATS_TPA_TX_PATH_GET_TX_PERMITTED_FRMS(bits)\
764 #define VXGE_HAL_DBG_STAT_TX_ANY_FRMS_GET_PORT0_TX_ANY_FRMS(bits)\
766 #define VXGE_HAL_DBG_STAT_TX_ANY_FRMS_GET_PORT1_TX_ANY_FRMS(bits)\
768 #define VXGE_HAL_DBG_STAT_TX_ANY_FRMS_GET_PORT2_TX_ANY_FRMS(bits)\
771 #define VXGE_HAL_DBG_STAT_RX_ANY_FRMS_GET_PORT0_RX_ANY_FRMS(bits)\
773 #define VXGE_HAL_DBG_STAT_RX_ANY_FRMS_GET_PORT1_RX_ANY_FRMS(bits)\
775 #define VXGE_HAL_DBG_STAT_RX_ANY_FRMS_GET_PORT2_RX_ANY_FRMS(bits)\
780 #endif /* VXGE_HAL_REGDEFS_H */