2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1997, 1998
5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
35 #include <sys/cdefs.h>
36 __FBSDID("$FreeBSD$");
39 * Winbond fast ethernet PCI NIC driver
41 * Supports various cheap network adapters based on the Winbond W89C840F
42 * fast ethernet controller chip. This includes adapters manufactured by
43 * Winbond itself and some made by Linksys.
45 * Written by Bill Paul <wpaul@ctr.columbia.edu>
46 * Electrical Engineering Department
47 * Columbia University, New York City
50 * The Winbond W89C840F chip is a bus master; in some ways it resembles
51 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has
52 * one major difference which is that while the registers do many of
53 * the same things as a tulip adapter, the offsets are different: where
54 * tulip registers are typically spaced 8 bytes apart, the Winbond
55 * registers are spaced 4 bytes apart. The receiver filter is also
56 * programmed differently.
58 * Like the tulip, the Winbond chip uses small descriptors containing
59 * a status word, a control word and 32-bit areas that can either be used
60 * to point to two external data blocks, or to point to a single block
61 * and another descriptor in a linked list. Descriptors can be grouped
62 * together in blocks to form fixed length rings or can be chained
63 * together in linked lists. A single packet may be spread out over
64 * several descriptors if necessary.
66 * For the receive ring, this driver uses a linked list of descriptors,
67 * each pointing to a single mbuf cluster buffer, which us large enough
68 * to hold an entire packet. The link list is looped back to created a
71 * For transmission, the driver creates a linked list of 'super descriptors'
72 * which each contain several individual descriptors linked toghether.
73 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we
74 * abuse as fragment pointers. This allows us to use a buffer managment
75 * scheme very similar to that used in the ThunderLAN and Etherlink XL
78 * Autonegotiation is performed using the external PHY via the MII bus.
79 * The sample boards I have all use a Davicom PHY.
81 * Note: the author of the Linux driver for the Winbond chip alludes
82 * to some sort of flaw in the chip's design that seems to mandate some
83 * drastic workaround which signigicantly impairs transmit performance.
84 * I have no idea what he's on about: transmit performance with all
85 * three of my test boards seems fine.
88 #include <sys/param.h>
89 #include <sys/systm.h>
90 #include <sys/sockio.h>
92 #include <sys/malloc.h>
93 #include <sys/module.h>
94 #include <sys/kernel.h>
95 #include <sys/socket.h>
96 #include <sys/queue.h>
99 #include <net/if_var.h>
100 #include <net/if_arp.h>
101 #include <net/ethernet.h>
102 #include <net/if_dl.h>
103 #include <net/if_media.h>
104 #include <net/if_types.h>
108 #include <vm/vm.h> /* for vtophys */
109 #include <vm/pmap.h> /* for vtophys */
110 #include <machine/bus.h>
111 #include <machine/resource.h>
113 #include <sys/rman.h>
115 #include <dev/pci/pcireg.h>
116 #include <dev/pci/pcivar.h>
118 #include <dev/mii/mii.h>
119 #include <dev/mii/mii_bitbang.h>
120 #include <dev/mii/miivar.h>
122 /* "device miibus" required. See GENERIC if you get errors here. */
123 #include "miibus_if.h"
125 #define WB_USEIOSPACE
127 #include <dev/wb/if_wbreg.h>
129 MODULE_DEPEND(wb, pci, 1, 1, 1);
130 MODULE_DEPEND(wb, ether, 1, 1, 1);
131 MODULE_DEPEND(wb, miibus, 1, 1, 1);
134 * Various supported device vendors/types and their names.
136 static const struct wb_type wb_devs[] = {
137 { WB_VENDORID, WB_DEVICEID_840F,
138 "Winbond W89C840F 10/100BaseTX" },
139 { CP_VENDORID, CP_DEVICEID_RL100,
140 "Compex RL100-ATX 10/100baseTX" },
144 static int wb_probe(device_t);
145 static int wb_attach(device_t);
146 static int wb_detach(device_t);
148 static void wb_bfree(struct mbuf *);
149 static int wb_newbuf(struct wb_softc *, struct wb_chain_onefrag *,
151 static int wb_encap(struct wb_softc *, struct wb_chain *, struct mbuf *);
153 static void wb_rxeof(struct wb_softc *);
154 static void wb_rxeoc(struct wb_softc *);
155 static void wb_txeof(struct wb_softc *);
156 static void wb_txeoc(struct wb_softc *);
157 static void wb_intr(void *);
158 static void wb_tick(void *);
159 static void wb_start(struct ifnet *);
160 static void wb_start_locked(struct ifnet *);
161 static int wb_ioctl(struct ifnet *, u_long, caddr_t);
162 static void wb_init(void *);
163 static void wb_init_locked(struct wb_softc *);
164 static void wb_stop(struct wb_softc *);
165 static void wb_watchdog(struct wb_softc *);
166 static int wb_shutdown(device_t);
167 static int wb_ifmedia_upd(struct ifnet *);
168 static void wb_ifmedia_sts(struct ifnet *, struct ifmediareq *);
170 static void wb_eeprom_putbyte(struct wb_softc *, int);
171 static void wb_eeprom_getword(struct wb_softc *, int, u_int16_t *);
172 static void wb_read_eeprom(struct wb_softc *, caddr_t, int, int, int);
174 static void wb_setcfg(struct wb_softc *, u_int32_t);
175 static void wb_setmulti(struct wb_softc *);
176 static void wb_reset(struct wb_softc *);
177 static void wb_fixmedia(struct wb_softc *);
178 static int wb_list_rx_init(struct wb_softc *);
179 static int wb_list_tx_init(struct wb_softc *);
181 static int wb_miibus_readreg(device_t, int, int);
182 static int wb_miibus_writereg(device_t, int, int, int);
183 static void wb_miibus_statchg(device_t);
188 static uint32_t wb_mii_bitbang_read(device_t);
189 static void wb_mii_bitbang_write(device_t, uint32_t);
191 static const struct mii_bitbang_ops wb_mii_bitbang_ops = {
193 wb_mii_bitbang_write,
195 WB_SIO_MII_DATAOUT, /* MII_BIT_MDO */
196 WB_SIO_MII_DATAIN, /* MII_BIT_MDI */
197 WB_SIO_MII_CLK, /* MII_BIT_MDC */
198 WB_SIO_MII_DIR, /* MII_BIT_DIR_HOST_PHY */
199 0, /* MII_BIT_DIR_PHY_HOST */
204 #define WB_RES SYS_RES_IOPORT
205 #define WB_RID WB_PCI_LOIO
207 #define WB_RES SYS_RES_MEMORY
208 #define WB_RID WB_PCI_LOMEM
211 static device_method_t wb_methods[] = {
212 /* Device interface */
213 DEVMETHOD(device_probe, wb_probe),
214 DEVMETHOD(device_attach, wb_attach),
215 DEVMETHOD(device_detach, wb_detach),
216 DEVMETHOD(device_shutdown, wb_shutdown),
219 DEVMETHOD(miibus_readreg, wb_miibus_readreg),
220 DEVMETHOD(miibus_writereg, wb_miibus_writereg),
221 DEVMETHOD(miibus_statchg, wb_miibus_statchg),
226 static driver_t wb_driver = {
229 sizeof(struct wb_softc)
232 static devclass_t wb_devclass;
234 DRIVER_MODULE(wb, pci, wb_driver, wb_devclass, 0, 0);
235 DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0);
237 #define WB_SETBIT(sc, reg, x) \
238 CSR_WRITE_4(sc, reg, \
239 CSR_READ_4(sc, reg) | (x))
241 #define WB_CLRBIT(sc, reg, x) \
242 CSR_WRITE_4(sc, reg, \
243 CSR_READ_4(sc, reg) & ~(x))
246 CSR_WRITE_4(sc, WB_SIO, \
247 CSR_READ_4(sc, WB_SIO) | (x))
250 CSR_WRITE_4(sc, WB_SIO, \
251 CSR_READ_4(sc, WB_SIO) & ~(x))
254 * Send a read command and address to the EEPROM, check for ACK.
257 wb_eeprom_putbyte(sc, addr)
263 d = addr | WB_EECMD_READ;
266 * Feed in each bit and stobe the clock.
268 for (i = 0x400; i; i >>= 1) {
270 SIO_SET(WB_SIO_EE_DATAIN);
272 SIO_CLR(WB_SIO_EE_DATAIN);
275 SIO_SET(WB_SIO_EE_CLK);
277 SIO_CLR(WB_SIO_EE_CLK);
283 * Read a word of data stored in the EEPROM at address 'addr.'
286 wb_eeprom_getword(sc, addr, dest)
294 /* Enter EEPROM access mode. */
295 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
298 * Send address of word we want to read.
300 wb_eeprom_putbyte(sc, addr);
302 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
305 * Start reading bits from EEPROM.
307 for (i = 0x8000; i; i >>= 1) {
308 SIO_SET(WB_SIO_EE_CLK);
310 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT)
312 SIO_CLR(WB_SIO_EE_CLK);
316 /* Turn off EEPROM access mode. */
317 CSR_WRITE_4(sc, WB_SIO, 0);
323 * Read a sequence of words from the EEPROM.
326 wb_read_eeprom(sc, dest, off, cnt, swap)
334 u_int16_t word = 0, *ptr;
336 for (i = 0; i < cnt; i++) {
337 wb_eeprom_getword(sc, off + i, &word);
338 ptr = (u_int16_t *)(dest + (i * 2));
347 * Read the MII serial port for the MII bit-bang module.
350 wb_mii_bitbang_read(device_t dev)
355 sc = device_get_softc(dev);
357 val = CSR_READ_4(sc, WB_SIO);
358 CSR_BARRIER(sc, WB_SIO, 4,
359 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
365 * Write the MII serial port for the MII bit-bang module.
368 wb_mii_bitbang_write(device_t dev, uint32_t val)
372 sc = device_get_softc(dev);
374 CSR_WRITE_4(sc, WB_SIO, val);
375 CSR_BARRIER(sc, WB_SIO, 4,
376 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
380 wb_miibus_readreg(dev, phy, reg)
385 return (mii_bitbang_readreg(dev, &wb_mii_bitbang_ops, phy, reg));
389 wb_miibus_writereg(dev, phy, reg, data)
394 mii_bitbang_writereg(dev, &wb_mii_bitbang_ops, phy, reg, data);
400 wb_miibus_statchg(dev)
404 struct mii_data *mii;
406 sc = device_get_softc(dev);
407 mii = device_get_softc(sc->wb_miibus);
408 wb_setcfg(sc, mii->mii_media_active);
412 * Program the 64-bit multicast hash filter.
420 u_int32_t hashes[2] = { 0, 0 };
421 struct ifmultiaddr *ifma;
427 rxfilt = CSR_READ_4(sc, WB_NETCFG);
429 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
430 rxfilt |= WB_NETCFG_RX_MULTI;
431 CSR_WRITE_4(sc, WB_NETCFG, rxfilt);
432 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF);
433 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF);
437 /* first, zot all the existing hash bits */
438 CSR_WRITE_4(sc, WB_MAR0, 0);
439 CSR_WRITE_4(sc, WB_MAR1, 0);
441 /* now program new ones */
443 CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
444 if (ifma->ifma_addr->sa_family != AF_LINK)
446 h = ~ether_crc32_be(LLADDR((struct sockaddr_dl *)
447 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
449 hashes[0] |= (1 << h);
451 hashes[1] |= (1 << (h - 32));
454 if_maddr_runlock(ifp);
457 rxfilt |= WB_NETCFG_RX_MULTI;
459 rxfilt &= ~WB_NETCFG_RX_MULTI;
461 CSR_WRITE_4(sc, WB_MAR0, hashes[0]);
462 CSR_WRITE_4(sc, WB_MAR1, hashes[1]);
463 CSR_WRITE_4(sc, WB_NETCFG, rxfilt);
467 * The Winbond manual states that in order to fiddle with the
468 * 'full-duplex' and '100Mbps' bits in the netconfig register, we
469 * first have to put the transmit and/or receive logic in the idle state.
478 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) {
480 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON));
482 for (i = 0; i < WB_TIMEOUT; i++) {
484 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) &&
485 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE))
490 device_printf(sc->wb_dev,
491 "failed to force tx and rx to idle state\n");
494 if (IFM_SUBTYPE(media) == IFM_10_T)
495 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS);
497 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS);
499 if ((media & IFM_GMASK) == IFM_FDX)
500 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX);
502 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX);
505 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON);
513 struct mii_data *mii;
514 struct mii_softc *miisc;
516 CSR_WRITE_4(sc, WB_NETCFG, 0);
517 CSR_WRITE_4(sc, WB_BUSCTL, 0);
518 CSR_WRITE_4(sc, WB_TXADDR, 0);
519 CSR_WRITE_4(sc, WB_RXADDR, 0);
521 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET);
522 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET);
524 for (i = 0; i < WB_TIMEOUT; i++) {
526 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET))
530 device_printf(sc->wb_dev, "reset never completed!\n");
532 /* Wait a little while for the chip to get its brains in order. */
535 if (sc->wb_miibus == NULL)
538 mii = device_get_softc(sc->wb_miibus);
539 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
547 struct mii_data *mii = NULL;
551 mii = device_get_softc(sc->wb_miibus);
555 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) {
556 media = mii->mii_media_active & ~IFM_10_T;
558 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
559 media = mii->mii_media_active & ~IFM_100_TX;
564 ifmedia_set(&mii->mii_media, media);
568 * Probe for a Winbond chip. Check the PCI vendor and device
569 * IDs against our list and return a device name if we find a match.
575 const struct wb_type *t;
579 while(t->wb_name != NULL) {
580 if ((pci_get_vendor(dev) == t->wb_vid) &&
581 (pci_get_device(dev) == t->wb_did)) {
582 device_set_desc(dev, t->wb_name);
583 return (BUS_PROBE_DEFAULT);
592 * Attach the interface. Allocate softc structures, do ifmedia
593 * setup and ethernet/BPF attach.
599 u_char eaddr[ETHER_ADDR_LEN];
604 sc = device_get_softc(dev);
607 mtx_init(&sc->wb_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
609 callout_init_mtx(&sc->wb_stat_callout, &sc->wb_mtx, 0);
612 * Map control/status registers.
614 pci_enable_busmaster(dev);
617 sc->wb_res = bus_alloc_resource_any(dev, WB_RES, &rid, RF_ACTIVE);
619 if (sc->wb_res == NULL) {
620 device_printf(dev, "couldn't map ports/memory\n");
625 /* Allocate interrupt */
627 sc->wb_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
628 RF_SHAREABLE | RF_ACTIVE);
630 if (sc->wb_irq == NULL) {
631 device_printf(dev, "couldn't map interrupt\n");
636 /* Save the cache line size. */
637 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF;
639 /* Reset the adapter. */
643 * Get station address from the EEPROM.
645 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0);
647 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF,
648 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
650 if (sc->wb_ldata == NULL) {
651 device_printf(dev, "no memory for list buffers!\n");
656 bzero(sc->wb_ldata, sizeof(struct wb_list_data));
658 ifp = sc->wb_ifp = if_alloc(IFT_ETHER);
660 device_printf(dev, "can not if_alloc()\n");
665 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
666 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
667 ifp->if_ioctl = wb_ioctl;
668 ifp->if_start = wb_start;
669 ifp->if_init = wb_init;
670 ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1;
675 error = mii_attach(dev, &sc->wb_miibus, ifp, wb_ifmedia_upd,
676 wb_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
678 device_printf(dev, "attaching PHYs failed\n");
683 * Call MI attach routine.
685 ether_ifattach(ifp, eaddr);
687 /* Hook interrupt last to avoid having to lock softc */
688 error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET | INTR_MPSAFE,
689 NULL, wb_intr, sc, &sc->wb_intrhand);
692 device_printf(dev, "couldn't set up irq\n");
705 * Shutdown hardware and free up resources. This can be called any
706 * time after the mutex has been initialized. It is called in both
707 * the error case in attach and the normal detach case so it needs
708 * to be careful about only freeing resources that have actually been
718 sc = device_get_softc(dev);
719 KASSERT(mtx_initialized(&sc->wb_mtx), ("wb mutex not initialized"));
723 * Delete any miibus and phy devices attached to this interface.
724 * This should only be done if attach succeeded.
726 if (device_is_attached(dev)) {
731 callout_drain(&sc->wb_stat_callout);
734 device_delete_child(dev, sc->wb_miibus);
735 bus_generic_detach(dev);
738 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand);
740 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq);
742 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
748 contigfree(sc->wb_ldata, sizeof(struct wb_list_data) + 8,
752 mtx_destroy(&sc->wb_mtx);
758 * Initialize the transmit descriptors.
764 struct wb_chain_data *cd;
765 struct wb_list_data *ld;
771 for (i = 0; i < WB_TX_LIST_CNT; i++) {
772 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i];
773 if (i == (WB_TX_LIST_CNT - 1)) {
774 cd->wb_tx_chain[i].wb_nextdesc =
777 cd->wb_tx_chain[i].wb_nextdesc =
778 &cd->wb_tx_chain[i + 1];
782 cd->wb_tx_free = &cd->wb_tx_chain[0];
783 cd->wb_tx_tail = cd->wb_tx_head = NULL;
790 * Initialize the RX descriptors and allocate mbufs for them. Note that
791 * we arrange the descriptors in a closed ring, so that the last descriptor
792 * points back to the first.
798 struct wb_chain_data *cd;
799 struct wb_list_data *ld;
805 for (i = 0; i < WB_RX_LIST_CNT; i++) {
806 cd->wb_rx_chain[i].wb_ptr =
807 (struct wb_desc *)&ld->wb_rx_list[i];
808 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i];
809 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS)
811 if (i == (WB_RX_LIST_CNT - 1)) {
812 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0];
813 ld->wb_rx_list[i].wb_next =
814 vtophys(&ld->wb_rx_list[0]);
816 cd->wb_rx_chain[i].wb_nextdesc =
817 &cd->wb_rx_chain[i + 1];
818 ld->wb_rx_list[i].wb_next =
819 vtophys(&ld->wb_rx_list[i + 1]);
823 cd->wb_rx_head = &cd->wb_rx_chain[0];
829 wb_bfree(struct mbuf *m)
834 * Initialize an RX descriptor and attach an MBUF cluster.
839 struct wb_chain_onefrag *c;
842 struct mbuf *m_new = NULL;
845 MGETHDR(m_new, M_NOWAIT, MT_DATA);
848 m_new->m_pkthdr.len = m_new->m_len = WB_BUFBYTES;
849 m_extadd(m_new, c->wb_buf, WB_BUFBYTES, wb_bfree, NULL, NULL,
853 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES;
854 m_new->m_data = m_new->m_ext.ext_buf;
857 m_adj(m_new, sizeof(u_int64_t));
860 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t));
861 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536;
862 c->wb_ptr->wb_status = WB_RXSTAT;
868 * A frame has been uploaded: pass the resulting mbuf chain up to
869 * the higher level protocols.
875 struct mbuf *m = NULL;
877 struct wb_chain_onefrag *cur_rx;
885 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) &
887 struct mbuf *m0 = NULL;
889 cur_rx = sc->wb_cdata.wb_rx_head;
890 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc;
894 if ((rxstat & WB_RXSTAT_MIIERR) ||
895 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) ||
896 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) ||
897 !(rxstat & WB_RXSTAT_LASTFRAG) ||
898 !(rxstat & WB_RXSTAT_RXCMP)) {
899 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
900 wb_newbuf(sc, cur_rx, m);
901 device_printf(sc->wb_dev,
902 "receiver babbling: possible chip bug,"
910 if (rxstat & WB_RXSTAT_RXERR) {
911 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
912 wb_newbuf(sc, cur_rx, m);
916 /* No errors; receive the packet. */
917 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status);
920 * XXX The Winbond chip includes the CRC with every
921 * received frame, and there's no way to turn this
922 * behavior off (at least, I can't find anything in
923 * the manual that explains how to do it) so we have
924 * to trim off the CRC manually.
926 total_len -= ETHER_CRC_LEN;
928 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp,
930 wb_newbuf(sc, cur_rx, m);
932 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
937 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
939 (*ifp->if_input)(ifp, m);
950 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
951 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0]));
952 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
953 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND)
954 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF);
958 * A frame was downloaded to the chip. It's safe for us to clean up
965 struct wb_chain *cur_tx;
970 /* Clear the timeout timer. */
973 if (sc->wb_cdata.wb_tx_head == NULL)
977 * Go through our tx list and free mbufs for those
978 * frames that have been transmitted.
980 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) {
983 cur_tx = sc->wb_cdata.wb_tx_head;
984 txstat = WB_TXSTATUS(cur_tx);
986 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT)
989 if (txstat & WB_TXSTAT_TXERR) {
990 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
991 if (txstat & WB_TXSTAT_ABORT)
992 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
993 if (txstat & WB_TXSTAT_LATECOLL)
994 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
997 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, (txstat & WB_TXSTAT_COLLCNT) >> 3);
999 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
1000 m_freem(cur_tx->wb_mbuf);
1001 cur_tx->wb_mbuf = NULL;
1003 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) {
1004 sc->wb_cdata.wb_tx_head = NULL;
1005 sc->wb_cdata.wb_tx_tail = NULL;
1009 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc;
1014 * TX 'end of channel' interrupt handler.
1018 struct wb_softc *sc;
1026 if (sc->wb_cdata.wb_tx_head == NULL) {
1027 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1028 sc->wb_cdata.wb_tx_tail = NULL;
1030 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) {
1031 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN;
1033 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1042 struct wb_softc *sc;
1050 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
1055 /* Disable interrupts. */
1056 CSR_WRITE_4(sc, WB_IMR, 0x00000000);
1060 status = CSR_READ_4(sc, WB_ISR);
1062 CSR_WRITE_4(sc, WB_ISR, status);
1064 if ((status & WB_INTRS) == 0)
1067 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) {
1068 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1070 if (status & WB_ISR_RX_ERR)
1076 if (status & WB_ISR_RX_OK)
1079 if (status & WB_ISR_RX_IDLE)
1082 if (status & WB_ISR_TX_OK)
1085 if (status & WB_ISR_TX_NOBUF)
1088 if (status & WB_ISR_TX_IDLE) {
1090 if (sc->wb_cdata.wb_tx_head != NULL) {
1091 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1092 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1096 if (status & WB_ISR_TX_UNDERRUN) {
1097 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1099 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1100 /* Jack up TX threshold */
1101 sc->wb_txthresh += WB_TXTHRESH_CHUNK;
1102 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH);
1103 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh));
1104 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1107 if (status & WB_ISR_BUS_ERR) {
1114 /* Re-enable interrupts. */
1115 CSR_WRITE_4(sc, WB_IMR, WB_INTRS);
1117 if (ifp->if_snd.ifq_head != NULL) {
1118 wb_start_locked(ifp);
1128 struct wb_softc *sc;
1129 struct mii_data *mii;
1133 mii = device_get_softc(sc->wb_miibus);
1137 if (sc->wb_timer > 0 && --sc->wb_timer == 0)
1139 callout_reset(&sc->wb_stat_callout, hz, wb_tick, sc);
1143 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1144 * pointers to the fragment pointers.
1147 wb_encap(sc, c, m_head)
1148 struct wb_softc *sc;
1150 struct mbuf *m_head;
1153 struct wb_desc *f = NULL;
1158 * Start packing the mbufs in this chain into
1159 * the fragment pointers. Stop when we run out
1160 * of fragments or hit the end of the mbuf chain.
1165 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1166 if (m->m_len != 0) {
1167 if (frag == WB_MAXFRAGS)
1169 total_len += m->m_len;
1170 f = &c->wb_ptr->wb_frag[frag];
1171 f->wb_ctl = WB_TXCTL_TLINK | m->m_len;
1173 f->wb_ctl |= WB_TXCTL_FIRSTFRAG;
1176 f->wb_status = WB_TXSTAT_OWN;
1177 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]);
1178 f->wb_data = vtophys(mtod(m, vm_offset_t));
1184 * Handle special case: we used up all 16 fragments,
1185 * but we have more mbufs left in the chain. Copy the
1186 * data into an mbuf cluster. Note that we don't
1187 * bother clearing the values in the other fragment
1188 * pointers/counters; it wouldn't gain us anything,
1189 * and would waste cycles.
1192 struct mbuf *m_new = NULL;
1194 MGETHDR(m_new, M_NOWAIT, MT_DATA);
1197 if (m_head->m_pkthdr.len > MHLEN) {
1198 if (!(MCLGET(m_new, M_NOWAIT))) {
1203 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1204 mtod(m_new, caddr_t));
1205 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1208 f = &c->wb_ptr->wb_frag[0];
1210 f->wb_data = vtophys(mtod(m_new, caddr_t));
1211 f->wb_ctl = total_len = m_new->m_len;
1212 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG;
1216 if (total_len < WB_MIN_FRAMELEN) {
1217 f = &c->wb_ptr->wb_frag[frag];
1218 f->wb_ctl = WB_MIN_FRAMELEN - total_len;
1219 f->wb_data = vtophys(&sc->wb_cdata.wb_pad);
1220 f->wb_ctl |= WB_TXCTL_TLINK;
1221 f->wb_status = WB_TXSTAT_OWN;
1225 c->wb_mbuf = m_head;
1226 c->wb_lastdesc = frag - 1;
1227 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG;
1228 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]);
1234 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1235 * to the mbuf data regions directly in the transmit lists. We also save a
1236 * copy of the pointers since the transmit list fragment pointers are
1237 * physical addresses.
1244 struct wb_softc *sc;
1248 wb_start_locked(ifp);
1253 wb_start_locked(ifp)
1256 struct wb_softc *sc;
1257 struct mbuf *m_head = NULL;
1258 struct wb_chain *cur_tx = NULL, *start_tx;
1264 * Check for an available queue slot. If there are none,
1267 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) {
1268 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1272 start_tx = sc->wb_cdata.wb_tx_free;
1274 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) {
1275 IF_DEQUEUE(&ifp->if_snd, m_head);
1279 /* Pick a descriptor off the free list. */
1280 cur_tx = sc->wb_cdata.wb_tx_free;
1281 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc;
1283 /* Pack the data into the descriptor. */
1284 wb_encap(sc, cur_tx, m_head);
1286 if (cur_tx != start_tx)
1287 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN;
1290 * If there's a BPF listener, bounce a copy of this frame
1293 BPF_MTAP(ifp, cur_tx->wb_mbuf);
1297 * If there are no packets queued, bail.
1303 * Place the request for the upload interrupt
1304 * in the last descriptor in the chain. This way, if
1305 * we're chaining several packets at once, we'll only
1306 * get an interrupt once for the whole chain rather than
1307 * once for each packet.
1309 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT;
1310 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT;
1311 sc->wb_cdata.wb_tx_tail = cur_tx;
1313 if (sc->wb_cdata.wb_tx_head == NULL) {
1314 sc->wb_cdata.wb_tx_head = start_tx;
1315 WB_TXOWN(start_tx) = WB_TXSTAT_OWN;
1316 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1319 * We need to distinguish between the case where
1320 * the own bit is clear because the chip cleared it
1321 * and where the own bit is clear because we haven't
1322 * set it yet. The magic value WB_UNSET is just some
1323 * ramdomly chosen number which doesn't have the own
1324 * bit set. When we actually transmit the frame, the
1325 * status word will have _only_ the own bit set, so
1326 * the txeoc handler will be able to tell if it needs
1327 * to initiate another transmission to flush out pending
1330 WB_TXOWN(start_tx) = WB_UNSENT;
1334 * Set a timeout in case the chip goes out to lunch.
1343 struct wb_softc *sc = xsc;
1352 struct wb_softc *sc;
1354 struct ifnet *ifp = sc->wb_ifp;
1356 struct mii_data *mii;
1359 mii = device_get_softc(sc->wb_miibus);
1362 * Cancel pending I/O and free all RX/TX buffers.
1367 sc->wb_txthresh = WB_TXTHRESH_INIT;
1370 * Set cache alignment and burst length.
1373 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG);
1374 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH);
1375 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh));
1378 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION);
1379 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG);
1380 switch(sc->wb_cachesize) {
1382 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG);
1385 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG);
1388 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG);
1392 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE);
1396 /* This doesn't tend to work too well at 100Mbps. */
1397 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON);
1399 /* Init our MAC address */
1400 for (i = 0; i < ETHER_ADDR_LEN; i++) {
1401 CSR_WRITE_1(sc, WB_NODE0 + i, IF_LLADDR(sc->wb_ifp)[i]);
1404 /* Init circular RX list. */
1405 if (wb_list_rx_init(sc) == ENOBUFS) {
1406 device_printf(sc->wb_dev,
1407 "initialization failed: no memory for rx buffers\n");
1412 /* Init TX descriptors. */
1413 wb_list_tx_init(sc);
1415 /* If we want promiscuous mode, set the allframes bit. */
1416 if (ifp->if_flags & IFF_PROMISC) {
1417 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);
1419 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);
1423 * Set capture broadcast bit to capture broadcast frames.
1425 if (ifp->if_flags & IFF_BROADCAST) {
1426 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);
1428 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);
1432 * Program the multicast filter, if necessary.
1437 * Load the address of the RX list.
1439 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1440 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0]));
1443 * Enable interrupts.
1445 CSR_WRITE_4(sc, WB_IMR, WB_INTRS);
1446 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF);
1448 /* Enable receiver and transmitter. */
1449 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1450 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF);
1452 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1453 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0]));
1454 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1458 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1459 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1461 callout_reset(&sc->wb_stat_callout, hz, wb_tick, sc);
1465 * Set media options.
1471 struct wb_softc *sc;
1476 if (ifp->if_flags & IFF_UP)
1484 * Report current media status.
1487 wb_ifmedia_sts(ifp, ifmr)
1489 struct ifmediareq *ifmr;
1491 struct wb_softc *sc;
1492 struct mii_data *mii;
1497 mii = device_get_softc(sc->wb_miibus);
1500 ifmr->ifm_active = mii->mii_media_active;
1501 ifmr->ifm_status = mii->mii_media_status;
1506 wb_ioctl(ifp, command, data)
1511 struct wb_softc *sc = ifp->if_softc;
1512 struct mii_data *mii;
1513 struct ifreq *ifr = (struct ifreq *) data;
1519 if (ifp->if_flags & IFF_UP) {
1522 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1537 mii = device_get_softc(sc->wb_miibus);
1538 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1541 error = ether_ioctl(ifp, command, data);
1550 struct wb_softc *sc;
1556 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1557 if_printf(ifp, "watchdog timeout\n");
1559 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT))
1560 if_printf(ifp, "no carrier - transceiver cable problem?\n");
1566 if (ifp->if_snd.ifq_head != NULL)
1567 wb_start_locked(ifp);
1571 * Stop the adapter and free any mbufs allocated to the
1576 struct wb_softc *sc;
1585 callout_stop(&sc->wb_stat_callout);
1587 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON));
1588 CSR_WRITE_4(sc, WB_IMR, 0x00000000);
1589 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000);
1590 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000);
1593 * Free data in the RX lists.
1595 for (i = 0; i < WB_RX_LIST_CNT; i++) {
1596 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) {
1597 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf);
1598 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL;
1601 bzero((char *)&sc->wb_ldata->wb_rx_list,
1602 sizeof(sc->wb_ldata->wb_rx_list));
1605 * Free the TX list buffers.
1607 for (i = 0; i < WB_TX_LIST_CNT; i++) {
1608 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) {
1609 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf);
1610 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL;
1614 bzero((char *)&sc->wb_ldata->wb_tx_list,
1615 sizeof(sc->wb_ldata->wb_tx_list));
1617 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1621 * Stop all chip I/O so that the kernel's probe routines don't
1622 * get confused by errant DMAs when rebooting.
1628 struct wb_softc *sc;
1630 sc = device_get_softc(dev);