2 * Copyright (c) 2011 Sandvine Incorporated ULC.
3 * Copyright (c) 2012 iXsystems, Inc.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * Support for Winbond watchdog.
30 * With minor abstractions it might be possible to add support for other
31 * different Winbond Super I/O chips as well. Winbond seems to have four
32 * different types of chips, four different ways to get into extended config
35 * Note: there is no serialization between the debugging sysctl handlers and
36 * the watchdog functions and possibly others poking the registers at the same
37 * time. For that at least possibly interfering sysctls are hidden by default.
40 #include <sys/cdefs.h>
41 __FBSDID("$FreeBSD$");
43 #include <sys/param.h>
44 #include <sys/kernel.h>
45 #include <sys/systm.h>
47 #include <sys/eventhandler.h>
49 #include <sys/module.h>
52 #include <sys/sysctl.h>
53 #include <sys/watchdog.h>
55 #include <isa/isavar.h>
57 #include <machine/bus.h>
58 #include <machine/resource.h>
63 #define WB_DEVICE_ID_REG 0x20 /* Device ID */
64 #define WB_DEVICE_REV_REG 0x21 /* Device revision */
65 #define WB_CR26 0x26 /* Bit6: HEFRAS (base port selector) */
68 #define WB_LDN_REG 0x07
69 #define WB_LDN_REG_LDN8 0x08 /* GPIO 2, Watchdog */
72 * LDN8 (GPIO 2, Watchdog) specific registers and options.
74 /* CR30: LDN8 activation control. */
75 #define WB_LDN8_CR30 0x30
76 #define WB_LDN8_CR30_ACTIVE 0x01 /* 1: LD active */
78 /* CRF5: Watchdog scale, P20. Mapped to reg_1. */
79 #define WB_LDN8_CRF5 0xF5
80 #define WB_LDN8_CRF5_SCALE 0x08 /* 0: 1s, 1: 60s */
81 #define WB_LDN8_CRF5_KEYB_P20 0x04 /* 1: keyb P20 forces timeout */
82 #define WB_LDN8_CRF5_KBRST 0x02 /* 1: timeout causes pin60 kbd reset */
84 /* CRF6: Watchdog Timeout (0 == off). Mapped to reg_timeout. */
85 #define WB_LDN8_CRF6 0xF6
87 /* CRF7: Watchdog mouse, keyb, force, .. Mapped to reg_2. */
88 #define WB_LDN8_CRF7 0xF7
89 #define WB_LDN8_CRF7_MOUSE 0x80 /* 1: mouse irq resets wd timer */
90 #define WB_LDN8_CRF7_KEYB 0x40 /* 1: keyb irq resets wd timer */
91 #define WB_LDN8_CRF7_FORCE 0x20 /* 1: force timeout (self-clear) */
92 #define WB_LDN8_CRF7_TS 0x10 /* 0: counting, 1: fired */
93 #define WB_LDN8_CRF7_IRQS 0x0f /* irq source for watchdog, 2 == SMI */
95 enum chips { w83627hf, w83627s, w83697hf, w83697ug, w83637hf, w83627thf,
96 w83687thf, w83627ehf, w83627dhg, w83627uhg, w83667hg,
97 w83627dhg_p, w83667hg_b, nct6775, nct6776, nct6779, nct6791,
102 struct resource *portres;
104 bus_space_handle_t bsh;
106 eventhandler_tag ev_tag;
107 int (*ext_cfg_enter_f)(struct wb_softc *, u_short);
108 void (*ext_cfg_exit_f)(struct wb_softc *, u_short);
116 * Special feature to let the watchdog fire at a different
117 * timeout as set by watchdog(4) but still use that API to
118 * re-load it periodically.
120 unsigned int timeout_override;
123 * Space to save current state temporary and for sysctls.
124 * We want to know the timeout value and usually need two
125 * additional registers for options. Do not name them by
126 * register as these might be different by chip.
133 static int ext_cfg_enter_0x87_0x87(struct wb_softc *, u_short);
134 static void ext_cfg_exit_0xaa(struct wb_softc *, u_short);
136 struct winbond_superio_cfg {
137 uint8_t efer; /* and efir */
138 int (*ext_cfg_enter_f)(struct wb_softc *, u_short);
139 void (*ext_cfg_exit_f)(struct wb_softc *, u_short);
143 .ext_cfg_enter_f = ext_cfg_enter_0x87_0x87,
144 .ext_cfg_exit_f = ext_cfg_exit_0xaa,
148 .ext_cfg_enter_f = ext_cfg_enter_0x87_0x87,
149 .ext_cfg_exit_f = ext_cfg_exit_0xaa,
153 struct winbond_vendor_device_id {
161 .descr = "Winbond 83627HF/F/HG/G",
166 .descr = "Winbond 83627S",
171 .descr = "Winbond 83697HF",
176 .descr = "Winbond 83697UG",
181 .descr = "Winbond 83637HF",
186 .descr = "Winbond 83627THF",
191 .descr = "Winbond 83687THF",
196 .descr = "Winbond 83627EHF",
201 .descr = "Winbond 83627DHG",
206 .descr = "Winbond 83627UHG",
211 .descr = "Winbond 83667HG",
216 .descr = "Winbond 83627DHG-P",
221 .descr = "Winbond 83667HG-B",
226 .descr = "Nuvoton NCT6775",
231 .descr = "Nuvoton NCT6776",
236 .descr = "Nuvoton NCT6102",
241 .descr = "Nuvoton NCT6779",
246 .descr = "Nuvoton NCT6791",
251 .descr = "Nuvoton NCT6792",
256 write_efir_1(struct wb_softc *sc, u_short baseport, uint8_t value)
259 MPASS(sc != NULL || baseport != 0);
261 bus_space_write_1((sc)->bst, (sc)->bsh, 0, (value));
263 outb(baseport, value);
266 static uint8_t __unused
267 read_efir_1(struct wb_softc *sc, u_short baseport)
270 MPASS(sc != NULL || baseport != 0);
272 return (bus_space_read_1((sc)->bst, (sc)->bsh, 0));
274 return (inb(baseport));
278 write_efdr_1(struct wb_softc *sc, u_short baseport, uint8_t value)
281 MPASS(sc != NULL || baseport != 0);
283 bus_space_write_1((sc)->bst, (sc)->bsh, 1, (value));
285 outb(baseport + 1, value);
289 read_efdr_1(struct wb_softc *sc, u_short baseport)
292 MPASS(sc != NULL || baseport != 0);
294 return (bus_space_read_1((sc)->bst, (sc)->bsh, 1));
296 return (inb(baseport + 1));
300 write_reg(struct wb_softc *sc, uint8_t reg, uint8_t value)
303 write_efir_1(sc, 0, reg);
304 write_efdr_1(sc, 0, value);
308 read_reg(struct wb_softc *sc, uint8_t reg)
311 write_efir_1(sc, 0, reg);
312 return (read_efdr_1(sc, 0));
316 * Return the watchdog related registers as we last read them. This will
317 * usually not give the current timeout or state on whether the watchdog
321 sysctl_wb_debug(SYSCTL_HANDLER_ARGS)
329 sbuf_new_for_sysctl(&sb, NULL, 64, req);
331 sbuf_printf(&sb, "LDN8 (GPIO2, Watchdog): ");
332 sbuf_printf(&sb, "CR%02X 0x%02x ", sc->ctl_reg, sc->reg_1);
333 sbuf_printf(&sb, "CR%02X 0x%02x ", sc->time_reg, sc->reg_timeout);
334 sbuf_printf(&sb, "CR%02X 0x%02x", sc->csr_reg, sc->reg_2);
336 error = sbuf_finish(&sb);
342 * Read the current values before returning them. Given this might poke
343 * the registers the same time as the watchdog, this sysctl handler should
344 * be marked CTLFLAG_SKIP to not show up by default.
347 sysctl_wb_debug_current(SYSCTL_HANDLER_ARGS)
353 if ((*sc->ext_cfg_enter_f)(sc, 0) != 0)
356 /* Watchdog is configured as part of LDN 8 (GPIO Port2, Watchdog). */
357 write_reg(sc, WB_LDN_REG, WB_LDN_REG_LDN8);
359 sc->reg_1 = read_reg(sc, sc->ctl_reg);
360 sc->reg_timeout = read_reg(sc, sc->time_reg);
361 sc->reg_2 = read_reg(sc, sc->csr_reg);
363 (*sc->ext_cfg_exit_f)(sc, 0);
365 return (sysctl_wb_debug(oidp, arg1, arg2, req));
369 * Sysctl handlers to force a watchdog timeout or to test the NMI functionality
371 * For testing we could set a test_nmi flag in the softc that, in case of NMI, a
372 * callback function from trap.c could check whether we fired and not report the
373 * timeout but clear the flag for the sysctl again. This is interesting given a
374 * lot of boards have jumpers to change the action on watchdog timeout or
375 * disable the watchdog completely.
376 * XXX-BZ notyet: currently no general infrastructure exists to do this.
379 sysctl_wb_force_test_nmi(SYSCTL_HANDLER_ARGS)
382 int error, test, val;
392 error = sysctl_handle_int(oidp, &val, 0, req);
393 if (error || !req->newptr)
397 /* Manually clear the test for a value of 0 and do nothing else. */
398 if (test && val == 0) {
404 if ((*sc->ext_cfg_enter_f)(sc, 0) != 0)
409 * If we are testing the NMI functionality, set the flag before
410 * forcing the timeout.
416 /* Watchdog is configured as part of LDN 8 (GPIO Port2, Watchdog). */
417 write_reg(sc, WB_LDN_REG, WB_LDN_REG_LDN8);
419 /* Force watchdog to fire. */
420 sc->reg_2 = read_reg(sc, sc->csr_reg);
421 sc->reg_2 |= WB_LDN8_CRF7_FORCE;
422 write_reg(sc, sc->csr_reg, sc->reg_2);
424 (*sc->ext_cfg_exit_f)(sc, 0);
430 * Print current watchdog state.
432 * Note: it is the responsibility of the caller to update the registers
436 wb_print_state(struct wb_softc *sc, const char *msg)
439 device_printf(sc->dev, "%s%sWatchdog %sabled. %s"
440 "Scaling by %ds, timer at %d (%s=%ds%s). "
441 "CRF5 0x%02x CRF7 0x%02x\n",
442 (msg != NULL) ? msg : "", (msg != NULL) ? ": " : "",
443 (sc->reg_timeout > 0x00) ? "en" : "dis",
444 (sc->reg_2 & WB_LDN8_CRF7_TS) ? "Watchdog fired. " : "",
445 (sc->reg_1 & WB_LDN8_CRF5_SCALE) ? 60 : 1,
447 (sc->reg_timeout > 0x00) ? "<" : "",
448 sc->reg_timeout * ((sc->reg_1 & WB_LDN8_CRF5_SCALE) ? 60 : 1),
449 (sc->reg_timeout > 0x00) ? " left" : "",
450 sc->reg_1, sc->reg_2);
454 * Functions to enter and exit extended function mode. Possibly shared
455 * between different chips.
458 ext_cfg_enter_0x87_0x87(struct wb_softc *sc, u_short baseport)
462 * Enable extended function mode.
463 * Winbond does not allow us to validate so always return success.
465 write_efir_1(sc, baseport, 0x87);
466 write_efir_1(sc, baseport, 0x87);
472 ext_cfg_exit_0xaa(struct wb_softc *sc, u_short baseport)
475 write_efir_1(sc, baseport, 0xaa);
479 * (Re)load the watchdog counter depending on timeout. A timeout of 0 will
480 * disable the watchdog.
483 wb_set_watchdog(struct wb_softc *sc, unsigned int timeout)
488 * In case an override is set, let it override. It may lead
489 * to strange results as we do not check the input of the sysctl.
491 if (sc->timeout_override > 0)
492 timeout = sc->timeout_override;
494 /* Make sure we support the requested timeout. */
495 if (timeout > 255 * 60)
499 if (sc->debug_verbose)
500 wb_print_state(sc, "Before watchdog counter (re)load");
502 if ((*sc->ext_cfg_enter_f)(sc, 0) != 0)
505 /* Watchdog is configured as part of LDN 8 (GPIO Port2, Watchdog) */
506 write_reg(sc, WB_LDN_REG, WB_LDN_REG_LDN8);
509 /* Disable watchdog. */
511 write_reg(sc, sc->time_reg, sc->reg_timeout);
514 /* Read current scaling factor. */
515 sc->reg_1 = read_reg(sc, sc->ctl_reg);
518 /* Set scaling factor to 60s. */
519 sc->reg_1 |= WB_LDN8_CRF5_SCALE;
520 sc->reg_timeout = (timeout / 60);
524 /* Set scaling factor to 1s. */
525 sc->reg_1 &= ~WB_LDN8_CRF5_SCALE;
526 sc->reg_timeout = timeout;
529 /* In case we fired before we need to clear to fire again. */
530 sc->reg_2 = read_reg(sc, sc->csr_reg);
531 if (sc->reg_2 & WB_LDN8_CRF7_TS) {
532 sc->reg_2 &= ~WB_LDN8_CRF7_TS;
533 write_reg(sc, sc->csr_reg, sc->reg_2);
536 /* Write back scaling factor. */
537 write_reg(sc, sc->ctl_reg, sc->reg_1);
539 /* Set timer and arm/reset the watchdog. */
540 write_reg(sc, sc->time_reg, sc->reg_timeout);
543 (*sc->ext_cfg_exit_f)(sc, 0);
545 if (sc->debug_verbose)
546 wb_print_state(sc, "After watchdog counter (re)load");
551 * watchdog(9) EVENTHANDLER function implementation to (re)load the counter
552 * with the given timeout or disable the watchdog.
555 wb_watchdog_fn(void *private, u_int cmd, int *error)
558 unsigned int timeout;
562 KASSERT(sc != NULL, ("%s: watchdog handler function called without "
563 "softc.", __func__));
566 if (cmd > 0 && cmd <= 63) {
567 /* Reset (and arm) watchdog. */
568 timeout = ((uint64_t)1 << cmd) / 1000000000;
571 e = wb_set_watchdog(sc, timeout);
576 /* On error, try to make sure the WD is disabled. */
577 wb_set_watchdog(sc, 0);
581 /* Disable watchdog. */
582 e = wb_set_watchdog(sc, 0);
583 if (e != 0 && cmd == 0 && error != NULL) {
584 /* Failed to disable watchdog. */
591 * Probe/attach the Winbond Super I/O chip.
593 * Initial abstraction to possibly support more chips:
594 * - Iterate over the well known base ports, try to enable extended function
595 * mode and read and match the device ID and device revision. Unfortunately
596 * the Vendor ID is in the hardware monitoring section accessible by different
598 * - Also HEFRAS, which would tell use the base port, is only accessible after
599 * entering extended function mode, for which the base port is needed.
600 * At least check HEFRAS to match the current base port we are probing.
601 * - On match set the description, remember functions to enter/exit extended
602 * function mode as well as the base port.
605 wb_probe_enable(device_t dev, int probe)
608 int error, found, i, j;
609 uint8_t dev_id, dev_rev, cr26;
615 sc = device_get_softc(dev);
616 bzero(sc, sizeof(*sc));
622 for (i = 0; i < nitems(probe_addrs); i++) {
625 /* Allocate bus resources for IO index/data register access. */
626 sc->portres = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->rid,
627 probe_addrs[i].efer, probe_addrs[i].efer + 1, 2, RF_ACTIVE);
628 if (sc->portres == NULL)
630 sc->bst = rman_get_bustag(sc->portres);
631 sc->bsh = rman_get_bushandle(sc->portres);
634 error = (*probe_addrs[i].ext_cfg_enter_f)(sc, probe_addrs[i].efer);
638 /* Identify the SuperIO chip. */
639 write_efir_1(sc, probe_addrs[i].efer, WB_DEVICE_ID_REG);
640 dev_id = read_efdr_1(sc, probe_addrs[i].efer);
641 write_efir_1(sc, probe_addrs[i].efer, WB_DEVICE_REV_REG);
642 dev_rev = read_efdr_1(sc, probe_addrs[i].efer);
643 write_efir_1(sc, probe_addrs[i].efer, WB_CR26);
644 cr26 = read_efdr_1(sc, probe_addrs[i].efer);
646 if (dev_id == 0xff && dev_rev == 0xff)
649 /* HEFRAS of 0 means EFER at 0x2e, 1 means EFER at 0x4e. */
650 if (((cr26 & 0x40) == 0x00 && probe_addrs[i].efer != 0x2e) ||
651 ((cr26 & 0x40) == 0x40 && probe_addrs[i].efer != 0x4e)) {
653 device_printf(dev, "HEFRAS and EFER do not "
654 "align: EFER 0x%02x DevID 0x%02x DevRev "
655 "0x%02x CR26 0x%02x\n",
656 probe_addrs[i].efer, dev_id, dev_rev, cr26);
660 for (j = 0; j < nitems(wb_devs); j++) {
661 if (wb_devs[j].device_id == dev_id) {
667 if (probe && dev != NULL) {
668 snprintf(buf, sizeof(buf),
669 "%s (0x%02x/0x%02x) Watchdog Timer",
670 found ? wb_devs[j].descr :
671 "Unknown Winbond/Nuvoton", dev_id, dev_rev);
672 device_set_desc_copy(dev, buf);
675 /* If this is hinted attach, try to guess the model. */
676 if (dev != NULL && !found) {
682 if (probe || !found) {
683 (*probe_addrs[i].ext_cfg_exit_f)(sc, probe_addrs[i].efer);
685 (void) bus_release_resource(dev, SYS_RES_IOPORT,
686 sc->rid, sc->portres);
690 * Stop probing if have successfully identified the SuperIO.
691 * Remember the extended function mode enter/exit functions
696 sc->ext_cfg_enter_f = probe_addrs[i].ext_cfg_enter_f;
697 sc->ext_cfg_exit_f = probe_addrs[i].ext_cfg_exit_f;
698 sc->chip = wb_devs[j].chip;
702 if (sc->chip == w83697hf ||
703 sc->chip == w83697ug) {
706 } else if (sc->chip == nct6102) {
712 return (BUS_PROBE_SPECIFIC);
721 wb_identify(driver_t *driver, device_t parent)
724 if (device_find_child(parent, driver->name, 0) == NULL) {
725 if (wb_probe_enable(NULL, 1) <= 0)
726 BUS_ADD_CHILD(parent, 0, driver->name, 0);
731 wb_probe(device_t dev)
734 /* Make sure we do not claim some ISA PNP device. */
735 if (isa_get_logicalid(dev) != 0)
738 return (wb_probe_enable(dev, 1));
742 wb_attach(device_t dev)
745 struct sysctl_ctx_list *sctx;
746 struct sysctl_oid *soid;
747 unsigned long timeout;
751 error = wb_probe_enable(dev, 0);
755 sc = device_get_softc(dev);
756 KASSERT(sc->ext_cfg_enter_f != NULL && sc->ext_cfg_exit_f != NULL,
757 ("%s: successful probe result but not setup correctly", __func__));
759 /* Watchdog is configured as part of LDN 8 (GPIO Port2, Watchdog). */
760 write_reg(sc, WB_LDN_REG, WB_LDN_REG_LDN8);
762 /* Make sure WDT is enabled. */
763 write_reg(sc, WB_LDN8_CR30,
764 read_reg(sc, WB_LDN8_CR30) | WB_LDN8_CR30_ACTIVE);
769 t = read_reg(sc, 0x2B) & ~0x10;
770 write_reg(sc, 0x2B, t); /* set GPIO24 to WDT0 */
773 /* Set pin 119 to WDTO# mode (= CR29, WDT0) */
774 t = read_reg(sc, 0x29) & ~0x60;
776 write_reg(sc, 0x29, t);
779 /* Set pin 118 to WDTO# mode */
780 t = read_reg(sc, 0x2b) & ~0x04;
781 write_reg(sc, 0x2b, t);
784 t = (read_reg(sc, 0x2B) & ~0x08) | 0x04;
785 write_reg(sc, 0x2B, t); /* set GPIO3 to WDT0 */
789 t = read_reg(sc, 0x2D) & ~0x01; /* PIN77 -> WDT0# */
790 write_reg(sc, 0x2D, t); /* set GPIO5 to WDT0 */
791 t = read_reg(sc, sc->ctl_reg);
792 t |= 0x02; /* enable the WDTO# output low pulse
793 * to the KBRST# pin */
794 write_reg(sc, sc->ctl_reg, t);
799 t = read_reg(sc, 0x2C) & ~0x80; /* PIN47 -> WDT0# */
800 write_reg(sc, 0x2C, t);
813 * These chips have a fixed WDTO# output pin (W83627UHG),
814 * or support more than one WDTO# output pin.
815 * Don't touch its configuration, and hope the BIOS
816 * does the right thing.
818 t = read_reg(sc, sc->ctl_reg);
819 t |= 0x02; /* enable the WDTO# output low pulse
820 * to the KBRST# pin */
821 write_reg(sc, sc->ctl_reg, t);
827 /* Read the current watchdog configuration. */
828 sc->reg_1 = read_reg(sc, sc->ctl_reg);
829 sc->reg_timeout = read_reg(sc, sc->time_reg);
830 sc->reg_2 = read_reg(sc, sc->csr_reg);
832 /* Print current state if bootverbose or watchdog already enabled. */
833 if (bootverbose || (sc->reg_timeout > 0x00))
834 wb_print_state(sc, "Before watchdog attach");
836 sc->reg_1 &= ~WB_LDN8_CRF5_KEYB_P20;
837 sc->reg_1 |= WB_LDN8_CRF5_KBRST;
838 write_reg(sc, sc->ctl_reg, sc->reg_1);
841 * Clear a previous watchdog timeout event (if still set).
842 * Disable timer reset on mouse interrupts. Leave reset on keyboard,
843 * since one of my boards is getting stuck in reboot without it.
845 sc->reg_2 &= ~(WB_LDN8_CRF7_MOUSE|WB_LDN8_CRF7_TS);
846 write_reg(sc, sc->csr_reg, sc->reg_2);
848 (*sc->ext_cfg_exit_f)(sc, 0);
850 /* Read global timeout override tunable, Add per device sysctls. */
851 if (TUNABLE_ULONG_FETCH("hw.wbwd.timeout_override", &timeout)) {
853 sc->timeout_override = timeout;
855 sctx = device_get_sysctl_ctx(dev);
856 soid = device_get_sysctl_tree(dev);
857 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO,
858 "timeout_override", CTLFLAG_RW, &sc->timeout_override, 0,
859 "Timeout in seconds overriding default watchdog timeout");
860 SYSCTL_ADD_INT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO,
861 "debug_verbose", CTLFLAG_RW, &sc->debug_verbose, 0,
862 "Enables extra debugging information");
863 SYSCTL_ADD_PROC(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "debug",
864 CTLTYPE_STRING|CTLFLAG_RD, sc, 0, sysctl_wb_debug, "A",
865 "Selected register information from last change by driver");
866 SYSCTL_ADD_PROC(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "debug_current",
867 CTLTYPE_STRING|CTLFLAG_RD|CTLFLAG_SKIP, sc, 0,
868 sysctl_wb_debug_current, "A",
869 "Selected register information (may interfere)");
870 SYSCTL_ADD_PROC(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "force_timeout",
871 CTLTYPE_INT|CTLFLAG_RW|CTLFLAG_SKIP, sc, 0,
872 sysctl_wb_force_test_nmi, "I", "Enable to force watchdog to fire.");
874 /* Register watchdog. */
875 sc->ev_tag = EVENTHANDLER_REGISTER(watchdog_list, wb_watchdog_fn, sc,
879 wb_print_state(sc, "After watchdog attach");
885 wb_detach(device_t dev)
889 sc = device_get_softc(dev);
891 /* Unregister and stop the watchdog if running. */
893 EVENTHANDLER_DEREGISTER(watchdog_list, sc->ev_tag);
894 wb_set_watchdog(sc, 0);
896 /* Disable extended function mode. */
897 (*sc->ext_cfg_exit_f)(sc, 0);
899 /* Cleanup resources. */
900 (void) bus_release_resource(dev, SYS_RES_IOPORT, sc->rid, sc->portres);
902 /* Bus subroutines take care of sysctls already. */
907 static device_method_t wb_methods[] = {
908 /* Device interface */
909 DEVMETHOD(device_identify, wb_identify),
910 DEVMETHOD(device_probe, wb_probe),
911 DEVMETHOD(device_attach, wb_attach),
912 DEVMETHOD(device_detach, wb_detach),
917 static driver_t wb_isa_driver = {
920 sizeof(struct wb_softc)
923 static devclass_t wb_devclass;
925 DRIVER_MODULE(wb, isa, wb_isa_driver, wb_devclass, NULL, NULL);