2 * Copyright (c) 2011 Sandvine Incorporated ULC.
3 * Copyright (c) 2012 iXsystems, Inc.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * Support for Winbond watchdog.
30 * With minor abstractions it might be possible to add support for other
31 * different Winbond Super I/O chips as well. Winbond seems to have four
32 * different types of chips, four different ways to get into extended config
35 * Note: there is no serialization between the debugging sysctl handlers and
36 * the watchdog functions and possibly others poking the registers at the same
37 * time. For that at least possibly interfering sysctls are hidden by default.
40 #include <sys/cdefs.h>
41 __FBSDID("$FreeBSD$");
43 #include <sys/param.h>
44 #include <sys/kernel.h>
45 #include <sys/systm.h>
47 #include <sys/eventhandler.h>
49 #include <sys/module.h>
52 #include <sys/sysctl.h>
53 #include <sys/watchdog.h>
55 #include <isa/isavar.h>
57 #include <machine/bus.h>
58 #include <machine/resource.h>
63 #define WB_DEVICE_ID_REG 0x20 /* Device ID */
64 #define WB_DEVICE_REV_REG 0x21 /* Device revision */
65 #define WB_CR26 0x26 /* Bit6: HEFRAS (base port selector) */
68 #define WB_LDN_REG 0x07
69 #define WB_LDN_REG_LDN8 0x08 /* GPIO 2, Watchdog */
72 * LDN8 (GPIO 2, Watchdog) specific registers and options.
74 /* CR30: LDN8 activation control. */
75 #define WB_LDN8_CR30 0x30
76 #define WB_LDN8_CR30_ACTIVE 0x01 /* 1: LD active */
78 /* CRF5: Watchdog scale, P20. Mapped to reg_1. */
79 #define WB_LDN8_CRF5 0xF5
80 #define WB_LDN8_CRF5_SCALE 0x08 /* 0: 1s, 1: 60s */
81 #define WB_LDN8_CRF5_KEYB_P20 0x04 /* 1: keyb P20 forces timeout */
82 #define WB_LDN8_CRF5_KBRST 0x02 /* 1: timeout causes pin60 kbd reset */
84 /* CRF6: Watchdog Timeout (0 == off). Mapped to reg_timeout. */
85 #define WB_LDN8_CRF6 0xF6
87 /* CRF7: Watchdog mouse, keyb, force, .. Mapped to reg_2. */
88 #define WB_LDN8_CRF7 0xF7
89 #define WB_LDN8_CRF7_MOUSE 0x80 /* 1: mouse irq resets wd timer */
90 #define WB_LDN8_CRF7_KEYB 0x40 /* 1: keyb irq resets wd timer */
91 #define WB_LDN8_CRF7_FORCE 0x20 /* 1: force timeout (self-clear) */
92 #define WB_LDN8_CRF7_TS 0x10 /* 0: counting, 1: fired */
93 #define WB_LDN8_CRF7_IRQS 0x0f /* irq source for watchdog, 2 == SMI */
94 #define WB_LDN8_CRF7_CLEAR_MASK \
95 (WB_LDN8_CRF7_MOUSE|WB_LDN8_CRF7_KEYB|WB_LDN8_CRF7_TS|WB_LDN8_CRF7_IRQS)
99 struct resource *portres;
101 bus_space_handle_t bsh;
103 eventhandler_tag ev_tag;
104 int (*ext_cfg_enter_f)(struct wb_softc *, u_short);
105 void (*ext_cfg_exit_f)(struct wb_softc *, u_short);
109 * Special feature to let the watchdog fire at a different
110 * timeout as set by watchdog(4) but still use that API to
111 * re-load it periodically.
113 unsigned int timeout_override;
116 * Space to save current state temporary and for sysctls.
117 * We want to know the timeout value and usually need two
118 * additional registers for options. Do not name them by
119 * register as these might be different by chip.
126 static int ext_cfg_enter_0x87_0x87(struct wb_softc *, u_short);
127 static void ext_cfg_exit_0xaa(struct wb_softc *, u_short);
129 struct winbond_superio_cfg {
130 uint8_t efer; /* and efir */
131 int (*ext_cfg_enter_f)(struct wb_softc *, u_short);
132 void (*ext_cfg_exit_f)(struct wb_softc *, u_short);
136 .ext_cfg_enter_f = ext_cfg_enter_0x87_0x87,
137 .ext_cfg_exit_f = ext_cfg_exit_0xaa,
141 .ext_cfg_enter_f = ext_cfg_enter_0x87_0x87,
142 .ext_cfg_exit_f = ext_cfg_exit_0xaa,
146 struct winbond_vendor_device_id {
156 .descr = "Winbond 83627HF/F/HG/G Rev. G",
162 .descr = "Winbond 83627HF/F/HG/G Rev. J",
168 .descr = "Winbond 83627HF/F/HG/G Rev. UD-A",
174 .descr = "Winbond 83627DHG IC ver. 5",
180 .descr = "Winbond 83627DHG-P",
186 .descr = "Nuvoton WPCM450RA0BX",
191 write_efir_1(struct wb_softc *sc, u_short baseport, uint8_t value)
194 MPASS(sc != NULL || baseport != 0);
196 bus_space_write_1((sc)->bst, (sc)->bsh, 0, (value));
198 outb(baseport, value);
201 static uint8_t __unused
202 read_efir_1(struct wb_softc *sc, u_short baseport)
205 MPASS(sc != NULL || baseport != 0);
207 return (bus_space_read_1((sc)->bst, (sc)->bsh, 0));
209 return (inb(baseport));
213 write_efdr_1(struct wb_softc *sc, u_short baseport, uint8_t value)
216 MPASS(sc != NULL || baseport != 0);
218 bus_space_write_1((sc)->bst, (sc)->bsh, 1, (value));
220 outb(baseport + 1, value);
224 read_efdr_1(struct wb_softc *sc, u_short baseport)
227 MPASS(sc != NULL || baseport != 0);
229 return (bus_space_read_1((sc)->bst, (sc)->bsh, 1));
231 return (inb(baseport + 1));
235 * Return the watchdog related registers as we last read them. This will
236 * usually not give the current timeout or state on whether the watchdog
240 sysctl_wb_debug(SYSCTL_HANDLER_ARGS)
248 sbuf_new_for_sysctl(&sb, NULL, 64, req);
250 sbuf_printf(&sb, "LDN8 (GPIO2, Watchdog): ");
251 sbuf_printf(&sb, "CRF5 0x%02x ", sc->reg_1);
252 sbuf_printf(&sb, "CRF6 0x%02x ", sc->reg_timeout);
253 sbuf_printf(&sb, "CRF7 0x%02x", sc->reg_2);
255 error = sbuf_finish(&sb);
261 * Read the current values before returning them. Given this might poke
262 * the registers the same time as the watchdog, this sysctl handler should
263 * be marked CTLFLAG_SKIP to not show up by default.
266 sysctl_wb_debug_current(SYSCTL_HANDLER_ARGS)
273 * Enter extended function mode in case someone else has been
274 * poking on the registers. We will not leave it though.
276 if ((*sc->ext_cfg_enter_f)(sc, 0) != 0)
279 /* Watchdog is configured as part of LDN 8 (GPIO Port2, Watchdog). */
280 write_efir_1(sc, 0, WB_LDN_REG);
281 write_efdr_1(sc, 0, WB_LDN_REG_LDN8);
283 write_efir_1(sc, 0, WB_LDN8_CRF5);
284 sc->reg_1 = read_efdr_1(sc, 0);
285 write_efir_1(sc, 0, WB_LDN8_CRF6);
286 sc->reg_timeout = read_efdr_1(sc, 0);
287 write_efir_1(sc, 0, WB_LDN8_CRF7);
288 sc->reg_2 = read_efdr_1(sc, 0);
290 return (sysctl_wb_debug(oidp, arg1, arg2, req));
294 * Sysctl handlers to force a watchdog timeout or to test the NMI functionality
296 * For testing we could set a test_nmi flag in the softc that, in case of NMI, a
297 * callback function from trap.c could check whether we fired and not report the
298 * timeout but clear the flag for the sysctl again. This is interesting given a
299 * lot of boards have jumpers to change the action on watchdog timeout or
300 * disable the watchdog completely.
301 * XXX-BZ notyet: currently no general infrastructure exists to do this.
304 sysctl_wb_force_test_nmi(SYSCTL_HANDLER_ARGS)
307 int error, test, val;
317 error = sysctl_handle_int(oidp, &val, 0, req);
318 if (error || !req->newptr)
322 /* Manually clear the test for a value of 0 and do nothing else. */
323 if (test && val == 0) {
330 * Enter extended function mode in case someone else has been
331 * poking on the registers. We will not leave it though.
333 if ((*sc->ext_cfg_enter_f)(sc, 0) != 0)
338 * If we are testing the NMI functionality, set the flag before
339 * forcing the timeout.
345 /* Watchdog is configured as part of LDN 8 (GPIO Port2, Watchdog). */
346 write_efir_1(sc, 0, WB_LDN_REG);
347 write_efdr_1(sc, 0, WB_LDN_REG_LDN8);
349 /* Force watchdog to fire. */
350 write_efir_1(sc, 0, WB_LDN8_CRF7);
351 sc->reg_2 = read_efdr_1(sc, 0);
352 sc->reg_2 |= WB_LDN8_CRF7_FORCE;
354 write_efir_1(sc, 0, WB_LDN8_CRF7);
355 write_efdr_1(sc, 0, sc->reg_2);
361 * Print current watchdog state.
363 * Note: it is the responsibility of the caller to update the registers
367 wb_print_state(struct wb_softc *sc, const char *msg)
370 device_printf(sc->dev, "%s%sWatchdog %sabled. %s"
371 "Scaling by %ds, timer at %d (%s=%ds%s). "
372 "CRF5 0x%02x CRF7 0x%02x\n",
373 (msg != NULL) ? msg : "", (msg != NULL) ? ": " : "",
374 (sc->reg_timeout > 0x00) ? "en" : "dis",
375 (sc->reg_2 & WB_LDN8_CRF7_TS) ? "Watchdog fired. " : "",
376 (sc->reg_1 & WB_LDN8_CRF5_SCALE) ? 60 : 1,
378 (sc->reg_timeout > 0x00) ? "<" : "",
379 sc->reg_timeout * ((sc->reg_1 & WB_LDN8_CRF5_SCALE) ? 60 : 1),
380 (sc->reg_timeout > 0x00) ? " left" : "",
381 sc->reg_1, sc->reg_2);
385 * Functions to enter and exit extended function mode. Possibly shared
386 * between different chips.
389 ext_cfg_enter_0x87_0x87(struct wb_softc *sc, u_short baseport)
393 * Enable extended function mode.
394 * Winbond does not allow us to validate so always return success.
396 write_efir_1(sc, baseport, 0x87);
397 write_efir_1(sc, baseport, 0x87);
403 ext_cfg_exit_0xaa(struct wb_softc *sc, u_short baseport)
406 write_efir_1(sc, baseport, 0xaa);
410 * (Re)load the watchdog counter depending on timeout. A timeout of 0 will
411 * disable the watchdog.
414 wb_set_watchdog(struct wb_softc *sc, unsigned int timeout)
417 if (sc->debug_verbose)
418 wb_print_state(sc, "Before watchdog counter (re)load");
421 * Enter extended function mode in case someone else has been
422 * poking on the registers. We will not leave it though.
424 if ((*sc->ext_cfg_enter_f)(sc, 0) != 0)
427 /* Watchdog is configured as part of LDN 8 (GPIO Port2, Watchdog) */
428 write_efir_1(sc, 0, WB_LDN_REG);
429 write_efdr_1(sc, 0, WB_LDN_REG_LDN8);
431 /* Disable and validate or arm/reset watchdog. */
433 /* Disable watchdog. */
434 write_efir_1(sc, 0, WB_LDN8_CRF6);
435 write_efdr_1(sc, 0, 0x00);
438 write_efir_1(sc, 0, WB_LDN8_CRF6);
439 sc->reg_timeout = read_efdr_1(sc, 0);
441 if (sc->reg_timeout != 0x00) {
442 device_printf(sc->dev, "Failed to disable watchdog: "
443 "0x%02x.\n", sc->reg_timeout);
449 * In case an override is set, let it override. It may lead
450 * to strange results as we do not check the input of the sysctl.
452 if (sc->timeout_override > 0)
453 timeout = sc->timeout_override;
455 /* Make sure we support the requested timeout. */
456 if (timeout > 255 * 60)
459 /* Read current scaling factor. */
460 write_efir_1(sc, 0, WB_LDN8_CRF5);
461 sc->reg_1 = read_efdr_1(sc, 0);
464 /* Set scaling factor to 60s. */
465 sc->reg_1 |= WB_LDN8_CRF5_SCALE;
466 sc->reg_timeout = (timeout / 60);
470 /* Set scaling factor to 1s. */
471 sc->reg_1 &= ~WB_LDN8_CRF5_SCALE;
472 sc->reg_timeout = timeout;
475 /* In case we fired before we need to clear to fire again. */
476 write_efir_1(sc, 0, WB_LDN8_CRF7);
477 sc->reg_2 = read_efdr_1(sc, 0);
478 if (sc->reg_2 & WB_LDN8_CRF7_TS) {
479 sc->reg_2 &= ~WB_LDN8_CRF7_TS;
480 write_efir_1(sc, 0, WB_LDN8_CRF7);
481 write_efdr_1(sc, 0, sc->reg_2);
484 /* Write back scaling factor. */
485 write_efir_1(sc, 0, WB_LDN8_CRF5);
486 write_efdr_1(sc, 0, sc->reg_1);
488 /* Set timer and arm/reset the watchdog. */
489 write_efir_1(sc, 0, WB_LDN8_CRF6);
490 write_efdr_1(sc, 0, sc->reg_timeout);
493 if (sc->debug_verbose)
494 wb_print_state(sc, "After watchdog counter (re)load");
500 * watchdog(9) EVENTHANDLER function implementation to (re)load the counter
501 * with the given timeout or disable the watchdog.
504 wb_watchdog_fn(void *private, u_int cmd, int *error)
507 unsigned int timeout;
511 KASSERT(sc != NULL, ("%s: watchdog handler function called without "
512 "softc.", __func__));
515 if (cmd > 0 && cmd <= 63) {
516 /* Reset (and arm) watchdog. */
517 timeout = ((uint64_t)1 << cmd) / 1000000000;
520 e = wb_set_watchdog(sc, timeout);
525 /* On error, try to make sure the WD is disabled. */
526 wb_set_watchdog(sc, 0);
530 /* Disable watchdog. */
531 e = wb_set_watchdog(sc, 0);
532 if (e != 0 && cmd == 0 && error != NULL) {
533 /* Failed to disable watchdog. */
540 * Probe/attach the Winbond Super I/O chip.
542 * Initial abstraction to possibly support more chips:
543 * - Iterate over the well known base ports, try to enable extended function
544 * mode and read and match the device ID and device revision. Unfortunately
545 * the Vendor ID is in the hardware monitoring section accessible by different
547 * - Also HEFRAS, which would tell use the base port, is only accessible after
548 * entering extended function mode, for which the base port is needed.
549 * At least check HEFRAS to match the current base port we are probing.
550 * - On match set the description, remember functions to enter/exit extended
551 * function mode as well as the base port.
554 wb_probe_enable(device_t dev, int probe)
557 int error, found, i, j;
558 uint8_t dev_id, dev_rev, cr26;
563 sc = device_get_softc(dev);
564 bzero(sc, sizeof(*sc));
569 for (i = 0; i < sizeof(probe_addrs) / sizeof(*probe_addrs); i++) {
572 /* Allocate bus resources for IO index/data register access. */
573 sc->portres = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->rid,
574 probe_addrs[i].efer, probe_addrs[i].efer + 1, 2, RF_ACTIVE);
575 if (sc->portres == NULL)
577 sc->bst = rman_get_bustag(sc->portres);
578 sc->bsh = rman_get_bushandle(sc->portres);
582 error = (*probe_addrs[i].ext_cfg_enter_f)(sc, probe_addrs[i].efer);
586 /* Identify the SuperIO chip. */
587 write_efir_1(sc, probe_addrs[i].efer, WB_DEVICE_ID_REG);
588 dev_id = read_efdr_1(sc, probe_addrs[i].efer);
589 write_efir_1(sc, probe_addrs[i].efer, WB_DEVICE_REV_REG);
590 dev_rev = read_efdr_1(sc, probe_addrs[i].efer);
591 write_efir_1(sc, probe_addrs[i].efer, WB_CR26);
592 cr26 = read_efdr_1(sc, probe_addrs[i].efer);
594 /* HEFRAS of 0 means EFER at 0x2e, 1 means EFER at 0x4e. */
595 if (((cr26 & 0x40) == 0x00 && probe_addrs[i].efer != 0x2e) ||
596 ((cr26 & 0x40) == 0x40 && probe_addrs[i].efer != 0x4e)) {
598 device_printf(dev, "HEFRAS and EFER do not "
599 "align: EFER 0x%02x DevID 0x%02x DevRev "
600 "0x%02x CR26 0x%02x\n",
601 probe_addrs[i].efer, dev_id, dev_rev, cr26);
605 if (dev_id == 0xff && dev_rev == 0xff)
608 for (j = 0; j < sizeof(wb_devs) / sizeof(*wb_devs); j++) {
609 if (wb_devs[j].device_id == dev_id &&
610 wb_devs[j].device_rev == dev_rev) {
611 if (probe && dev != NULL)
612 device_set_desc(dev, wb_devs[j].descr);
619 if (probe && dev != NULL) {
620 device_set_desc(dev, "Unknown Winbond/Nuvoton model");
621 device_printf(dev, "DevID 0x%02x DevRev 0x%02x, "
622 "please report this.\n", dev_id, dev_rev);
627 if (probe && found && bootverbose && dev != NULL)
628 device_printf(dev, "%s EFER 0x%02x ID 0x%02x Rev 0x%02x"
629 " CR26 0x%02x (probing)\n", device_get_desc(dev),
630 probe_addrs[i].efer, dev_id, dev_rev, cr26);
632 if (probe || !found) {
633 (*probe_addrs[i].ext_cfg_exit_f)(sc, probe_addrs[i].efer);
636 (void) bus_release_resource(dev, SYS_RES_IOPORT,
637 sc->rid, sc->portres);
641 * Stop probing if have successfully identified the SuperIO.
642 * Remember the extended function mode enter/exit functions
647 sc->ext_cfg_enter_f = probe_addrs[i].ext_cfg_enter_f;
648 sc->ext_cfg_exit_f = probe_addrs[i].ext_cfg_exit_f;
650 error = BUS_PROBE_DEFAULT;
660 wb_identify(driver_t *driver, device_t parent)
664 if ((dev = device_find_child(parent, driver->name, 0)) == NULL) {
665 if (wb_probe_enable(dev, 1) != BUS_PROBE_DEFAULT) {
667 device_printf(dev, "can not find compatible Winbond chip.\n");
669 dev = BUS_ADD_CHILD(parent, 0, driver->name, 0);
675 wb_probe(device_t dev)
678 /* Make sure we do not claim some ISA PNP device. */
679 if (isa_get_logicalid(dev) != 0)
682 return (wb_probe_enable(dev, 1));
686 wb_attach(device_t dev)
689 struct sysctl_ctx_list *sctx;
690 struct sysctl_oid *soid;
691 unsigned long timeout;
694 error = wb_probe_enable(dev, 0);
698 sc = device_get_softc(dev);
699 KASSERT(sc->ext_cfg_enter_f != NULL && sc->ext_cfg_exit_f != NULL,
700 ("%s: successfull probe result but not setup correctly", __func__));
702 /* Watchdog is configured as part of LDN 8 (GPIO Port2, Watchdog). */
703 write_efir_1(sc, 0, WB_LDN_REG);
704 write_efdr_1(sc, 0, WB_LDN_REG_LDN8);
706 /* Make sure LDN8 is enabled (Do we need to? Also affects GPIO). */
707 write_efir_1(sc, 0, WB_LDN8_CR30);
708 write_efdr_1(sc, 0, WB_LDN8_CR30_ACTIVE);
710 /* Read the current watchdog configuration. */
711 write_efir_1(sc, 0, WB_LDN8_CRF5);
712 sc->reg_1 = read_efdr_1(sc, 0);
713 write_efir_1(sc, 0, WB_LDN8_CRF6);
714 sc->reg_timeout = read_efdr_1(sc, 0);
715 write_efir_1(sc, 0, WB_LDN8_CRF7);
716 sc->reg_2 = read_efdr_1(sc, 0);
718 /* Print current state if bootverbose or watchdog already enabled. */
719 if (bootverbose || (sc->reg_timeout > 0x00))
720 wb_print_state(sc, "Before watchdog attach");
723 * Clear a previous watchdog timeout event (if (still) set).
724 * Disable all all interrupt reset sources (defaults).
726 sc->reg_1 &= ~(WB_LDN8_CRF5_KEYB_P20);
727 sc->reg_1 |= WB_LDN8_CRF5_KBRST;
728 write_efir_1(sc, 0, WB_LDN8_CRF5);
729 write_efdr_1(sc, 0, sc->reg_1);
731 sc->reg_2 &= ~WB_LDN8_CRF7_CLEAR_MASK;
732 write_efir_1(sc, 0, WB_LDN8_CRF7);
733 write_efdr_1(sc, 0, sc->reg_2);
735 /* Read global timeout override tunable, Add per device sysctls. */
736 if (TUNABLE_ULONG_FETCH("hw.wbwd.timeout_override", &timeout)) {
738 sc->timeout_override = timeout;
740 sctx = device_get_sysctl_ctx(dev);
741 soid = device_get_sysctl_tree(dev);
742 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO,
743 "timeout_override", CTLFLAG_RW, &sc->timeout_override, 0,
744 "Timeout in seconds overriding default watchdog timeout");
745 SYSCTL_ADD_INT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO,
746 "debug_verbose", CTLFLAG_RW, &sc->debug_verbose, 0,
747 "Enables extra debugging information");
748 SYSCTL_ADD_PROC(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "debug",
749 CTLTYPE_STRING|CTLFLAG_RD, sc, 0, sysctl_wb_debug, "A",
750 "Selected register information from last change by driver");
751 SYSCTL_ADD_PROC(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "debug_current",
752 CTLTYPE_STRING|CTLFLAG_RD|CTLFLAG_SKIP, sc, 0,
753 sysctl_wb_debug_current, "A",
754 "Selected register information (may interfere)");
755 SYSCTL_ADD_PROC(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "force_timeout",
756 CTLTYPE_INT|CTLFLAG_RW|CTLFLAG_SKIP, sc, 0,
757 sysctl_wb_force_test_nmi, "I", "Enable to force watchdog to fire.");
759 /* Register watchdog. */
760 sc->ev_tag = EVENTHANDLER_REGISTER(watchdog_list, wb_watchdog_fn, sc,
764 wb_print_state(sc, "After watchdog attach");
770 wb_detach(device_t dev)
774 sc = device_get_softc(dev);
776 /* Unregister and stop the watchdog if running. */
778 EVENTHANDLER_DEREGISTER(watchdog_list, sc->ev_tag);
779 wb_set_watchdog(sc, 0);
781 /* Disable extended function mode. */
782 (*sc->ext_cfg_exit_f)(sc, 0);
784 /* Cleanup resources. */
785 (void) bus_release_resource(dev, SYS_RES_IOPORT, sc->rid, sc->portres);
787 /* Bus subroutines take care of sysctls already. */
792 static device_method_t wb_methods[] = {
793 /* Device interface */
794 DEVMETHOD(device_identify, wb_identify),
795 DEVMETHOD(device_probe, wb_probe),
796 DEVMETHOD(device_attach, wb_attach),
797 DEVMETHOD(device_detach, wb_detach),
802 static driver_t wb_isa_driver = {
805 sizeof(struct wb_softc)
808 static devclass_t wb_devclass;
810 DRIVER_MODULE(wb, isa, wb_isa_driver, wb_devclass, NULL, NULL);