2 * Copyright (c) 2011 Sandvine Incorporated ULC.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * Support for Winbond watchdog.
29 * With minor abstractions it might be possible to add support for other
30 * different Winbond Super I/O chips as well. Winbond seems to have four
31 * different types of chips, four different ways to get into extended config
34 * Note: there is no serialization between the debugging sysctl handlers and
35 * the watchdog functions and possibly others poking the registers at the same
36 * time. For that at least possibly interfering sysctls are hidden by default.
39 #include <sys/cdefs.h>
40 __FBSDID("$FreeBSD$");
42 #include <sys/param.h>
43 #include <sys/kernel.h>
44 #include <sys/systm.h>
46 #include <sys/eventhandler.h>
48 #include <sys/module.h>
51 #include <sys/sysctl.h>
52 #include <sys/watchdog.h>
54 #include <isa/isavar.h>
56 #include <machine/bus.h>
57 #include <machine/resource.h>
62 #define WB_DEVICE_ID_REG 0x20 /* Device ID */
63 #define WB_DEVICE_REV_REG 0x21 /* Device revision */
64 #define WB_CR26 0x26 /* Bit6: HEFRAS (base port selector) */
67 #define WB_LDN_REG 0x07
68 #define WB_LDN_REG_LDN8 0x08 /* GPIO 2, Watchdog */
71 * LDN8 (GPIO 2, Watchdog) specific registers and options.
73 /* CR30: LDN8 activation control. */
74 #define WB_LDN8_CR30 0x30
75 #define WB_LDN8_CR30_ACTIVE 0x01 /* 1: LD active */
77 /* CRF5: Watchdog scale, P20. Mapped to reg_1. */
78 #define WB_LDN8_CRF5 0xF5
79 #define WB_LDN8_CRF5_SCALE 0x08 /* 0: 1s, 1: 60s */
80 #define WB_LDN8_CRF5_KEYB_P20 0x04 /* 1: keyb P20 forces timeout */
82 /* CRF6: Watchdog Timeout (0 == off). Mapped to reg_timeout. */
83 #define WB_LDN8_CRF6 0xF6
85 /* CRF7: Watchdog mouse, keyb, force, .. Mapped to reg_2. */
86 #define WB_LDN8_CRF7 0xF7
87 #define WB_LDN8_CRF7_MOUSE 0x80 /* 1: mouse irq resets wd timer */
88 #define WB_LDN8_CRF7_KEYB 0x40 /* 1: keyb irq resets wd timer */
89 #define WB_LDN8_CRF7_FORCE 0x20 /* 1: force timeout (self-clear) */
90 #define WB_LDN8_CRF7_TS 0x10 /* 0: counting, 1: fired */
91 #define WB_LDN8_CRF7_IRQS 0x0f /* irq source for watchdog, 2 == SMI */
92 #define WB_LDN8_CRF7_CLEAR_MASK \
93 (WB_LDN8_CRF7_MOUSE|WB_LDN8_CRF7_KEYB|WB_LDN8_CRF7_TS|WB_LDN8_CRF7_IRQS)
95 #define write_efir_1(sc, value) \
96 bus_space_write_1((sc)->bst, (sc)->bsh, 0, (value))
97 #define read_efir_1(sc) \
98 bus_space_read_1((sc)->bst, (sc)->bsh, 0)
99 #define write_efdr_1(sc, value) \
100 bus_space_write_1((sc)->bst, (sc)->bsh, 1, (value))
101 #define read_efdr_1(sc) \
102 bus_space_read_1((sc)->bst, (sc)->bsh, 1)
106 struct resource *portres;
108 bus_space_handle_t bsh;
110 eventhandler_tag ev_tag;
111 int (*ext_cfg_enter_f)(struct wb_softc *);
112 void (*ext_cfg_exit_f)(struct wb_softc *);
116 * Special feature to let the watchdog fire at a different
117 * timeout as set by watchdog(4) but still use that API to
118 * re-load it periodically.
120 unsigned int timeout_override;
123 * Space to save current state temporary and for sysctls.
124 * We want to know the timeout value and usually need two
125 * additional registers for options. Do not name them by
126 * register as these might be different by chip.
133 static int ext_cfg_enter_0x87_0x87(struct wb_softc *);
134 static void ext_cfg_exit_0xaa(struct wb_softc *);
136 struct winbond_superio_cfg {
137 uint8_t efer; /* and efir */
138 int (*ext_cfg_enter_f)(struct wb_softc *);
139 void (*ext_cfg_exit_f)(struct wb_softc *);
143 .ext_cfg_enter_f = ext_cfg_enter_0x87_0x87,
144 .ext_cfg_exit_f = ext_cfg_exit_0xaa,
148 .ext_cfg_enter_f = ext_cfg_enter_0x87_0x87,
149 .ext_cfg_exit_f = ext_cfg_exit_0xaa,
153 struct winbond_vendor_device_id {
163 .descr = "Winbond 83627HF/F/HG/G Rev. G",
169 .descr = "Winbond 83627HF/F/HG/G Rev. J",
175 .descr = "Winbond 83627HF/F/HG/G Rev. UD-A",
181 .descr = "Winbond 83627DHG IC ver. 5",
186 * Return the watchdog related registers as we last read them. This will
187 * usually not give the current timeout or state on whether the watchdog
191 sysctl_wb_debug(SYSCTL_HANDLER_ARGS)
199 sbuf_new_for_sysctl(&sb, NULL, 64, req);
201 sbuf_printf(&sb, "LDN8 (GPIO2, Watchdog): ");
202 sbuf_printf(&sb, "CRF5 0x%02x ", sc->reg_1);
203 sbuf_printf(&sb, "CRF6 0x%02x ", sc->reg_timeout);
204 sbuf_printf(&sb, "CRF7 0x%02x ", sc->reg_2);
207 error = sbuf_finish(&sb);
213 * Read the current values before returning them. Given this might poke
214 * the registers the same time as the watchdog, this sysctl handler should
215 * be marked CTLFLAG_SKIP to not show up by default.
218 sysctl_wb_debug_current(SYSCTL_HANDLER_ARGS)
225 * Enter extended function mode in case someone else has been
226 * poking on the registers. We will not leave it though.
228 if ((*sc->ext_cfg_enter_f)(sc) != 0)
231 /* Watchdog is configured as part of LDN 8 (GPIO Port2, Watchdog). */
232 write_efir_1(sc, WB_LDN_REG);
233 write_efdr_1(sc, WB_LDN_REG_LDN8);
235 write_efir_1(sc, WB_LDN8_CRF5);
236 sc->reg_1 = read_efdr_1(sc);
237 write_efir_1(sc, WB_LDN8_CRF6);
238 sc->reg_timeout = read_efdr_1(sc);
239 write_efir_1(sc, WB_LDN8_CRF7);
240 sc->reg_2 = read_efdr_1(sc);
242 return (sysctl_wb_debug(oidp, arg1, arg2, req));
246 * Sysctl handlers to force a watchdog timeout or to test the NMI functionality
248 * For testing we could set a test_nmi flag in the softc that, in case of NMI, a
249 * callback function from trap.c could check whether we fired and not report the
250 * timeout but clear the flag for the sysctl again. This is interesting given a
251 * lot of boards have jumpers to change the action on watchdog timeout or
252 * disable the watchdog completely.
253 * XXX-BZ notyet: currently no general infrastructure exists to do this.
256 sysctl_wb_force_test_nmi(SYSCTL_HANDLER_ARGS)
259 int error, test, val;
269 error = sysctl_handle_int(oidp, &val, 0, req);
270 if (error || !req->newptr)
274 /* Manually clear the test for a value of 0 and do nothing else. */
275 if (test && val == 0) {
282 * Enter extended function mode in case someone else has been
283 * poking on the registers. We will not leave it though.
285 if ((*sc->ext_cfg_enter_f)(sc) != 0)
290 * If we are testing the NMI functionality, set the flag before
291 * forcing the timeout.
297 /* Watchdog is configured as part of LDN 8 (GPIO Port2, Watchdog). */
298 write_efir_1(sc, WB_LDN_REG);
299 write_efdr_1(sc, WB_LDN_REG_LDN8);
301 /* Force watchdog to fire. */
302 write_efir_1(sc, WB_LDN8_CRF7);
303 sc->reg_2 = read_efdr_1(sc);
304 sc->reg_2 |= WB_LDN8_CRF7_FORCE;
306 write_efir_1(sc, WB_LDN8_CRF7);
307 write_efdr_1(sc, sc->reg_2);
313 * Print current watchdog state.
315 * Note: it is the responsibility of the caller to update the registers
319 wb_print_state(struct wb_softc *sc, const char *msg)
322 device_printf(sc->dev, "%s%sWatchdog %sabled. %s"
323 "Scaling by %ds, timer at %d (%s=%ds%s). "
324 "CRF5 0x%02x CRF7 0x%02x\n",
325 (msg != NULL) ? msg : "", (msg != NULL) ? ": " : "",
326 (sc->reg_timeout > 0x00) ? "en" : "dis",
327 (sc->reg_2 & WB_LDN8_CRF7_TS) ? "Watchdog fired. " : "",
328 (sc->reg_1 & WB_LDN8_CRF5_SCALE) ? 60 : 1,
330 (sc->reg_timeout > 0x00) ? "<" : "",
331 sc->reg_timeout * ((sc->reg_1 & WB_LDN8_CRF5_SCALE) ? 60 : 1),
332 (sc->reg_timeout > 0x00) ? " left" : "",
333 sc->reg_1, sc->reg_2);
337 * Functions to enter and exit extended function mode. Possibly shared
338 * between different chips.
341 ext_cfg_enter_0x87_0x87(struct wb_softc *sc)
345 * Enable extended function mode.
346 * Winbond does not allow us to validate so always return success.
348 write_efir_1(sc, 0x87);
349 write_efir_1(sc, 0x87);
355 ext_cfg_exit_0xaa(struct wb_softc *sc)
358 write_efir_1(sc, 0xaa);
362 * (Re)load the watchdog counter depending on timeout. A timeout of 0 will
363 * disable the watchdog.
366 wb_set_watchdog(struct wb_softc *sc, unsigned int timeout)
369 if (sc->debug_verbose)
370 wb_print_state(sc, "Before watchdog counter (re)load");
373 * Enter extended function mode in case someone else has been
374 * poking on the registers. We will not leave it though.
376 if ((*sc->ext_cfg_enter_f)(sc) != 0)
379 /* Watchdog is configured as part of LDN 8 (GPIO Port2, Watchdog) */
380 write_efir_1(sc, WB_LDN_REG);
381 write_efdr_1(sc, WB_LDN_REG_LDN8);
383 /* Disable and validate or arm/reset watchdog. */
385 /* Disable watchdog. */
386 write_efir_1(sc, WB_LDN8_CRF6);
387 write_efdr_1(sc, 0x00);
390 write_efir_1(sc, WB_LDN8_CRF6);
391 sc->reg_timeout = read_efdr_1(sc);
393 if (sc->reg_timeout != 0x00) {
394 device_printf(sc->dev, "Failed to disable watchdog: "
395 "0x%02x.\n", sc->reg_timeout);
401 * In case an override is set, let it override. It may lead
402 * to strange results as we do not check the input of the sysctl.
404 if (sc->timeout_override > 0)
405 timeout = sc->timeout_override;
407 /* Make sure we support the requested timeout. */
408 if (timeout > 255 * 60)
411 /* Read current scaling factor. */
412 write_efir_1(sc, WB_LDN8_CRF5);
413 sc->reg_1 = read_efdr_1(sc);
416 /* Set scaling factor to 60s. */
417 sc->reg_1 |= WB_LDN8_CRF5_SCALE;
418 sc->reg_timeout = (timeout / 60);
422 /* Set scaling factor to 1s. */
423 sc->reg_1 &= ~WB_LDN8_CRF5_SCALE;
424 sc->reg_timeout = timeout;
427 /* In case we fired before we need to clear to fire again. */
428 write_efir_1(sc, WB_LDN8_CRF7);
429 sc->reg_2 = read_efdr_1(sc);
430 if (sc->reg_2 & WB_LDN8_CRF7_TS) {
431 sc->reg_2 &= ~WB_LDN8_CRF7_TS;
432 write_efir_1(sc, WB_LDN8_CRF7);
433 write_efdr_1(sc, sc->reg_2);
436 /* Write back scaling factor. */
437 write_efir_1(sc, WB_LDN8_CRF5);
438 write_efdr_1(sc, sc->reg_1);
440 /* Set timer and arm/reset the watchdog. */
441 write_efir_1(sc, WB_LDN8_CRF6);
442 write_efdr_1(sc, sc->reg_timeout);
445 if (sc->debug_verbose)
446 wb_print_state(sc, "After watchdog counter (re)load");
452 * watchdog(9) EVENTHANDLER function implementation to (re)load the counter
453 * with the given timeout or disable the watchdog.
456 wb_watchdog_fn(void *private, u_int cmd, int *error)
459 unsigned int timeout;
463 KASSERT(sc != NULL, ("%s: watchdog handler function called without "
464 "softc.", __func__));
467 if (cmd > 0 && cmd <= 63) {
468 /* Reset (and arm) watchdog. */
469 timeout = ((uint64_t)1 << cmd) / 1000000000;
472 e = wb_set_watchdog(sc, timeout);
477 /* On error, try to make sure the WD is disabled. */
478 wb_set_watchdog(sc, 0);
482 /* Disable watchdog. */
483 e = wb_set_watchdog(sc, 0);
484 if (e != 0 && cmd == 0 && error != NULL) {
485 /* Failed to disable watchdog. */
492 * Probe/attach the Winbond Super I/O chip.
494 * Initial abstraction to possibly support more chips:
495 * - Iterate over the well known base ports, try to enable extended function
496 * mode and read and match the device ID and device revision. Unfortunately
497 * the Vendor ID is in the hardware monitoring section accessible by different
499 * - Also HEFRAS, which would tell use the base port, is only accessible after
500 * entering extended function mode, for which the base port is needed.
501 * At least check HEFRAS to match the current base port we are probing.
502 * - On match set the description, remember functions to enter/exit extended
503 * function mode as well as the base port.
506 wb_probe_enable(device_t dev, int probe)
509 int error, found, i, j;
510 uint8_t dev_id, dev_rev, cr26;
512 sc = device_get_softc(dev);
513 bzero(sc, sizeof(*sc));
517 for (i = 0; i < sizeof(probe_addrs) / sizeof(*probe_addrs); i++) {
519 /* Allocate bus resources for IO index/data register access. */
520 sc->portres = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->rid,
521 probe_addrs[i].efer, probe_addrs[i].efer + 1, 2, RF_ACTIVE);
522 if (sc->portres == NULL)
524 sc->bst = rman_get_bustag(sc->portres);
525 sc->bsh = rman_get_bushandle(sc->portres);
528 error = (*probe_addrs[i].ext_cfg_enter_f)(sc);
532 /* Identify the SuperIO chip. */
533 write_efir_1(sc, WB_DEVICE_ID_REG);
534 dev_id = read_efdr_1(sc);
535 write_efir_1(sc, WB_DEVICE_REV_REG);
536 dev_rev = read_efdr_1(sc);
537 write_efir_1(sc, WB_CR26);
538 cr26 = read_efdr_1(sc);
540 /* HEFRAS of 0 means EFER at 0x2e, 1 means EFER at 0x4e. */
541 if (((cr26 & 0x40) == 0x00 && probe_addrs[i].efer != 0x2e) ||
542 ((cr26 & 0x40) == 0x40 && probe_addrs[i].efer != 0x4e)) {
543 device_printf(dev, "HEFRAS and EFER do not align: EFER "
544 "0x%02x DevID 0x%02x DevRev 0x%02x CR26 0x%02x\n",
545 probe_addrs[i].efer, dev_id, dev_rev, cr26);
549 for (j = 0; j < sizeof(wb_devs) / sizeof(*wb_devs); j++) {
550 if (wb_devs[j].device_id == dev_id &&
551 wb_devs[j].device_rev == dev_rev) {
553 device_set_desc(dev, wb_devs[j].descr);
558 if (probe && found && bootverbose)
559 device_printf(dev, "%s EFER 0x%02x ID 0x%02x Rev 0x%02x"
560 " CR26 0x%02x (probing)\n", device_get_desc(dev),
561 probe_addrs[i].efer, dev_id, dev_rev, cr26);
563 if (probe || !found) {
564 (*probe_addrs[i].ext_cfg_exit_f)(sc);
566 (void) bus_release_resource(dev, SYS_RES_IOPORT, sc->rid,
571 * Stop probing if have successfully identified the SuperIO.
572 * Remember the extended function mode enter/exit functions
576 sc->ext_cfg_enter_f = probe_addrs[i].ext_cfg_enter_f;
577 sc->ext_cfg_exit_f = probe_addrs[i].ext_cfg_exit_f;
578 error = BUS_PROBE_DEFAULT;
588 wb_probe(device_t dev)
591 /* Make sure we do not claim some ISA PNP device. */
592 if (isa_get_logicalid(dev) != 0)
595 return (wb_probe_enable(dev, 1));
599 wb_attach(device_t dev)
602 struct sysctl_ctx_list *sctx;
603 struct sysctl_oid *soid;
604 unsigned long timeout;
607 error = wb_probe_enable(dev, 0);
611 sc = device_get_softc(dev);
612 KASSERT(sc->ext_cfg_enter_f != NULL && sc->ext_cfg_exit_f != NULL,
613 ("%s: successfull probe result but not setup correctly", __func__));
615 /* Watchdog is configured as part of LDN 8 (GPIO Port2, Watchdog). */
616 write_efir_1(sc, WB_LDN_REG);
617 write_efdr_1(sc, WB_LDN_REG_LDN8);
619 /* Make sure LDN8 is enabled (Do we need to? Also affects GPIO). */
620 write_efir_1(sc, WB_LDN8_CR30);
621 write_efdr_1(sc, WB_LDN8_CR30_ACTIVE);
623 /* Read the current watchdog configuration. */
624 write_efir_1(sc, WB_LDN8_CRF5);
625 sc->reg_1 = read_efdr_1(sc);
626 write_efir_1(sc, WB_LDN8_CRF6);
627 sc->reg_timeout = read_efdr_1(sc);
628 write_efir_1(sc, WB_LDN8_CRF7);
629 sc->reg_2 = read_efdr_1(sc);
631 /* Print current state if bootverbose or watchdog already enabled. */
632 if (bootverbose || (sc->reg_timeout > 0x00))
633 wb_print_state(sc, "Before watchdog attach");
636 * Clear a previous watchdog timeout event (if (still) set).
637 * Disable all all interrupt reset sources (defaults).
639 sc->reg_1 &= ~(WB_LDN8_CRF5_KEYB_P20);
640 write_efir_1(sc, WB_LDN8_CRF5);
641 write_efdr_1(sc, sc->reg_1);
643 sc->reg_2 &= ~WB_LDN8_CRF7_CLEAR_MASK;
644 write_efir_1(sc, WB_LDN8_CRF7);
645 write_efdr_1(sc, sc->reg_2);
647 /* Read global timeout override tunable, Add per device sysctls. */
648 if (TUNABLE_ULONG_FETCH("hw.wbwd.timeout_override", &timeout)) {
650 sc->timeout_override = timeout;
652 sctx = device_get_sysctl_ctx(dev);
653 soid = device_get_sysctl_tree(dev);
654 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO,
655 "timeout_override", CTLFLAG_RW, &sc->timeout_override, 0,
656 "Timeout in seconds overriding default watchdog timeout");
657 SYSCTL_ADD_INT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO,
658 "debug_verbose", CTLFLAG_RW, &sc->debug_verbose, 0,
659 "Enables extra debugging information");
660 SYSCTL_ADD_PROC(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "debug",
661 CTLTYPE_STRING|CTLFLAG_RD, sc, 0, sysctl_wb_debug, "A",
662 "Selected register information from last change by driver");
663 SYSCTL_ADD_PROC(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "debug_current",
664 CTLTYPE_STRING|CTLFLAG_RD|CTLFLAG_SKIP, sc, 0,
665 sysctl_wb_debug_current, "A",
666 "Selected register information (may interfere)");
667 SYSCTL_ADD_PROC(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "force_timeout",
668 CTLTYPE_INT|CTLFLAG_RW|CTLFLAG_SKIP, sc, 0,
669 sysctl_wb_force_test_nmi, "I", "Enable to force watchdog to fire.");
671 /* Register watchdog. */
672 sc->ev_tag = EVENTHANDLER_REGISTER(watchdog_list, wb_watchdog_fn, sc,
676 wb_print_state(sc, "After watchdog attach");
682 wb_detach(device_t dev)
686 sc = device_get_softc(dev);
688 /* Unregister and stop the watchdog if running. */
690 EVENTHANDLER_DEREGISTER(watchdog_list, sc->ev_tag);
691 wb_set_watchdog(sc, 0);
693 /* Disable extended function mode. */
694 (*sc->ext_cfg_exit_f)(sc);
696 /* Cleanup resources. */
697 (void) bus_release_resource(dev, SYS_RES_IOPORT, sc->rid, sc->portres);
699 /* Bus subroutines take care of sysctls already. */
704 static device_method_t wb_methods[] = {
705 /* Device interface */
706 DEVMETHOD(device_probe, wb_probe),
707 DEVMETHOD(device_attach, wb_attach),
708 DEVMETHOD(device_detach, wb_detach),
713 static driver_t wb_isa_driver = {
716 sizeof(struct wb_softc)
719 static devclass_t wb_devclass;
721 DRIVER_MODULE(wb, isa, wb_isa_driver, wb_devclass, NULL, NULL);