2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2010-2011 Monthadar Al Jaberi, TerraNet AB
7 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
25 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
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29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
30 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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38 * Ioctl-related defintions for the Wireless TAP
39 * based on Atheros Wireless LAN controller driver.
42 #ifndef _DEV_WTAP_WTAPIOCTL_H
43 #define _DEV_WTAP_WTAPIOCTL_H
45 #include <sys/param.h>
46 #include <net80211/ieee80211_radiotap.h>
48 #define SIOCGATHSTATS _IOWR('i', 137, struct ifreq)
49 #define SIOCZATHSTATS _IOWR('i', 139, struct ifreq)
51 #define WTAPIOCTLCRT _IOW('W', 1, int)
52 #define WTAPIOCTLDEL _IOW('W', 2, int)
55 u_int32_t ast_watchdog; /* device reset by watchdog */
56 u_int32_t ast_hardware; /* fatal hardware error interrupts */
57 u_int32_t ast_bmiss; /* beacon miss interrupts */
58 u_int32_t ast_bmiss_phantom;/* beacon miss interrupts */
59 u_int32_t ast_bstuck; /* beacon stuck interrupts */
60 u_int32_t ast_rxorn; /* rx overrun interrupts */
61 u_int32_t ast_rxeol; /* rx eol interrupts */
62 u_int32_t ast_txurn; /* tx underrun interrupts */
63 u_int32_t ast_mib; /* mib interrupts */
64 u_int32_t ast_intrcoal; /* interrupts coalesced */
65 u_int32_t ast_tx_packets; /* packet sent on the interface */
66 u_int32_t ast_tx_mgmt; /* management frames transmitted */
67 u_int32_t ast_tx_discard; /* frames discarded prior to assoc */
68 u_int32_t ast_tx_qstop; /* output stopped 'cuz no buffer */
69 u_int32_t ast_tx_encap; /* tx encapsulation failed */
70 u_int32_t ast_tx_nonode; /* tx failed 'cuz no node */
71 u_int32_t ast_tx_nombuf; /* tx failed 'cuz no mbuf */
72 u_int32_t ast_tx_nomcl; /* tx failed 'cuz no cluster */
73 u_int32_t ast_tx_linear; /* tx linearized to cluster */
74 u_int32_t ast_tx_nodata; /* tx discarded empty frame */
75 u_int32_t ast_tx_busdma; /* tx failed for dma resrcs */
76 u_int32_t ast_tx_xretries;/* tx failed 'cuz too many retries */
77 u_int32_t ast_tx_fifoerr; /* tx failed 'cuz FIFO underrun */
78 u_int32_t ast_tx_filtered;/* tx failed 'cuz xmit filtered */
79 u_int32_t ast_tx_shortretry;/* tx on-chip retries (short) */
80 u_int32_t ast_tx_longretry;/* tx on-chip retries (long) */
81 u_int32_t ast_tx_badrate; /* tx failed 'cuz bogus xmit rate */
82 u_int32_t ast_tx_noack; /* tx frames with no ack marked */
83 u_int32_t ast_tx_rts; /* tx frames with rts enabled */
84 u_int32_t ast_tx_cts; /* tx frames with cts enabled */
85 u_int32_t ast_tx_shortpre;/* tx frames with short preamble */
86 u_int32_t ast_tx_altrate; /* tx frames with alternate rate */
87 u_int32_t ast_tx_protect; /* tx frames with protection */
88 u_int32_t ast_tx_ctsburst;/* tx frames with cts and bursting */
89 u_int32_t ast_tx_ctsext; /* tx frames with cts extension */
90 u_int32_t ast_rx_nombuf; /* rx setup failed 'cuz no mbuf */
91 u_int32_t ast_rx_busdma; /* rx setup failed for dma resrcs */
92 u_int32_t ast_rx_orn; /* rx failed 'cuz of desc overrun */
93 u_int32_t ast_rx_crcerr; /* rx failed 'cuz of bad CRC */
94 u_int32_t ast_rx_fifoerr; /* rx failed 'cuz of FIFO overrun */
95 u_int32_t ast_rx_badcrypt;/* rx failed 'cuz decryption */
96 u_int32_t ast_rx_badmic; /* rx failed 'cuz MIC failure */
97 u_int32_t ast_rx_phyerr; /* rx failed 'cuz of PHY err */
98 u_int32_t ast_rx_phy[32]; /* rx PHY error per-code counts */
99 u_int32_t ast_rx_tooshort;/* rx discarded 'cuz frame too short */
100 u_int32_t ast_rx_toobig; /* rx discarded 'cuz frame too large */
101 u_int32_t ast_rx_packets; /* packet recv on the interface */
102 u_int32_t ast_rx_mgt; /* management frames received */
103 u_int32_t ast_rx_ctl; /* rx discarded 'cuz ctl frame */
104 int8_t ast_tx_rssi; /* tx rssi of last ack */
105 int8_t ast_rx_rssi; /* rx rssi from histogram */
106 u_int8_t ast_tx_rate; /* IEEE rate of last unicast tx */
107 u_int32_t ast_be_xmit; /* beacons transmitted */
108 u_int32_t ast_be_nombuf; /* beacon setup failed 'cuz no mbuf */
109 u_int32_t ast_per_cal; /* periodic calibration calls */
110 u_int32_t ast_per_calfail;/* periodic calibration failed */
111 u_int32_t ast_per_rfgain; /* periodic calibration rfgain reset */
112 u_int32_t ast_rate_calls; /* rate control checks */
113 u_int32_t ast_rate_raise; /* rate control raised xmit rate */
114 u_int32_t ast_rate_drop; /* rate control dropped xmit rate */
115 u_int32_t ast_ant_defswitch;/* rx/default antenna switches */
116 u_int32_t ast_ant_txswitch;/* tx antenna switches */
117 u_int32_t ast_ant_rx[8]; /* rx frames with antenna */
118 u_int32_t ast_ant_tx[8]; /* tx frames with antenna */
119 u_int32_t ast_cabq_xmit; /* cabq frames transmitted */
120 u_int32_t ast_cabq_busy; /* cabq found busy */
121 u_int32_t ast_tx_raw; /* tx frames through raw api */
122 u_int32_t ast_ff_txok; /* fast frames tx'd successfully */
123 u_int32_t ast_ff_txerr; /* fast frames tx'd w/ error */
124 u_int32_t ast_ff_rx; /* fast frames rx'd */
125 u_int32_t ast_ff_flush; /* fast frames flushed from staging q */
126 u_int32_t ast_tx_qfull; /* tx dropped 'cuz of queue limit */
127 int8_t ast_rx_noise; /* rx noise floor */
128 u_int32_t ast_tx_nobuf; /* tx dropped 'cuz no ath buffer */
129 u_int32_t ast_tdma_update;/* TDMA slot timing updates */
130 u_int32_t ast_tdma_timers;/* TDMA slot update set beacon timers */
131 u_int32_t ast_tdma_tsf; /* TDMA slot update set TSF */
132 u_int16_t ast_tdma_tsfadjp;/* TDMA slot adjust+ (usec, smoothed)*/
133 u_int16_t ast_tdma_tsfadjm;/* TDMA slot adjust- (usec, smoothed)*/
134 u_int32_t ast_tdma_ack; /* TDMA tx failed 'cuz ACK required */
135 u_int32_t ast_tx_raw_fail;/* raw tx failed 'cuz h/w down */
136 u_int32_t ast_tx_nofrag; /* tx dropped 'cuz no ath frag buffer */
137 u_int32_t ast_be_missed; /* missed beacons */
138 u_int32_t ast_pad[13];
142 * Radio capture format.
144 #define WTAP_RX_RADIOTAP_PRESENT ( \
147 struct wtap_rx_radiotap_header {
148 struct ieee80211_radiotap_header wr_ihdr;
157 u_int32_t wr_chan_flags;
158 u_int16_t wr_chan_freq;
159 u_int8_t wr_chan_ieee;
160 int8_t wr_chan_maxpow;
162 } __packed __aligned(8);
164 #define WTAP_TX_RADIOTAP_PRESENT ( \
167 struct wtap_tx_radiotap_header {
168 struct ieee80211_radiotap_header wt_ihdr;
174 u_int32_t wt_chan_flags;
175 u_int16_t wt_chan_freq;
176 u_int8_t wt_chan_ieee;
177 int8_t wt_chan_maxpow;