2 * Copyright (c) 2017-2018 Ruslan Bukin <br@bsdpad.com>
5 * This software was developed by SRI International and the University of
6 * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
7 * ("CTSRD"), as part of the DARPA CRASH research programme.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 /* ARM PrimeCell DMA Controller (PL330) driver. */
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 #include "opt_platform.h"
37 #include <sys/param.h>
38 #include <sys/endian.h>
39 #include <sys/systm.h>
42 #include <sys/kernel.h>
43 #include <sys/kthread.h>
44 #include <sys/sglist.h>
45 #include <sys/module.h>
47 #include <sys/resource.h>
51 #include <vm/vm_extern.h>
52 #include <vm/vm_kern.h>
55 #include <machine/bus.h>
58 #include <dev/fdt/fdt_common.h>
59 #include <dev/ofw/ofw_bus.h>
60 #include <dev/ofw/ofw_bus_subr.h>
63 #include <dev/xdma/xdma.h>
64 #include <dev/xdma/controller/pl330.h>
72 #define dprintf(fmt, ...) printf(fmt, ##__VA_ARGS__)
74 #define dprintf(fmt, ...)
77 #define READ4(_sc, _reg) \
78 bus_read_4(_sc->res[0], _reg)
79 #define WRITE4(_sc, _reg, _val) \
80 bus_write_4(_sc->res[0], _reg, _val)
82 #define PL330_NCHANNELS 32
83 #define PL330_MAXLOAD 2048
85 struct pl330_channel {
86 struct pl330_softc *sc;
87 xdma_channel_t *xchan;
96 struct pl330_fdt_data {
102 struct resource *res[PL330_NCHANNELS + 1];
103 void *ih[PL330_NCHANNELS];
104 struct pl330_channel channels[PL330_NCHANNELS];
107 static struct resource_spec pl330_spec[] = {
108 { SYS_RES_MEMORY, 0, RF_ACTIVE },
109 { SYS_RES_IRQ, 0, RF_ACTIVE },
110 { SYS_RES_IRQ, 1, RF_ACTIVE | RF_OPTIONAL },
111 { SYS_RES_IRQ, 2, RF_ACTIVE | RF_OPTIONAL },
112 { SYS_RES_IRQ, 3, RF_ACTIVE | RF_OPTIONAL },
113 { SYS_RES_IRQ, 4, RF_ACTIVE | RF_OPTIONAL },
114 { SYS_RES_IRQ, 5, RF_ACTIVE | RF_OPTIONAL },
115 { SYS_RES_IRQ, 6, RF_ACTIVE | RF_OPTIONAL },
116 { SYS_RES_IRQ, 7, RF_ACTIVE | RF_OPTIONAL },
117 { SYS_RES_IRQ, 8, RF_ACTIVE | RF_OPTIONAL },
118 { SYS_RES_IRQ, 9, RF_ACTIVE | RF_OPTIONAL },
119 { SYS_RES_IRQ, 10, RF_ACTIVE | RF_OPTIONAL },
120 { SYS_RES_IRQ, 11, RF_ACTIVE | RF_OPTIONAL },
121 { SYS_RES_IRQ, 12, RF_ACTIVE | RF_OPTIONAL },
122 { SYS_RES_IRQ, 13, RF_ACTIVE | RF_OPTIONAL },
123 { SYS_RES_IRQ, 14, RF_ACTIVE | RF_OPTIONAL },
124 { SYS_RES_IRQ, 15, RF_ACTIVE | RF_OPTIONAL },
125 { SYS_RES_IRQ, 16, RF_ACTIVE | RF_OPTIONAL },
126 { SYS_RES_IRQ, 17, RF_ACTIVE | RF_OPTIONAL },
127 { SYS_RES_IRQ, 18, RF_ACTIVE | RF_OPTIONAL },
128 { SYS_RES_IRQ, 19, RF_ACTIVE | RF_OPTIONAL },
129 { SYS_RES_IRQ, 20, RF_ACTIVE | RF_OPTIONAL },
130 { SYS_RES_IRQ, 21, RF_ACTIVE | RF_OPTIONAL },
131 { SYS_RES_IRQ, 22, RF_ACTIVE | RF_OPTIONAL },
132 { SYS_RES_IRQ, 23, RF_ACTIVE | RF_OPTIONAL },
133 { SYS_RES_IRQ, 24, RF_ACTIVE | RF_OPTIONAL },
134 { SYS_RES_IRQ, 25, RF_ACTIVE | RF_OPTIONAL },
135 { SYS_RES_IRQ, 26, RF_ACTIVE | RF_OPTIONAL },
136 { SYS_RES_IRQ, 27, RF_ACTIVE | RF_OPTIONAL },
137 { SYS_RES_IRQ, 28, RF_ACTIVE | RF_OPTIONAL },
138 { SYS_RES_IRQ, 29, RF_ACTIVE | RF_OPTIONAL },
139 { SYS_RES_IRQ, 30, RF_ACTIVE | RF_OPTIONAL },
140 { SYS_RES_IRQ, 31, RF_ACTIVE | RF_OPTIONAL },
144 #define HWTYPE_NONE 0
147 static struct ofw_compat_data compat_data[] = {
148 { "arm,pl330", HWTYPE_STD },
149 { NULL, HWTYPE_NONE },
153 pl330_intr(void *arg)
155 xdma_transfer_status_t status;
156 struct xdma_transfer_status st;
157 struct pl330_channel *chan;
158 struct xdma_channel *xchan;
159 struct pl330_softc *sc;
166 pending = READ4(sc, INTMIS);
168 dprintf("%s: 0x%x, LC0 %x, SAR %x DAR %x\n",
169 __func__, pending, READ4(sc, LC0(0)),
170 READ4(sc, SAR(0)), READ4(sc, DAR(0)));
172 WRITE4(sc, INTCLR, pending);
174 for (c = 0; c < PL330_NCHANNELS; c++) {
175 if ((pending & (1 << c)) == 0) {
178 chan = &sc->channels[c];
182 for (i = 0; i < chan->enqueued; i++) {
183 xchan_seg_done(xchan, &st);
186 /* Accept new requests. */
187 chan->capacity = PL330_MAXLOAD;
189 /* Finish operation */
191 status.transferred = 0;
192 xdma_callback(chan->xchan, &status);
197 emit_mov(uint8_t *buf, uint32_t reg, uint32_t val)
211 emit_lp(uint8_t *buf, uint8_t idx, uint32_t iter)
215 return (0); /* We have two loops only. */
218 buf[0] |= (idx << 1);
219 buf[1] = (iter - 1) & 0xff;
225 emit_lpend(uint8_t *buf, uint8_t idx,
226 uint8_t burst, uint8_t jump_addr_relative)
230 buf[0] |= DMALPEND_NF;
231 buf[0] |= (idx << 2);
233 buf[0] |= (1 << 1) | (1 << 0);
235 buf[0] |= (0 << 1) | (1 << 0);
236 buf[1] = jump_addr_relative;
242 emit_ld(uint8_t *buf, uint8_t burst)
247 buf[0] |= (1 << 1) | (1 << 0);
249 buf[0] |= (0 << 1) | (1 << 0);
255 emit_st(uint8_t *buf, uint8_t burst)
260 buf[0] |= (1 << 1) | (1 << 0);
262 buf[0] |= (0 << 1) | (1 << 0);
268 emit_end(uint8_t *buf)
277 emit_sev(uint8_t *buf, uint32_t ev)
287 emit_wfp(uint8_t *buf, uint32_t p_id)
292 buf[1] = (p_id << 3);
298 emit_go(uint8_t *buf, uint32_t chan_id,
299 uint32_t addr, uint8_t non_secure)
303 buf[0] |= (non_secure << 1);
315 pl330_probe(device_t dev)
319 if (!ofw_bus_status_okay(dev))
322 hwtype = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
323 if (hwtype == HWTYPE_NONE)
326 device_set_desc(dev, "ARM PrimeCell DMA Controller (PL330)");
328 return (BUS_PROBE_DEFAULT);
332 pl330_attach(device_t dev)
334 struct pl330_softc *sc;
335 phandle_t xref, node;
339 sc = device_get_softc(dev);
342 if (bus_alloc_resources(dev, pl330_spec, sc->res)) {
343 device_printf(dev, "could not allocate resources for device\n");
347 /* Setup interrupt handler */
348 for (i = 0; i < PL330_NCHANNELS; i++) {
349 if (sc->res[i + 1] == NULL)
351 err = bus_setup_intr(dev, sc->res[i + 1], INTR_TYPE_MISC | INTR_MPSAFE,
352 NULL, pl330_intr, sc, sc->ih[i]);
354 device_printf(dev, "Unable to alloc interrupt resource.\n");
359 node = ofw_bus_get_node(dev);
360 xref = OF_xref_from_node(node);
361 OF_device_register_xref(xref, dev);
367 pl330_detach(device_t dev)
369 struct pl330_softc *sc;
371 sc = device_get_softc(dev);
377 pl330_channel_alloc(device_t dev, struct xdma_channel *xchan)
379 struct pl330_channel *chan;
380 struct pl330_softc *sc;
383 sc = device_get_softc(dev);
385 for (i = 0; i < PL330_NCHANNELS; i++) {
386 chan = &sc->channels[i];
387 if (chan->used == 0) {
389 xchan->chan = (void *)chan;
390 xchan->caps |= XCHAN_CAP_BUSDMA;
395 chan->ibuf = (void *)kmem_alloc_contig(kernel_arena,
396 PAGE_SIZE*8, M_ZERO, 0, ~0, PAGE_SIZE, 0,
397 VM_MEMATTR_UNCACHEABLE);
398 chan->ibuf_phys = vtophys(chan->ibuf);
408 pl330_channel_free(device_t dev, struct xdma_channel *xchan)
410 struct pl330_channel *chan;
411 struct pl330_softc *sc;
413 sc = device_get_softc(dev);
415 chan = (struct pl330_channel *)xchan->chan;
422 pl330_channel_capacity(device_t dev, xdma_channel_t *xchan,
425 struct pl330_channel *chan;
427 chan = (struct pl330_channel *)xchan->chan;
429 *capacity = chan->capacity;
435 pl330_ccr_port_width(struct xdma_sglist *sg, uint32_t *addr)
441 switch (sg->src_width) {
443 reg |= CCR_SRC_BURST_SIZE_1;
446 reg |= CCR_SRC_BURST_SIZE_2;
449 reg |= CCR_SRC_BURST_SIZE_4;
455 switch (sg->dst_width) {
457 reg |= CCR_DST_BURST_SIZE_1;
460 reg |= CCR_DST_BURST_SIZE_2;
463 reg |= CCR_DST_BURST_SIZE_4;
475 pl330_channel_submit_sg(device_t dev, struct xdma_channel *xchan,
476 struct xdma_sglist *sg, uint32_t sg_n)
478 struct pl330_fdt_data *data;
479 xdma_controller_t *xdma;
480 struct pl330_channel *chan;
481 struct pl330_softc *sc;
482 uint32_t src_addr_lo;
483 uint32_t dst_addr_lo;
490 uint8_t offs0, offs1;
494 sc = device_get_softc(dev);
497 data = (struct pl330_fdt_data *)xdma->data;
499 chan = (struct pl330_channel *)xchan->chan;
502 dprintf("%s: chan->index %d\n", __func__, chan->index);
506 for (i = 0; i < sg_n; i++) {
507 if (sg[i].direction == XDMA_DEV_TO_MEM)
511 reg |= (CCR_DST_PROT_PRIV);
514 err = pl330_ccr_port_width(&sg[i], ®);
518 offs += emit_mov(&chan->ibuf[offs], R_CCR, reg);
520 src_addr_lo = (uint32_t)sg[i].src_addr;
521 dst_addr_lo = (uint32_t)sg[i].dst_addr;
522 len = (uint32_t)sg[i].len;
524 dprintf("%s: src %x dst %x len %d periph_id %d\n", __func__,
525 src_addr_lo, dst_addr_lo, len, data->periph_id);
527 offs += emit_mov(&ibuf[offs], R_SAR, src_addr_lo);
528 offs += emit_mov(&ibuf[offs], R_DAR, dst_addr_lo);
530 if (sg[i].src_width != sg[i].dst_width)
531 return (-1); /* Not supported. */
533 cnt = (len / sg[i].src_width);
535 offs += emit_lp(&ibuf[offs], 0, cnt / 128);
537 offs += emit_lp(&ibuf[offs], 1, 128);
540 offs += emit_lp(&ibuf[offs], 0, cnt);
543 offs += emit_wfp(&ibuf[offs], data->periph_id);
544 offs += emit_ld(&ibuf[offs], 1);
545 offs += emit_st(&ibuf[offs], 1);
548 offs += emit_lpend(&ibuf[offs], 1, 1, (offs - offs1));
550 offs += emit_lpend(&ibuf[offs], 0, 1, (offs - offs0));
553 offs += emit_sev(&ibuf[offs], chan->index);
554 offs += emit_end(&ibuf[offs]);
556 emit_go(dbuf, chan->index, chan->ibuf_phys, 0);
558 reg = (dbuf[1] << 24) | (dbuf[0] << 16);
559 WRITE4(sc, DBGINST0, reg);
560 reg = (dbuf[5] << 24) | (dbuf[4] << 16) | (dbuf[3] << 8) | dbuf[2];
561 WRITE4(sc, DBGINST1, reg);
563 WRITE4(sc, INTCLR, 0xffffffff);
564 WRITE4(sc, INTEN, (1 << chan->index));
566 chan->enqueued = sg_n;
569 /* Start operation */
570 WRITE4(sc, DBGCMD, 0);
576 pl330_channel_prep_sg(device_t dev, struct xdma_channel *xchan)
578 struct pl330_channel *chan;
579 struct pl330_softc *sc;
581 sc = device_get_softc(dev);
583 dprintf("%s(%d)\n", __func__, device_get_unit(dev));
585 chan = (struct pl330_channel *)xchan->chan;
586 chan->capacity = PL330_MAXLOAD;
592 pl330_channel_control(device_t dev, xdma_channel_t *xchan, int cmd)
594 struct pl330_channel *chan;
595 struct pl330_softc *sc;
597 sc = device_get_softc(dev);
599 chan = (struct pl330_channel *)xchan->chan;
603 case XDMA_CMD_TERMINATE:
605 /* TODO: implement me */
614 pl330_ofw_md_data(device_t dev, pcell_t *cells, int ncells, void **ptr)
616 struct pl330_fdt_data *data;
621 data = malloc(sizeof(struct pl330_fdt_data),
622 M_DEVBUF, (M_WAITOK | M_ZERO));
623 data->periph_id = cells[0];
631 static device_method_t pl330_methods[] = {
632 /* Device interface */
633 DEVMETHOD(device_probe, pl330_probe),
634 DEVMETHOD(device_attach, pl330_attach),
635 DEVMETHOD(device_detach, pl330_detach),
638 DEVMETHOD(xdma_channel_alloc, pl330_channel_alloc),
639 DEVMETHOD(xdma_channel_free, pl330_channel_free),
640 DEVMETHOD(xdma_channel_control, pl330_channel_control),
642 /* xDMA SG Interface */
643 DEVMETHOD(xdma_channel_capacity, pl330_channel_capacity),
644 DEVMETHOD(xdma_channel_prep_sg, pl330_channel_prep_sg),
645 DEVMETHOD(xdma_channel_submit_sg, pl330_channel_submit_sg),
648 DEVMETHOD(xdma_ofw_md_data, pl330_ofw_md_data),
654 static driver_t pl330_driver = {
657 sizeof(struct pl330_softc),
660 static devclass_t pl330_devclass;
662 EARLY_DRIVER_MODULE(pl330, simplebus, pl330_driver, pl330_devclass, 0, 0,
663 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE);