2 * Copyright (c) 2016 Ruslan Bukin <br@bsdpad.com>
5 * This software was developed by SRI International and the University of
6 * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
7 * ("CTSRD"), as part of the DARPA CRASH research programme.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 #ifndef _DEV_EXTRES_XDMA_H_
34 #define _DEV_EXTRES_XDMA_H_
43 enum xdma_operation_type {
53 XDMA_CMD_TERMINATE_ALL,
56 struct xdma_controller {
57 device_t dev; /* DMA consumer device_t. */
58 device_t dma_dev; /* A real DMA device_t. */
59 void *data; /* OFW MD part. */
61 /* List of virtual channels allocated. */
62 TAILQ_HEAD(xdma_channel_list, xdma_channel) channels;
65 typedef struct xdma_controller xdma_controller_t;
67 struct xdma_channel_config {
68 enum xdma_direction direction;
69 uintptr_t src_addr; /* Physical address. */
70 uintptr_t dst_addr; /* Physical address. */
71 int block_len; /* In bytes. */
72 int block_num; /* Count of blocks. */
73 int src_width; /* In bytes. */
74 int dst_width; /* In bytes. */
77 typedef struct xdma_channel_config xdma_config_t;
79 struct xdma_descriptor {
84 typedef struct xdma_descriptor xdma_descriptor_t;
87 xdma_controller_t *xdma;
91 #define XCHAN_DESC_ALLOCATED (1 << 0)
92 #define XCHAN_CONFIGURED (1 << 1)
93 #define XCHAN_TYPE_CYCLIC (1 << 2)
94 #define XCHAN_TYPE_MEMCPY (1 << 3)
96 /* A real hardware driver channel. */
99 /* Interrupt handlers. */
100 TAILQ_HEAD(, xdma_intr_handler) ie_handlers;
103 bus_dma_tag_t dma_tag;
104 bus_dmamap_t dma_map;
106 xdma_descriptor_t *descs_phys;
111 TAILQ_ENTRY(xdma_channel) xchan_next;
114 typedef struct xdma_channel xdma_channel_t;
116 /* xDMA controller alloc/free */
117 xdma_controller_t *xdma_ofw_get(device_t dev, const char *prop);
118 int xdma_put(xdma_controller_t *xdma);
120 xdma_channel_t * xdma_channel_alloc(xdma_controller_t *);
121 int xdma_channel_free(xdma_channel_t *);
123 int xdma_prep_cyclic(xdma_channel_t *, enum xdma_direction,
124 uintptr_t, uintptr_t, int, int, int, int);
125 int xdma_prep_memcpy(xdma_channel_t *, uintptr_t, uintptr_t, size_t len);
126 int xdma_desc_alloc(xdma_channel_t *, uint32_t, uint32_t);
127 int xdma_desc_free(xdma_channel_t *xchan);
129 /* Channel Control */
130 int xdma_begin(xdma_channel_t *xchan);
131 int xdma_pause(xdma_channel_t *xchan);
132 int xdma_terminate(xdma_channel_t *xchan);
134 /* Interrupt callback */
135 int xdma_setup_intr(xdma_channel_t *xchan, int (*cb)(void *), void *arg, void **);
136 int xdma_teardown_intr(xdma_channel_t *xchan, struct xdma_intr_handler *ih);
137 int xdma_teardown_all_intr(xdma_channel_t *xchan);
138 int xdma_callback(struct xdma_channel *xchan);
139 void xdma_assert_locked(void);
141 struct xdma_intr_handler {
145 TAILQ_ENTRY(xdma_intr_handler) ih_next;
148 #endif /* !_DEV_EXTRES_XDMA_H_ */