2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2019 Ruslan Bukin <br@bsdpad.com>
6 * This software was developed by SRI International and the University of
7 * Cambridge Computer Laboratory (Department of Computer Science and
8 * Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
9 * DARPA SSITH research programme.
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 #ifndef _DEV_XILINX_AXIDMA_H_
36 #define _DEV_XILINX_AXIDMA_H_
38 #define AXI_DMACR(n) (0x00 + 0x30 * (n)) /* DMA Control register */
39 #define DMACR_RS (1 << 0) /* Run / Stop. */
40 #define DMACR_RESET (1 << 2) /* Soft reset the AXI DMA core. */
41 #define DMACR_IOC_IRQEN (1 << 12) /* Interrupt on Complete (IOC) Interrupt Enable. */
42 #define DMACR_DLY_IRQEN (1 << 13) /* Interrupt on Delay Timer Interrupt Enable. */
43 #define DMACR_ERR_IRQEN (1 << 14) /* Interrupt on Error Interrupt Enable. */
44 #define AXI_DMASR(n) (0x04 + 0x30 * (n)) /* DMA Status register */
45 #define DMASR_HALTED (1 << 0)
46 #define DMASR_IDLE (1 << 1)
47 #define DMASR_SGINCLD (1 << 3) /* Scatter Gather Enabled */
48 #define DMASR_DMAINTERR (1 << 4) /* DMA Internal Error. */
49 #define DMASR_DMASLVERR (1 << 5) /* DMA Slave Error. */
50 #define DMASR_DMADECOREERR (1 << 6) /* Decode Error. */
51 #define DMASR_SGINTERR (1 << 8) /* Scatter Gather Internal Error. */
52 #define DMASR_SGSLVERR (1 << 9) /* Scatter Gather Slave Error. */
53 #define DMASR_SGDECERR (1 << 10) /* Scatter Gather Decode Error. */
54 #define DMASR_IOC_IRQ (1 << 12) /* Interrupt on Complete. */
55 #define DMASR_DLY_IRQ (1 << 13) /* Interrupt on Delay. */
56 #define DMASR_ERR_IRQ (1 << 14) /* Interrupt on Error. */
57 #define AXI_CURDESC(n) (0x08 + 0x30 * (n)) /* Current Descriptor Pointer. Lower 32 bits of the address. */
58 #define AXI_CURDESC_MSB(n) (0x0C + 0x30 * (n)) /* Current Descriptor Pointer. Upper 32 bits of address. */
59 #define AXI_TAILDESC(n) (0x10 + 0x30 * (n)) /* Tail Descriptor Pointer. Lower 32 bits. */
60 #define AXI_TAILDESC_MSB(n) (0x14 + 0x30 * (n)) /* Tail Descriptor Pointer. Upper 32 bits of address. */
61 #define AXI_SG_CTL 0x2C /* Scatter/Gather User and Cache */
63 #define AXIDMA_NCHANNELS 2
64 #define AXIDMA_DESCS_NUM 512
65 #define AXIDMA_TX_CHAN 0
66 #define AXIDMA_RX_CHAN 1
76 #define BD_CONTROL_TXSOF (1 << 27) /* Start of Frame. */
77 #define BD_CONTROL_TXEOF (1 << 26) /* End of Frame. */
78 #define BD_CONTROL_LEN_S 0 /* Buffer Length. */
79 #define BD_CONTROL_LEN_M (0x3ffffff << BD_CONTROL_LEN_S)
81 #define BD_STATUS_CMPLT (1 << 31)
82 #define BD_STATUS_TRANSFERRED_S 0
83 #define BD_STATUS_TRANSFERRED_M (0x7fffff << BD_STATUS_TRANSFERRED_S)
92 struct axidma_fdt_data {
96 #endif /* !_DEV_XILINX_AXIDMA_H_ */