2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2019 Ruslan Bukin <br@bsdpad.com>
6 * This software was developed by SRI International and the University of
7 * Cambridge Computer Laboratory (Department of Computer Science and
8 * Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
9 * DARPA SSITH research programme.
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 #include <sys/param.h>
37 #include <sys/systm.h>
39 #include <sys/kernel.h>
41 #include <sys/malloc.h>
43 #include <sys/module.h>
44 #include <sys/mutex.h>
46 #include <sys/socket.h>
47 #include <sys/sockio.h>
51 #include <net/ethernet.h>
52 #include <net/if_dl.h>
53 #include <net/if_media.h>
54 #include <net/if_types.h>
55 #include <net/if_var.h>
57 #include <machine/bus.h>
59 #include <dev/mii/mii.h>
60 #include <dev/mii/miivar.h>
61 #include <dev/mii/tiphy.h>
62 #include <dev/ofw/ofw_bus.h>
63 #include <dev/ofw/ofw_bus_subr.h>
64 #include <dev/xilinx/if_xaereg.h>
65 #include <dev/xilinx/if_xaevar.h>
67 #include "miibus_if.h"
69 #define READ4(_sc, _reg) \
70 bus_read_4((_sc)->res[0], _reg)
71 #define WRITE4(_sc, _reg, _val) \
72 bus_write_4((_sc)->res[0], _reg, _val)
74 #define READ8(_sc, _reg) \
75 bus_read_8((_sc)->res[0], _reg)
76 #define WRITE8(_sc, _reg, _val) \
77 bus_write_8((_sc)->res[0], _reg, _val)
79 #define XAE_LOCK(sc) mtx_lock(&(sc)->mtx)
80 #define XAE_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
81 #define XAE_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED)
82 #define XAE_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED)
88 #define dprintf(fmt, ...) printf(fmt, ##__VA_ARGS__)
90 #define dprintf(fmt, ...)
93 #define RX_QUEUE_SIZE 64
94 #define TX_QUEUE_SIZE 64
95 #define NUM_RX_MBUF 16
96 #define BUFRING_SIZE 8192
97 #define MDIO_CLK_DIV_DEFAULT 29
99 #define PHY1_RD(sc, _r) \
100 xae_miibus_read_reg(sc->dev, 1, _r)
101 #define PHY1_WR(sc, _r, _v) \
102 xae_miibus_write_reg(sc->dev, 1, _r, _v)
104 #define PHY_RD(sc, _r) \
105 xae_miibus_read_reg(sc->dev, sc->phy_addr, _r)
106 #define PHY_WR(sc, _r, _v) \
107 xae_miibus_write_reg(sc->dev, sc->phy_addr, _r, _v)
109 /* Use this macro to access regs > 0x1f */
110 #define WRITE_TI_EREG(sc, reg, data) { \
111 PHY_WR(sc, MII_MMDACR, MMDACR_DADDRMASK); \
112 PHY_WR(sc, MII_MMDAADR, reg); \
113 PHY_WR(sc, MII_MMDACR, MMDACR_DADDRMASK | MMDACR_FN_DATANPI); \
114 PHY_WR(sc, MII_MMDAADR, data); \
117 /* Not documented, Xilinx VCU118 workaround */
118 #define CFG4_SGMII_TMR 0x160 /* bits 8:7 MUST be '10' */
119 #define DP83867_SGMIICTL1 0xD3 /* not documented register */
120 #define SGMIICTL1_SGMII_6W (1 << 14) /* no idea what it is */
122 static struct resource_spec xae_spec[] = {
123 { SYS_RES_MEMORY, 0, RF_ACTIVE },
124 { SYS_RES_IRQ, 0, RF_ACTIVE },
128 static void xae_stop_locked(struct xae_softc *sc);
129 static void xae_setup_rxfilter(struct xae_softc *sc);
132 xae_rx_enqueue(struct xae_softc *sc, uint32_t n)
137 for (i = 0; i < n; i++) {
138 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
140 device_printf(sc->dev,
141 "%s: Can't alloc rx mbuf\n", __func__);
145 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size;
146 xdma_enqueue_mbuf(sc->xchan_rx, &m, 0, 4, 4, XDMA_DEV_TO_MEM);
153 xae_get_phyaddr(phandle_t node, int *phy_addr)
156 pcell_t phy_handle, phy_reg;
158 if (OF_getencprop(node, "phy-handle", (void *)&phy_handle,
159 sizeof(phy_handle)) <= 0)
162 phy_node = OF_node_from_xref(phy_handle);
164 if (OF_getencprop(phy_node, "reg", (void *)&phy_reg,
165 sizeof(phy_reg)) <= 0)
174 xae_xdma_tx_intr(void *arg, xdma_transfer_status_t *status)
176 xdma_transfer_status_t st;
177 struct xae_softc *sc;
189 err = xdma_dequeue_mbuf(sc->xchan_tx, &m, &st);
195 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
201 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
209 xae_xdma_rx_intr(void *arg, xdma_transfer_status_t *status)
211 xdma_transfer_status_t st;
212 struct xae_softc *sc;
216 uint32_t cnt_processed;
220 dprintf("%s\n", __func__);
228 err = xdma_dequeue_mbuf(sc->xchan_rx, &m, &st);
235 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
240 m->m_pkthdr.len = m->m_len = st.transferred;
241 m->m_pkthdr.rcvif = ifp;
243 (*ifp->if_input)(ifp, m);
247 xae_rx_enqueue(sc, cnt_processed);
255 xae_qflush(struct ifnet *ifp)
257 struct xae_softc *sc;
263 xae_transmit_locked(struct ifnet *ifp)
265 struct xae_softc *sc;
271 dprintf("%s\n", __func__);
278 while ((m = drbr_peek(ifp, br)) != NULL) {
279 error = xdma_enqueue_mbuf(sc->xchan_tx,
280 &m, 0, 4, 4, XDMA_MEM_TO_DEV);
282 /* No space in request queue available yet. */
283 drbr_putback(ifp, br, m);
287 drbr_advance(ifp, br);
291 /* If anyone is interested give them a copy. */
292 ETHER_BPF_MTAP(ifp, m);
296 xdma_queue_submit(sc->xchan_tx);
302 xae_transmit(struct ifnet *ifp, struct mbuf *m)
304 struct xae_softc *sc;
307 dprintf("%s\n", __func__);
313 error = drbr_enqueue(ifp, sc->br, m);
319 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
325 if (!sc->link_is_up) {
330 error = xae_transmit_locked(ifp);
338 xae_stop_locked(struct xae_softc *sc)
343 XAE_ASSERT_LOCKED(sc);
346 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
348 callout_stop(&sc->xae_callout);
350 /* Stop the transmitter */
351 reg = READ4(sc, XAE_TC);
353 WRITE4(sc, XAE_TC, reg);
355 /* Stop the receiver. */
356 reg = READ4(sc, XAE_RCW1);
358 WRITE4(sc, XAE_RCW1, reg);
362 xae_stat(struct xae_softc *sc, int counter_id)
367 KASSERT(counter_id < XAE_MAX_COUNTERS,
368 ("counter %d is out of range", counter_id));
370 new = READ8(sc, XAE_STATCNT(counter_id));
371 old = sc->counters[counter_id];
376 delta = UINT64_MAX - old + new;
377 sc->counters[counter_id] = new;
383 xae_harvest_stats(struct xae_softc *sc)
389 if_inc_counter(ifp, IFCOUNTER_IPACKETS, xae_stat(sc, RX_GOOD_FRAMES));
390 if_inc_counter(ifp, IFCOUNTER_IMCASTS, xae_stat(sc, RX_GOOD_MCASTS));
391 if_inc_counter(ifp, IFCOUNTER_IERRORS,
392 xae_stat(sc, RX_FRAME_CHECK_SEQ_ERROR) +
393 xae_stat(sc, RX_LEN_OUT_OF_RANGE) +
394 xae_stat(sc, RX_ALIGNMENT_ERRORS));
396 if_inc_counter(ifp, IFCOUNTER_OBYTES, xae_stat(sc, TX_BYTES));
397 if_inc_counter(ifp, IFCOUNTER_OPACKETS, xae_stat(sc, TX_GOOD_FRAMES));
398 if_inc_counter(ifp, IFCOUNTER_OMCASTS, xae_stat(sc, TX_GOOD_MCASTS));
399 if_inc_counter(ifp, IFCOUNTER_OERRORS,
400 xae_stat(sc, TX_GOOD_UNDERRUN_ERRORS));
402 if_inc_counter(ifp, IFCOUNTER_COLLISIONS,
403 xae_stat(sc, TX_SINGLE_COLLISION_FRAMES) +
404 xae_stat(sc, TX_MULTI_COLLISION_FRAMES) +
405 xae_stat(sc, TX_LATE_COLLISIONS) +
406 xae_stat(sc, TX_EXCESS_COLLISIONS));
412 struct xae_softc *sc;
418 XAE_ASSERT_LOCKED(sc);
422 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
425 /* Gather stats from hardware counters. */
426 xae_harvest_stats(sc);
428 /* Check the media status. */
429 link_was_up = sc->link_is_up;
430 mii_tick(sc->mii_softc);
431 if (sc->link_is_up && !link_was_up)
432 xae_transmit_locked(sc->ifp);
434 /* Schedule another check one second from now. */
435 callout_reset(&sc->xae_callout, hz, xae_tick, sc);
439 xae_init_locked(struct xae_softc *sc)
443 XAE_ASSERT_LOCKED(sc);
446 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
449 ifp->if_drv_flags |= IFF_DRV_RUNNING;
451 xae_setup_rxfilter(sc);
453 /* Enable the transmitter */
454 WRITE4(sc, XAE_TC, TC_TX);
456 /* Enable the receiver. */
457 WRITE4(sc, XAE_RCW1, RCW1_RX);
460 * Call mii_mediachg() which will call back into xae_miibus_statchg()
461 * to set up the remaining config registers based on current media.
463 mii_mediachg(sc->mii_softc);
464 callout_reset(&sc->xae_callout, hz, xae_tick, sc);
470 struct xae_softc *sc;
480 xae_media_status(struct ifnet * ifp, struct ifmediareq *ifmr)
482 struct xae_softc *sc;
483 struct mii_data *mii;
490 ifmr->ifm_active = mii->mii_media_active;
491 ifmr->ifm_status = mii->mii_media_status;
496 xae_media_change_locked(struct xae_softc *sc)
499 return (mii_mediachg(sc->mii_softc));
503 xae_media_change(struct ifnet * ifp)
505 struct xae_softc *sc;
511 error = xae_media_change_locked(sc);
518 xae_setup_rxfilter(struct xae_softc *sc)
520 struct ifmultiaddr *ifma;
526 XAE_ASSERT_LOCKED(sc);
531 * Set the multicast (group) filter hash.
533 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) {
534 reg = READ4(sc, XAE_FFC);
536 WRITE4(sc, XAE_FFC, reg);
538 reg = READ4(sc, XAE_FFC);
540 WRITE4(sc, XAE_FFC, reg);
545 CK_STAILQ_FOREACH(ifma, &sc->ifp->if_multiaddrs, ifma_link) {
546 if (ifma->ifma_addr->sa_family != AF_LINK)
549 if (i >= XAE_MULTICAST_TABLE_SIZE)
552 ma = LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
554 reg = READ4(sc, XAE_FFC) & 0xffffff00;
556 WRITE4(sc, XAE_FFC, reg);
560 reg |= (ma[2] << 16);
561 reg |= (ma[3] << 24);
562 WRITE4(sc, XAE_FFV(0), reg);
566 WRITE4(sc, XAE_FFV(1), reg);
568 if_maddr_runlock(ifp);
572 * Set the primary address.
574 reg = sc->macaddr[0];
575 reg |= (sc->macaddr[1] << 8);
576 reg |= (sc->macaddr[2] << 16);
577 reg |= (sc->macaddr[3] << 24);
578 WRITE4(sc, XAE_UAW0, reg);
580 reg = sc->macaddr[4];
581 reg |= (sc->macaddr[5] << 8);
582 WRITE4(sc, XAE_UAW1, reg);
586 xae_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
588 struct xae_softc *sc;
589 struct mii_data *mii;
594 ifr = (struct ifreq *)data;
600 if (ifp->if_flags & IFF_UP) {
601 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
602 if ((ifp->if_flags ^ sc->if_flags) &
603 (IFF_PROMISC | IFF_ALLMULTI))
604 xae_setup_rxfilter(sc);
606 if (!sc->is_detaching)
610 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
613 sc->if_flags = ifp->if_flags;
618 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
620 xae_setup_rxfilter(sc);
627 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
630 mask = ifp->if_capenable ^ ifr->ifr_reqcap;
631 if (mask & IFCAP_VLAN_MTU) {
632 /* No work to do except acknowledge the change took */
633 ifp->if_capenable ^= IFCAP_VLAN_MTU;
638 error = ether_ioctl(ifp, cmd, data);
652 xae_get_hwaddr(struct xae_softc *sc, uint8_t *hwaddr)
657 node = ofw_bus_get_node(sc->dev);
659 /* Check if there is property */
660 if ((len = OF_getproplen(node, "local-mac-address")) <= 0)
663 if (len != ETHER_ADDR_LEN)
666 OF_getprop(node, "local-mac-address", hwaddr,
673 mdio_wait(struct xae_softc *sc)
681 reg = READ4(sc, XAE_MDIO_CTRL);
682 if (reg & MDIO_CTRL_READY)
688 printf("Failed to get MDIO ready\n");
696 xae_miibus_read_reg(device_t dev, int phy, int reg)
698 struct xae_softc *sc;
702 sc = device_get_softc(dev);
707 mii = MDIO_CTRL_TX_OP_READ | MDIO_CTRL_INITIATE;
708 mii |= (reg << MDIO_TX_REGAD_S);
709 mii |= (phy << MDIO_TX_PHYAD_S);
711 WRITE4(sc, XAE_MDIO_CTRL, mii);
716 rv = READ4(sc, XAE_MDIO_READ);
722 xae_miibus_write_reg(device_t dev, int phy, int reg, int val)
724 struct xae_softc *sc;
727 sc = device_get_softc(dev);
732 mii = MDIO_CTRL_TX_OP_WRITE | MDIO_CTRL_INITIATE;
733 mii |= (reg << MDIO_TX_REGAD_S);
734 mii |= (phy << MDIO_TX_PHYAD_S);
736 WRITE4(sc, XAE_MDIO_WRITE, val);
737 WRITE4(sc, XAE_MDIO_CTRL, mii);
746 xae_phy_fixup(struct xae_softc *sc)
754 WRITE_TI_EREG(sc, DP83867_SGMIICTL1, SGMIICTL1_SGMII_6W);
755 PHY_WR(sc, DP83867_PHYCR, PHYCR_SGMII_EN);
757 reg = PHY_RD(sc, DP83867_CFG2);
758 reg &= ~CFG2_SPEED_OPT_ATTEMPT_CNT_M;
759 reg |= (CFG2_SPEED_OPT_ATTEMPT_CNT_4);
760 reg |= CFG2_INTERRUPT_POLARITY;
761 reg |= CFG2_SPEED_OPT_ENHANCED_EN;
762 reg |= CFG2_SPEED_OPT_10M_EN;
763 PHY_WR(sc, DP83867_CFG2, reg);
765 WRITE_TI_EREG(sc, DP83867_CFG4, CFG4_SGMII_TMR);
767 BMCR_AUTOEN | BMCR_FDX | BMCR_SPEED1 | BMCR_RESET);
768 } while (PHY1_RD(sc, MII_BMCR) == 0x0ffff);
771 PHY1_WR(sc, MII_BMCR,
772 BMCR_AUTOEN | BMCR_FDX | BMCR_SPEED1 | BMCR_STARTNEG);
774 } while ((PHY1_RD(sc, MII_BMSR) & BMSR_ACOMP) == 0);
778 setup_xdma(struct xae_softc *sc)
786 /* Get xDMA controller */
787 sc->xdma_tx = xdma_ofw_get(sc->dev, "tx");
788 if (sc->xdma_tx == NULL) {
789 device_printf(dev, "Could not find DMA controller.\n");
793 sc->xdma_rx = xdma_ofw_get(sc->dev, "rx");
794 if (sc->xdma_rx == NULL) {
795 device_printf(dev, "Could not find DMA controller.\n");
799 /* Alloc xDMA TX virtual channel. */
800 sc->xchan_tx = xdma_channel_alloc(sc->xdma_tx, 0);
801 if (sc->xchan_tx == NULL) {
802 device_printf(dev, "Can't alloc virtual DMA TX channel.\n");
806 /* Setup interrupt handler. */
807 error = xdma_setup_intr(sc->xchan_tx,
808 xae_xdma_tx_intr, sc, &sc->ih_tx);
810 device_printf(sc->dev,
811 "Can't setup xDMA TX interrupt handler.\n");
815 /* Alloc xDMA RX virtual channel. */
816 sc->xchan_rx = xdma_channel_alloc(sc->xdma_rx, 0);
817 if (sc->xchan_rx == NULL) {
818 device_printf(dev, "Can't alloc virtual DMA RX channel.\n");
822 /* Setup interrupt handler. */
823 error = xdma_setup_intr(sc->xchan_rx,
824 xae_xdma_rx_intr, sc, &sc->ih_rx);
826 device_printf(sc->dev,
827 "Can't setup xDMA RX interrupt handler.\n");
831 /* Setup bounce buffer */
832 vmem = xdma_get_memory(dev);
834 xchan_set_memory(sc->xchan_tx, vmem);
835 xchan_set_memory(sc->xchan_rx, vmem);
838 xdma_prep_sg(sc->xchan_tx,
839 TX_QUEUE_SIZE, /* xchan requests queue size */
840 MCLBYTES, /* maxsegsize */
844 BUS_SPACE_MAXADDR_32BIT,
847 xdma_prep_sg(sc->xchan_rx,
848 RX_QUEUE_SIZE, /* xchan requests queue size */
849 MCLBYTES, /* maxsegsize */
853 BUS_SPACE_MAXADDR_32BIT,
860 xae_probe(device_t dev)
863 if (!ofw_bus_status_okay(dev))
866 if (!ofw_bus_is_compatible(dev, "xlnx,axi-ethernet-1.00.a"))
869 device_set_desc(dev, "Xilinx AXI Ethernet");
871 return (BUS_PROBE_DEFAULT);
875 xae_attach(device_t dev)
877 struct xae_softc *sc;
883 sc = device_get_softc(dev);
885 node = ofw_bus_get_node(dev);
887 if (setup_xdma(sc) != 0) {
888 device_printf(dev, "Could not setup xDMA.\n");
892 mtx_init(&sc->mtx, device_get_nameunit(sc->dev),
893 MTX_NETWORK_LOCK, MTX_DEF);
895 sc->br = buf_ring_alloc(BUFRING_SIZE, M_DEVBUF,
900 if (bus_alloc_resources(dev, xae_spec, sc->res)) {
901 device_printf(dev, "could not allocate resources\n");
905 /* Memory interface */
906 sc->bst = rman_get_bustag(sc->res[0]);
907 sc->bsh = rman_get_bushandle(sc->res[0]);
909 device_printf(sc->dev, "Identification: %x\n",
910 READ4(sc, XAE_IDENT));
913 if (xae_get_hwaddr(sc, sc->macaddr)) {
914 device_printf(sc->dev, "can't get mac\n");
918 /* Enable MII clock */
919 reg = (MDIO_CLK_DIV_DEFAULT << MDIO_SETUP_CLK_DIV_S);
920 reg |= MDIO_SETUP_ENABLE;
921 WRITE4(sc, XAE_MDIO_SETUP, reg);
925 callout_init_mtx(&sc->xae_callout, &sc->mtx, 0);
927 /* Setup interrupt handler. */
928 error = bus_setup_intr(dev, sc->res[1], INTR_TYPE_NET | INTR_MPSAFE,
929 NULL, xae_intr, sc, &sc->intr_cookie);
931 device_printf(dev, "could not setup interrupt handler.\n");
935 /* Set up the ethernet interface. */
936 sc->ifp = ifp = if_alloc(IFT_ETHER);
938 device_printf(dev, "could not allocate ifp.\n");
943 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
944 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
945 ifp->if_capabilities = IFCAP_VLAN_MTU;
946 ifp->if_capenable = ifp->if_capabilities;
947 ifp->if_transmit = xae_transmit;
948 ifp->if_qflush = xae_qflush;
949 ifp->if_ioctl = xae_ioctl;
950 ifp->if_init = xae_init;
951 IFQ_SET_MAXLEN(&ifp->if_snd, TX_DESC_COUNT - 1);
952 ifp->if_snd.ifq_drv_maxlen = TX_DESC_COUNT - 1;
953 IFQ_SET_READY(&ifp->if_snd);
955 if (xae_get_phyaddr(node, &sc->phy_addr) != 0)
958 /* Attach the mii driver. */
959 error = mii_attach(dev, &sc->miibus, ifp, xae_media_change,
960 xae_media_status, BMSR_DEFCAPMASK, sc->phy_addr,
964 device_printf(dev, "PHY attach failed\n");
967 sc->mii_softc = device_get_softc(sc->miibus);
969 /* Apply vcu118 workaround. */
970 if (OF_getproplen(node, "xlnx,vcu118") >= 0)
973 /* All ready to run, attach the ethernet interface. */
974 ether_ifattach(ifp, sc->macaddr);
975 sc->is_attached = true;
977 xae_rx_enqueue(sc, NUM_RX_MBUF);
978 xdma_queue_submit(sc->xchan_rx);
984 xae_detach(device_t dev)
986 struct xae_softc *sc;
989 sc = device_get_softc(dev);
991 KASSERT(mtx_initialized(&sc->mtx), ("%s: mutex not initialized",
992 device_get_nameunit(dev)));
996 /* Only cleanup if attach succeeded. */
997 if (device_is_attached(dev)) {
1001 callout_drain(&sc->xae_callout);
1002 ether_ifdetach(ifp);
1005 if (sc->miibus != NULL)
1006 device_delete_child(dev, sc->miibus);
1011 mtx_destroy(&sc->mtx);
1013 bus_teardown_intr(dev, sc->res[1], sc->intr_cookie);
1015 bus_release_resources(dev, xae_spec, sc->res);
1017 xdma_channel_free(sc->xchan_tx);
1018 xdma_channel_free(sc->xchan_rx);
1019 xdma_put(sc->xdma_tx);
1020 xdma_put(sc->xdma_rx);
1026 xae_miibus_statchg(device_t dev)
1028 struct xae_softc *sc;
1029 struct mii_data *mii;
1033 * Called by the MII bus driver when the PHY establishes
1034 * link to set the MAC interface registers.
1037 sc = device_get_softc(dev);
1039 XAE_ASSERT_LOCKED(sc);
1041 mii = sc->mii_softc;
1043 if (mii->mii_media_status & IFM_ACTIVE)
1044 sc->link_is_up = true;
1046 sc->link_is_up = false;
1048 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1060 sc->link_is_up = false;
1063 sc->link_is_up = false;
1064 device_printf(dev, "Unsupported media %u\n",
1065 IFM_SUBTYPE(mii->mii_media_active));
1069 WRITE4(sc, XAE_SPEED, reg);
1072 static device_method_t xae_methods[] = {
1073 DEVMETHOD(device_probe, xae_probe),
1074 DEVMETHOD(device_attach, xae_attach),
1075 DEVMETHOD(device_detach, xae_detach),
1078 DEVMETHOD(miibus_readreg, xae_miibus_read_reg),
1079 DEVMETHOD(miibus_writereg, xae_miibus_write_reg),
1080 DEVMETHOD(miibus_statchg, xae_miibus_statchg),
1085 driver_t xae_driver = {
1088 sizeof(struct xae_softc),
1091 static devclass_t xae_devclass;
1093 DRIVER_MODULE(xae, simplebus, xae_driver, xae_devclass, 0, 0);
1094 DRIVER_MODULE(miibus, xae, miibus_driver, miibus_devclass, 0, 0);
1096 MODULE_DEPEND(xae, ether, 1, 1, 1);
1097 MODULE_DEPEND(xae, miibus, 1, 1, 1);