2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1997, 1998, 1999
5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
35 #include <sys/cdefs.h>
36 __FBSDID("$FreeBSD$");
39 * 3Com 3c90x Etherlink XL PCI NIC driver
41 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI
42 * bus-master chips (3c90x cards and embedded controllers) including
45 * 3Com 3c900-TPO 10Mbps/RJ-45
46 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC
47 * 3Com 3c905-TX 10/100Mbps/RJ-45
48 * 3Com 3c905-T4 10/100Mbps/RJ-45
49 * 3Com 3c900B-TPO 10Mbps/RJ-45
50 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC
51 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC
52 * 3Com 3c900B-FL 10Mbps/Fiber-optic
53 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC
54 * 3Com 3c905B-TX 10/100Mbps/RJ-45
55 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic
56 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC)
57 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC)
58 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC)
59 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC)
60 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC)
61 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane)
62 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
63 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
64 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
65 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
66 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
67 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
68 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
69 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC)
70 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45
71 * Dell on-board 3c920 10/100Mbps/RJ-45
72 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45
73 * Dell Latitude laptop docking station embedded 3c905-TX
75 * Written by Bill Paul <wpaul@ctr.columbia.edu>
76 * Electrical Engineering Department
77 * Columbia University, New York City
80 * The 3c90x series chips use a bus-master DMA interface for transferring
81 * packets to and from the controller chip. Some of the "vortex" cards
82 * (3c59x) also supported a bus master mode, however for those chips
83 * you could only DMA packets to/from a contiguous memory buffer. For
84 * transmission this would mean copying the contents of the queued mbuf
85 * chain into an mbuf cluster and then DMAing the cluster. This extra
86 * copy would sort of defeat the purpose of the bus master support for
87 * any packet that doesn't fit into a single mbuf.
89 * By contrast, the 3c90x cards support a fragment-based bus master
90 * mode where mbuf chains can be encapsulated using TX descriptors.
91 * This is similar to other PCI chips such as the Texas Instruments
92 * ThunderLAN and the Intel 82557/82558.
94 * The "vortex" driver (if_vx.c) happens to work for the "boomerang"
95 * bus master chips because they maintain the old PIO interface for
96 * backwards compatibility, but starting with the 3c905B and the
97 * "cyclone" chips, the compatibility interface has been dropped.
98 * Since using bus master DMA is a big win, we use this driver to
99 * support the PCI "boomerang" chips even though they work with the
100 * "vortex" driver in order to obtain better performance.
103 #ifdef HAVE_KERNEL_OPTION_HEADERS
104 #include "opt_device_polling.h"
107 #include <sys/param.h>
108 #include <sys/systm.h>
109 #include <sys/sockio.h>
110 #include <sys/endian.h>
111 #include <sys/kernel.h>
112 #include <sys/malloc.h>
113 #include <sys/mbuf.h>
114 #include <sys/module.h>
115 #include <sys/socket.h>
116 #include <sys/taskqueue.h>
119 #include <net/if_var.h>
120 #include <net/if_arp.h>
121 #include <net/ethernet.h>
122 #include <net/if_dl.h>
123 #include <net/if_media.h>
124 #include <net/if_types.h>
128 #include <machine/bus.h>
129 #include <machine/resource.h>
131 #include <sys/rman.h>
133 #include <dev/mii/mii.h>
134 #include <dev/mii/mii_bitbang.h>
135 #include <dev/mii/miivar.h>
137 #include <dev/pci/pcireg.h>
138 #include <dev/pci/pcivar.h>
140 MODULE_DEPEND(xl, pci, 1, 1, 1);
141 MODULE_DEPEND(xl, ether, 1, 1, 1);
142 MODULE_DEPEND(xl, miibus, 1, 1, 1);
144 /* "device miibus" required. See GENERIC if you get errors here. */
145 #include "miibus_if.h"
147 #include <dev/xl/if_xlreg.h>
150 * TX Checksumming is disabled by default for two reasons:
151 * - TX Checksumming will occasionally produce corrupt packets
152 * - TX Checksumming seems to reduce performance
154 * Only 905B/C cards were reported to have this problem, it is possible
155 * that later chips _may_ be immune.
157 #define XL905B_TXCSUM_BROKEN 1
159 #ifdef XL905B_TXCSUM_BROKEN
160 #define XL905B_CSUM_FEATURES 0
162 #define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
166 * Various supported device vendors/types and their names.
168 static const struct xl_type xl_devs[] = {
169 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT,
170 "3Com 3c900-TPO Etherlink XL" },
171 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO,
172 "3Com 3c900-COMBO Etherlink XL" },
173 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT,
174 "3Com 3c905-TX Fast Etherlink XL" },
175 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4,
176 "3Com 3c905-T4 Fast Etherlink XL" },
177 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT,
178 "3Com 3c900B-TPO Etherlink XL" },
179 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO,
180 "3Com 3c900B-COMBO Etherlink XL" },
181 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC,
182 "3Com 3c900B-TPC Etherlink XL" },
183 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL,
184 "3Com 3c900B-FL Etherlink XL" },
185 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT,
186 "3Com 3c905B-TX Fast Etherlink XL" },
187 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4,
188 "3Com 3c905B-T4 Fast Etherlink XL" },
189 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX,
190 "3Com 3c905B-FX/SC Fast Etherlink XL" },
191 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO,
192 "3Com 3c905B-COMBO Fast Etherlink XL" },
193 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT,
194 "3Com 3c905C-TX Fast Etherlink XL" },
195 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B,
196 "3Com 3c920B-EMB Integrated Fast Etherlink XL" },
197 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B_WNM,
198 "3Com 3c920B-EMB-WNM Integrated Fast Etherlink XL" },
199 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV,
200 "3Com 3c980 Fast Etherlink XL" },
201 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV,
202 "3Com 3c980C Fast Etherlink XL" },
203 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX,
204 "3Com 3cSOHO100-TX OfficeConnect" },
205 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT,
206 "3Com 3c450-TX HomeConnect" },
207 { TC_VENDORID, TC_DEVICEID_HURRICANE_555,
208 "3Com 3c555 Fast Etherlink XL" },
209 { TC_VENDORID, TC_DEVICEID_HURRICANE_556,
210 "3Com 3c556 Fast Etherlink XL" },
211 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B,
212 "3Com 3c556B Fast Etherlink XL" },
213 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A,
214 "3Com 3c575TX Fast Etherlink XL" },
215 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B,
216 "3Com 3c575B Fast Etherlink XL" },
217 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C,
218 "3Com 3c575C Fast Etherlink XL" },
219 { TC_VENDORID, TC_DEVICEID_HURRICANE_656,
220 "3Com 3c656 Fast Etherlink XL" },
221 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B,
222 "3Com 3c656B Fast Etherlink XL" },
223 { TC_VENDORID, TC_DEVICEID_TORNADO_656C,
224 "3Com 3c656C Fast Etherlink XL" },
228 static int xl_probe(device_t);
229 static int xl_attach(device_t);
230 static int xl_detach(device_t);
232 static int xl_newbuf(struct xl_softc *, struct xl_chain_onefrag *);
233 static void xl_tick(void *);
234 static void xl_stats_update(struct xl_softc *);
235 static int xl_encap(struct xl_softc *, struct xl_chain *, struct mbuf **);
236 static int xl_rxeof(struct xl_softc *);
237 static void xl_rxeof_task(void *, int);
238 static int xl_rx_resync(struct xl_softc *);
239 static void xl_txeof(struct xl_softc *);
240 static void xl_txeof_90xB(struct xl_softc *);
241 static void xl_txeoc(struct xl_softc *);
242 static void xl_intr(void *);
243 static void xl_start(struct ifnet *);
244 static void xl_start_locked(struct ifnet *);
245 static void xl_start_90xB_locked(struct ifnet *);
246 static int xl_ioctl(struct ifnet *, u_long, caddr_t);
247 static void xl_init(void *);
248 static void xl_init_locked(struct xl_softc *);
249 static void xl_stop(struct xl_softc *);
250 static int xl_watchdog(struct xl_softc *);
251 static int xl_shutdown(device_t);
252 static int xl_suspend(device_t);
253 static int xl_resume(device_t);
254 static void xl_setwol(struct xl_softc *);
256 #ifdef DEVICE_POLLING
257 static int xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
258 static int xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count);
261 static int xl_ifmedia_upd(struct ifnet *);
262 static void xl_ifmedia_sts(struct ifnet *, struct ifmediareq *);
264 static int xl_eeprom_wait(struct xl_softc *);
265 static int xl_read_eeprom(struct xl_softc *, caddr_t, int, int, int);
267 static void xl_rxfilter(struct xl_softc *);
268 static void xl_rxfilter_90x(struct xl_softc *);
269 static void xl_rxfilter_90xB(struct xl_softc *);
270 static void xl_setcfg(struct xl_softc *);
271 static void xl_setmode(struct xl_softc *, int);
272 static void xl_reset(struct xl_softc *);
273 static int xl_list_rx_init(struct xl_softc *);
274 static int xl_list_tx_init(struct xl_softc *);
275 static int xl_list_tx_init_90xB(struct xl_softc *);
276 static void xl_wait(struct xl_softc *);
277 static void xl_mediacheck(struct xl_softc *);
278 static void xl_choose_media(struct xl_softc *sc, int *media);
279 static void xl_choose_xcvr(struct xl_softc *, int);
280 static void xl_dma_map_addr(void *, bus_dma_segment_t *, int, int);
282 static void xl_testpacket(struct xl_softc *);
285 static int xl_miibus_readreg(device_t, int, int);
286 static int xl_miibus_writereg(device_t, int, int, int);
287 static void xl_miibus_statchg(device_t);
288 static void xl_miibus_mediainit(device_t);
293 static uint32_t xl_mii_bitbang_read(device_t);
294 static void xl_mii_bitbang_write(device_t, uint32_t);
296 static const struct mii_bitbang_ops xl_mii_bitbang_ops = {
298 xl_mii_bitbang_write,
300 XL_MII_DATA, /* MII_BIT_MDO */
301 XL_MII_DATA, /* MII_BIT_MDI */
302 XL_MII_CLK, /* MII_BIT_MDC */
303 XL_MII_DIR, /* MII_BIT_DIR_HOST_PHY */
304 0, /* MII_BIT_DIR_PHY_HOST */
308 static device_method_t xl_methods[] = {
309 /* Device interface */
310 DEVMETHOD(device_probe, xl_probe),
311 DEVMETHOD(device_attach, xl_attach),
312 DEVMETHOD(device_detach, xl_detach),
313 DEVMETHOD(device_shutdown, xl_shutdown),
314 DEVMETHOD(device_suspend, xl_suspend),
315 DEVMETHOD(device_resume, xl_resume),
318 DEVMETHOD(miibus_readreg, xl_miibus_readreg),
319 DEVMETHOD(miibus_writereg, xl_miibus_writereg),
320 DEVMETHOD(miibus_statchg, xl_miibus_statchg),
321 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit),
326 static driver_t xl_driver = {
329 sizeof(struct xl_softc)
332 static devclass_t xl_devclass;
334 DRIVER_MODULE_ORDERED(xl, pci, xl_driver, xl_devclass, NULL, NULL,
336 DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, NULL, NULL);
337 MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, xl, xl_devs,
338 nitems(xl_devs) - 1);
341 xl_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
346 *paddr = segs->ds_addr;
350 * Murphy's law says that it's possible the chip can wedge and
351 * the 'command in progress' bit may never clear. Hence, we wait
352 * only a finite amount of time to avoid getting caught in an
353 * infinite loop. Normally this delay routine would be a macro,
354 * but it isn't called during normal operation so we can afford
355 * to make it a function. Suppress warning when card gone.
358 xl_wait(struct xl_softc *sc)
362 for (i = 0; i < XL_TIMEOUT; i++) {
363 if ((CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY) == 0)
367 if (i == XL_TIMEOUT && bus_child_present(sc->xl_dev))
368 device_printf(sc->xl_dev, "command never completed!\n");
372 * MII access routines are provided for adapters with external
373 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in
374 * autoneg logic that's faked up to look like a PHY (3c905B-TX).
375 * Note: if you don't perform the MDIO operations just right,
376 * it's possible to end up with code that works correctly with
377 * some chips/CPUs/processor speeds/bus speeds/etc but not
382 * Read the MII serial port for the MII bit-bang module.
385 xl_mii_bitbang_read(device_t dev)
390 sc = device_get_softc(dev);
392 /* We're already in window 4. */
393 val = CSR_READ_2(sc, XL_W4_PHY_MGMT);
394 CSR_BARRIER(sc, XL_W4_PHY_MGMT, 2,
395 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
401 * Write the MII serial port for the MII bit-bang module.
404 xl_mii_bitbang_write(device_t dev, uint32_t val)
408 sc = device_get_softc(dev);
410 /* We're already in window 4. */
411 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, val);
412 CSR_BARRIER(sc, XL_W4_PHY_MGMT, 2,
413 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
417 xl_miibus_readreg(device_t dev, int phy, int reg)
421 sc = device_get_softc(dev);
423 /* Select the window 4. */
426 return (mii_bitbang_readreg(dev, &xl_mii_bitbang_ops, phy, reg));
430 xl_miibus_writereg(device_t dev, int phy, int reg, int data)
434 sc = device_get_softc(dev);
436 /* Select the window 4. */
439 mii_bitbang_writereg(dev, &xl_mii_bitbang_ops, phy, reg, data);
445 xl_miibus_statchg(device_t dev)
448 struct mii_data *mii;
451 sc = device_get_softc(dev);
452 mii = device_get_softc(sc->xl_miibus);
456 /* Set ASIC's duplex mode to match the PHY. */
458 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL);
459 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
460 macctl |= XL_MACCTRL_DUPLEX;
461 if (sc->xl_type == XL_TYPE_905B) {
462 if ((IFM_OPTIONS(mii->mii_media_active) &
463 IFM_ETH_RXPAUSE) != 0)
464 macctl |= XL_MACCTRL_FLOW_CONTROL_ENB;
466 macctl &= ~XL_MACCTRL_FLOW_CONTROL_ENB;
469 macctl &= ~XL_MACCTRL_DUPLEX;
470 if (sc->xl_type == XL_TYPE_905B)
471 macctl &= ~XL_MACCTRL_FLOW_CONTROL_ENB;
473 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl);
477 * Special support for the 3c905B-COMBO. This card has 10/100 support
478 * plus BNC and AUI ports. This means we will have both an miibus attached
479 * plus some non-MII media settings. In order to allow this, we have to
480 * add the extra media to the miibus's ifmedia struct, but we can't do
481 * that during xl_attach() because the miibus hasn't been attached yet.
482 * So instead, we wait until the miibus probe/attach is done, at which
483 * point we will get a callback telling is that it's safe to add our
487 xl_miibus_mediainit(device_t dev)
490 struct mii_data *mii;
493 sc = device_get_softc(dev);
494 mii = device_get_softc(sc->xl_miibus);
495 ifm = &mii->mii_media;
497 if (sc->xl_media & (XL_MEDIAOPT_AUI | XL_MEDIAOPT_10FL)) {
499 * Check for a 10baseFL board in disguise.
501 if (sc->xl_type == XL_TYPE_905B &&
502 sc->xl_media == XL_MEDIAOPT_10FL) {
504 device_printf(sc->xl_dev, "found 10baseFL\n");
505 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL, 0, NULL);
506 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL|IFM_HDX, 0,
508 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
510 IFM_ETHER | IFM_10_FL | IFM_FDX, 0, NULL);
513 device_printf(sc->xl_dev, "found AUI\n");
514 ifmedia_add(ifm, IFM_ETHER | IFM_10_5, 0, NULL);
518 if (sc->xl_media & XL_MEDIAOPT_BNC) {
520 device_printf(sc->xl_dev, "found BNC\n");
521 ifmedia_add(ifm, IFM_ETHER | IFM_10_2, 0, NULL);
526 * The EEPROM is slow: give it time to come ready after issuing
530 xl_eeprom_wait(struct xl_softc *sc)
534 for (i = 0; i < 100; i++) {
535 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY)
542 device_printf(sc->xl_dev, "eeprom failed to come ready\n");
550 * Read a sequence of words from the EEPROM. Note that ethernet address
551 * data is stored in the EEPROM in network byte order.
554 xl_read_eeprom(struct xl_softc *sc, caddr_t dest, int off, int cnt, int swap)
557 u_int16_t word = 0, *ptr;
559 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F))
560 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F)
562 * XXX: WARNING! DANGER!
563 * It's easy to accidentally overwrite the rom content!
564 * Note: the 3c575 uses 8bit EEPROM offsets.
568 if (xl_eeprom_wait(sc))
571 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30)
574 for (i = 0; i < cnt; i++) {
575 if (sc->xl_flags & XL_FLAG_8BITROM)
576 CSR_WRITE_2(sc, XL_W0_EE_CMD,
577 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i));
579 CSR_WRITE_2(sc, XL_W0_EE_CMD,
580 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i));
581 err = xl_eeprom_wait(sc);
584 word = CSR_READ_2(sc, XL_W0_EE_DATA);
585 ptr = (u_int16_t *)(dest + (i * 2));
592 return (err ? 1 : 0);
596 xl_rxfilter(struct xl_softc *sc)
599 if (sc->xl_type == XL_TYPE_905B)
600 xl_rxfilter_90xB(sc);
606 * NICs older than the 3c905B have only one multicast option, which
607 * is to enable reception of all multicast frames.
610 xl_check_maddr_90x(void *arg, struct sockaddr_dl *sdl, u_int cnt)
612 uint8_t *rxfilt = arg;
614 *rxfilt |= XL_RXFILTER_ALLMULTI;
620 xl_rxfilter_90x(struct xl_softc *sc)
630 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
631 rxfilt &= ~(XL_RXFILTER_ALLFRAMES | XL_RXFILTER_ALLMULTI |
632 XL_RXFILTER_BROADCAST | XL_RXFILTER_INDIVIDUAL);
634 /* Set the individual bit to receive frames for this host only. */
635 rxfilt |= XL_RXFILTER_INDIVIDUAL;
636 /* Set capture broadcast bit to capture broadcast frames. */
637 if (ifp->if_flags & IFF_BROADCAST)
638 rxfilt |= XL_RXFILTER_BROADCAST;
640 /* If we want promiscuous mode, set the allframes bit. */
641 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) {
642 if (ifp->if_flags & IFF_PROMISC)
643 rxfilt |= XL_RXFILTER_ALLFRAMES;
644 if (ifp->if_flags & IFF_ALLMULTI)
645 rxfilt |= XL_RXFILTER_ALLMULTI;
647 if_foreach_llmaddr(sc->xl_ifp, xl_check_maddr_90x, &rxfilt);
649 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT);
654 * 3c905B adapters have a hash filter that we can program.
655 * Note: the 3c905B currently only supports a 64-bit
656 * hash table, which means we really only need 6 bits,
657 * but the manual indicates that future chip revisions
658 * will have a 256-bit hash table, hence the routine
659 * is set up to calculate 8 bits of position info in
660 * case we need it some day.
661 * Note II, The Sequel: _CURRENT_ versions of the
662 * 3c905B have a 256 bit hash table. This means we have
663 * to use all 8 bits regardless. On older cards, the
664 * upper 2 bits will be ignored. Grrrr....
667 xl_check_maddr_90xB(void *arg, struct sockaddr_dl *sdl, u_int count)
669 struct xl_softc *sc = arg;
672 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) & 0xFF;
673 CSR_WRITE_2(sc, XL_COMMAND, h | XL_CMD_RX_SET_HASH | XL_HASH_SET);
679 xl_rxfilter_90xB(struct xl_softc *sc)
690 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
691 rxfilt &= ~(XL_RXFILTER_ALLFRAMES | XL_RXFILTER_ALLMULTI |
692 XL_RXFILTER_BROADCAST | XL_RXFILTER_INDIVIDUAL |
693 XL_RXFILTER_MULTIHASH);
695 /* Set the individual bit to receive frames for this host only. */
696 rxfilt |= XL_RXFILTER_INDIVIDUAL;
697 /* Set capture broadcast bit to capture broadcast frames. */
698 if (ifp->if_flags & IFF_BROADCAST)
699 rxfilt |= XL_RXFILTER_BROADCAST;
701 /* If we want promiscuous mode, set the allframes bit. */
702 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) {
703 if (ifp->if_flags & IFF_PROMISC)
704 rxfilt |= XL_RXFILTER_ALLFRAMES;
705 if (ifp->if_flags & IFF_ALLMULTI)
706 rxfilt |= XL_RXFILTER_ALLMULTI;
708 /* First, zot all the existing hash bits. */
709 for (i = 0; i < XL_HASHFILT_SIZE; i++)
710 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH | i);
712 /* Now program new ones. */
713 if (if_foreach_llmaddr(sc->xl_ifp, xl_check_maddr_90xB, sc) > 0)
714 rxfilt |= XL_RXFILTER_MULTIHASH;
717 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT);
722 xl_setcfg(struct xl_softc *sc)
726 /*XL_LOCK_ASSERT(sc);*/
729 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
730 icfg &= ~XL_ICFG_CONNECTOR_MASK;
731 if (sc->xl_media & XL_MEDIAOPT_MII ||
732 sc->xl_media & XL_MEDIAOPT_BT4)
733 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS);
734 if (sc->xl_media & XL_MEDIAOPT_BTX)
735 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS);
737 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
738 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
742 xl_setmode(struct xl_softc *sc, int media)
746 char *pmsg = "", *dmsg = "";
751 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
753 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
755 if (sc->xl_media & XL_MEDIAOPT_BT) {
756 if (IFM_SUBTYPE(media) == IFM_10_T) {
757 pmsg = "10baseT transceiver";
758 sc->xl_xcvr = XL_XCVR_10BT;
759 icfg &= ~XL_ICFG_CONNECTOR_MASK;
760 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS);
761 mediastat |= XL_MEDIASTAT_LINKBEAT |
762 XL_MEDIASTAT_JABGUARD;
763 mediastat &= ~XL_MEDIASTAT_SQEENB;
767 if (sc->xl_media & XL_MEDIAOPT_BFX) {
768 if (IFM_SUBTYPE(media) == IFM_100_FX) {
769 pmsg = "100baseFX port";
770 sc->xl_xcvr = XL_XCVR_100BFX;
771 icfg &= ~XL_ICFG_CONNECTOR_MASK;
772 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS);
773 mediastat |= XL_MEDIASTAT_LINKBEAT;
774 mediastat &= ~XL_MEDIASTAT_SQEENB;
778 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
779 if (IFM_SUBTYPE(media) == IFM_10_5) {
781 sc->xl_xcvr = XL_XCVR_AUI;
782 icfg &= ~XL_ICFG_CONNECTOR_MASK;
783 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
784 mediastat &= ~(XL_MEDIASTAT_LINKBEAT |
785 XL_MEDIASTAT_JABGUARD);
786 mediastat |= ~XL_MEDIASTAT_SQEENB;
788 if (IFM_SUBTYPE(media) == IFM_10_FL) {
789 pmsg = "10baseFL transceiver";
790 sc->xl_xcvr = XL_XCVR_AUI;
791 icfg &= ~XL_ICFG_CONNECTOR_MASK;
792 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
793 mediastat &= ~(XL_MEDIASTAT_LINKBEAT |
794 XL_MEDIASTAT_JABGUARD);
795 mediastat |= ~XL_MEDIASTAT_SQEENB;
799 if (sc->xl_media & XL_MEDIAOPT_BNC) {
800 if (IFM_SUBTYPE(media) == IFM_10_2) {
802 sc->xl_xcvr = XL_XCVR_COAX;
803 icfg &= ~XL_ICFG_CONNECTOR_MASK;
804 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS);
805 mediastat &= ~(XL_MEDIASTAT_LINKBEAT |
806 XL_MEDIASTAT_JABGUARD | XL_MEDIASTAT_SQEENB);
810 if ((media & IFM_GMASK) == IFM_FDX ||
811 IFM_SUBTYPE(media) == IFM_100_FX) {
814 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
818 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
819 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
822 if (IFM_SUBTYPE(media) == IFM_10_2)
823 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
825 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
827 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
829 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat);
834 device_printf(sc->xl_dev, "selecting %s, %s duplex\n", pmsg, dmsg);
838 xl_reset(struct xl_softc *sc)
845 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET |
846 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ?
847 XL_RESETOPT_DISADVFD:0));
850 * If we're using memory mapped register mode, pause briefly
851 * after issuing the reset command before trying to access any
852 * other registers. With my 3c575C CardBus card, failing to do
853 * this results in the system locking up while trying to poll
854 * the command busy bit in the status register.
856 if (sc->xl_flags & XL_FLAG_USE_MMIO)
859 for (i = 0; i < XL_TIMEOUT; i++) {
861 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
866 device_printf(sc->xl_dev, "reset didn't complete\n");
868 /* Reset TX and RX. */
869 /* Note: the RX reset takes an absurd amount of time
870 * on newer versions of the Tornado chips such as those
871 * on the 3c905CX and newer 3c908C cards. We wait an
872 * extra amount of time so that xl_wait() doesn't complain
873 * and annoy the users.
875 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
878 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
881 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR ||
882 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) {
884 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS,
885 CSR_READ_2(sc, XL_W2_RESET_OPTIONS) |
886 ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR) ?
887 XL_RESETOPT_INVERT_LED : 0) |
888 ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR) ?
889 XL_RESETOPT_INVERT_MII : 0));
892 /* Wait a little while for the chip to get its brains in order. */
897 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device
898 * IDs against our list and return a device name if we find a match.
901 xl_probe(device_t dev)
903 const struct xl_type *t;
907 while (t->xl_name != NULL) {
908 if ((pci_get_vendor(dev) == t->xl_vid) &&
909 (pci_get_device(dev) == t->xl_did)) {
910 device_set_desc(dev, t->xl_name);
911 return (BUS_PROBE_DEFAULT);
920 * This routine is a kludge to work around possible hardware faults
921 * or manufacturing defects that can cause the media options register
922 * (or reset options register, as it's called for the first generation
923 * 3c90x adapters) to return an incorrect result. I have encountered
924 * one Dell Latitude laptop docking station with an integrated 3c905-TX
925 * which doesn't have any of the 'mediaopt' bits set. This screws up
926 * the attach routine pretty badly because it doesn't know what media
927 * to look for. If we find ourselves in this predicament, this routine
928 * will try to guess the media options values and warn the user of a
929 * possible manufacturing defect with his adapter/system/whatever.
932 xl_mediacheck(struct xl_softc *sc)
936 * If some of the media options bits are set, assume they are
937 * correct. If not, try to figure it out down below.
938 * XXX I should check for 10baseFL, but I don't have an adapter
941 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) {
943 * Check the XCVR value. If it's not in the normal range
944 * of values, we need to fake it up here.
946 if (sc->xl_xcvr <= XL_XCVR_AUTO)
949 device_printf(sc->xl_dev,
950 "bogus xcvr value in EEPROM (%x)\n", sc->xl_xcvr);
951 device_printf(sc->xl_dev,
952 "choosing new default based on card type\n");
955 if (sc->xl_type == XL_TYPE_905B &&
956 sc->xl_media & XL_MEDIAOPT_10FL)
958 device_printf(sc->xl_dev,
959 "WARNING: no media options bits set in the media options register!!\n");
960 device_printf(sc->xl_dev,
961 "this could be a manufacturing defect in your adapter or system\n");
962 device_printf(sc->xl_dev,
963 "attempting to guess media type; you should probably consult your vendor\n");
966 xl_choose_xcvr(sc, 1);
970 xl_choose_xcvr(struct xl_softc *sc, int verbose)
975 * Read the device ID from the EEPROM.
976 * This is what's loaded into the PCI device ID register, so it has
977 * to be correct otherwise we wouldn't have gotten this far.
979 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0);
982 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */
983 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */
984 sc->xl_media = XL_MEDIAOPT_BT;
985 sc->xl_xcvr = XL_XCVR_10BT;
987 device_printf(sc->xl_dev,
988 "guessing 10BaseT transceiver\n");
990 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */
991 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */
992 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
993 sc->xl_xcvr = XL_XCVR_10BT;
995 device_printf(sc->xl_dev,
996 "guessing COMBO (AUI/BNC/TP)\n");
998 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */
999 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC;
1000 sc->xl_xcvr = XL_XCVR_10BT;
1002 device_printf(sc->xl_dev, "guessing TPC (BNC/TP)\n");
1004 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */
1005 sc->xl_media = XL_MEDIAOPT_10FL;
1006 sc->xl_xcvr = XL_XCVR_AUI;
1008 device_printf(sc->xl_dev, "guessing 10baseFL\n");
1010 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */
1011 case TC_DEVICEID_HURRICANE_555: /* 3c555 */
1012 case TC_DEVICEID_HURRICANE_556: /* 3c556 */
1013 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */
1014 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */
1015 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */
1016 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */
1017 case TC_DEVICEID_HURRICANE_656: /* 3c656 */
1018 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */
1019 case TC_DEVICEID_TORNADO_656C: /* 3c656C */
1020 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */
1021 case TC_DEVICEID_TORNADO_10_100BT_920B_WNM: /* 3c920B-EMB-WNM */
1022 sc->xl_media = XL_MEDIAOPT_MII;
1023 sc->xl_xcvr = XL_XCVR_MII;
1025 device_printf(sc->xl_dev, "guessing MII\n");
1027 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */
1028 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */
1029 sc->xl_media = XL_MEDIAOPT_BT4;
1030 sc->xl_xcvr = XL_XCVR_MII;
1032 device_printf(sc->xl_dev, "guessing 100baseT4/MII\n");
1034 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */
1035 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */
1036 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */
1037 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */
1038 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */
1039 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */
1040 sc->xl_media = XL_MEDIAOPT_BTX;
1041 sc->xl_xcvr = XL_XCVR_AUTO;
1043 device_printf(sc->xl_dev, "guessing 10/100 internal\n");
1045 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */
1046 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1047 sc->xl_xcvr = XL_XCVR_AUTO;
1049 device_printf(sc->xl_dev,
1050 "guessing 10/100 plus BNC/AUI\n");
1053 device_printf(sc->xl_dev,
1054 "unknown device ID: %x -- defaulting to 10baseT\n", devid);
1055 sc->xl_media = XL_MEDIAOPT_BT;
1061 * Attach the interface. Allocate softc structures, do ifmedia
1062 * setup and ethernet/BPF attach.
1065 xl_attach(device_t dev)
1067 u_char eaddr[ETHER_ADDR_LEN];
1068 u_int16_t sinfo2, xcvr[2];
1069 struct xl_softc *sc;
1072 int error = 0, phy, rid, res, unit;
1075 sc = device_get_softc(dev);
1078 unit = device_get_unit(dev);
1080 mtx_init(&sc->xl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1082 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts);
1084 did = pci_get_device(dev);
1087 if (did == TC_DEVICEID_HURRICANE_555)
1088 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK;
1089 if (did == TC_DEVICEID_HURRICANE_556 ||
1090 did == TC_DEVICEID_HURRICANE_556B)
1091 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK |
1092 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET |
1093 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR;
1094 if (did == TC_DEVICEID_HURRICANE_555 ||
1095 did == TC_DEVICEID_HURRICANE_556)
1096 sc->xl_flags |= XL_FLAG_8BITROM;
1097 if (did == TC_DEVICEID_HURRICANE_556B)
1098 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR;
1100 if (did == TC_DEVICEID_HURRICANE_575B ||
1101 did == TC_DEVICEID_HURRICANE_575C ||
1102 did == TC_DEVICEID_HURRICANE_656B ||
1103 did == TC_DEVICEID_TORNADO_656C)
1104 sc->xl_flags |= XL_FLAG_FUNCREG;
1105 if (did == TC_DEVICEID_HURRICANE_575A ||
1106 did == TC_DEVICEID_HURRICANE_575B ||
1107 did == TC_DEVICEID_HURRICANE_575C ||
1108 did == TC_DEVICEID_HURRICANE_656B ||
1109 did == TC_DEVICEID_TORNADO_656C)
1110 sc->xl_flags |= XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 |
1112 if (did == TC_DEVICEID_HURRICANE_656)
1113 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK;
1114 if (did == TC_DEVICEID_HURRICANE_575B)
1115 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR;
1116 if (did == TC_DEVICEID_HURRICANE_575C)
1117 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1118 if (did == TC_DEVICEID_TORNADO_656C)
1119 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1120 if (did == TC_DEVICEID_HURRICANE_656 ||
1121 did == TC_DEVICEID_HURRICANE_656B)
1122 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR |
1123 XL_FLAG_INVERT_LED_PWR;
1124 if (did == TC_DEVICEID_TORNADO_10_100BT_920B ||
1125 did == TC_DEVICEID_TORNADO_10_100BT_920B_WNM)
1126 sc->xl_flags |= XL_FLAG_PHYOK;
1129 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */
1130 case TC_DEVICEID_HURRICANE_575A:
1131 case TC_DEVICEID_HURRICANE_575B:
1132 case TC_DEVICEID_HURRICANE_575C:
1133 sc->xl_flags |= XL_FLAG_NO_MMIO;
1140 * Map control/status registers.
1142 pci_enable_busmaster(dev);
1144 if ((sc->xl_flags & XL_FLAG_NO_MMIO) == 0) {
1146 res = SYS_RES_MEMORY;
1148 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE);
1151 if (sc->xl_res != NULL) {
1152 sc->xl_flags |= XL_FLAG_USE_MMIO;
1154 device_printf(dev, "using memory mapped I/O\n");
1157 res = SYS_RES_IOPORT;
1158 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE);
1159 if (sc->xl_res == NULL) {
1160 device_printf(dev, "couldn't map ports/memory\n");
1165 device_printf(dev, "using port I/O\n");
1168 sc->xl_btag = rman_get_bustag(sc->xl_res);
1169 sc->xl_bhandle = rman_get_bushandle(sc->xl_res);
1171 if (sc->xl_flags & XL_FLAG_FUNCREG) {
1172 rid = XL_PCI_FUNCMEM;
1173 sc->xl_fres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1176 if (sc->xl_fres == NULL) {
1177 device_printf(dev, "couldn't map funcreg memory\n");
1182 sc->xl_ftag = rman_get_bustag(sc->xl_fres);
1183 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres);
1186 /* Allocate interrupt */
1188 sc->xl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1189 RF_SHAREABLE | RF_ACTIVE);
1190 if (sc->xl_irq == NULL) {
1191 device_printf(dev, "couldn't map interrupt\n");
1196 /* Initialize interface name. */
1197 ifp = sc->xl_ifp = if_alloc(IFT_ETHER);
1199 device_printf(dev, "can not if_alloc()\n");
1204 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1206 /* Reset the adapter. */
1212 * Get station address from the EEPROM.
1214 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) {
1215 device_printf(dev, "failed to read station address\n");
1220 callout_init_mtx(&sc->xl_tick_callout, &sc->xl_mtx, 0);
1221 NET_TASK_INIT(&sc->xl_task, 0, xl_rxeof_task, sc);
1224 * Now allocate a tag for the DMA descriptor lists and a chunk
1225 * of DMA-able memory based on the tag. Also obtain the DMA
1226 * addresses of the RX and TX ring, which we'll need later.
1227 * All of our lists are allocated as a contiguous block
1230 error = bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0,
1231 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1232 XL_RX_LIST_SZ, 1, XL_RX_LIST_SZ, 0, NULL, NULL,
1233 &sc->xl_ldata.xl_rx_tag);
1235 device_printf(dev, "failed to allocate rx dma tag\n");
1239 error = bus_dmamem_alloc(sc->xl_ldata.xl_rx_tag,
1240 (void **)&sc->xl_ldata.xl_rx_list, BUS_DMA_NOWAIT |
1241 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->xl_ldata.xl_rx_dmamap);
1243 device_printf(dev, "no memory for rx list buffers!\n");
1244 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1245 sc->xl_ldata.xl_rx_tag = NULL;
1249 error = bus_dmamap_load(sc->xl_ldata.xl_rx_tag,
1250 sc->xl_ldata.xl_rx_dmamap, sc->xl_ldata.xl_rx_list,
1251 XL_RX_LIST_SZ, xl_dma_map_addr,
1252 &sc->xl_ldata.xl_rx_dmaaddr, BUS_DMA_NOWAIT);
1254 device_printf(dev, "cannot get dma address of the rx ring!\n");
1255 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list,
1256 sc->xl_ldata.xl_rx_dmamap);
1257 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1258 sc->xl_ldata.xl_rx_tag = NULL;
1262 error = bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0,
1263 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1264 XL_TX_LIST_SZ, 1, XL_TX_LIST_SZ, 0, NULL, NULL,
1265 &sc->xl_ldata.xl_tx_tag);
1267 device_printf(dev, "failed to allocate tx dma tag\n");
1271 error = bus_dmamem_alloc(sc->xl_ldata.xl_tx_tag,
1272 (void **)&sc->xl_ldata.xl_tx_list, BUS_DMA_NOWAIT |
1273 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->xl_ldata.xl_tx_dmamap);
1275 device_printf(dev, "no memory for list buffers!\n");
1276 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1277 sc->xl_ldata.xl_tx_tag = NULL;
1281 error = bus_dmamap_load(sc->xl_ldata.xl_tx_tag,
1282 sc->xl_ldata.xl_tx_dmamap, sc->xl_ldata.xl_tx_list,
1283 XL_TX_LIST_SZ, xl_dma_map_addr,
1284 &sc->xl_ldata.xl_tx_dmaaddr, BUS_DMA_NOWAIT);
1286 device_printf(dev, "cannot get dma address of the tx ring!\n");
1287 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list,
1288 sc->xl_ldata.xl_tx_dmamap);
1289 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1290 sc->xl_ldata.xl_tx_tag = NULL;
1295 * Allocate a DMA tag for the mapping of mbufs.
1297 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
1298 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1299 MCLBYTES * XL_MAXFRAGS, XL_MAXFRAGS, MCLBYTES, 0, NULL,
1300 NULL, &sc->xl_mtag);
1302 device_printf(dev, "failed to allocate mbuf dma tag\n");
1306 /* We need a spare DMA map for the RX ring. */
1307 error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap);
1312 * Figure out the card type. 3c905B adapters have the
1313 * 'supportsNoTxLength' bit set in the capabilities
1314 * word in the EEPROM.
1315 * Note: my 3c575C CardBus card lies. It returns a value
1316 * of 0x1578 for its capabilities word, which is somewhat
1317 * nonsensical. Another way to distinguish a 3c90x chip
1318 * from a 3c90xB/C chip is to check for the 'supportsLargePackets'
1319 * bit. This will only be set for 3c90x boomerage chips.
1321 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0);
1322 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH ||
1323 !(sc->xl_caps & XL_CAPS_LARGE_PKTS))
1324 sc->xl_type = XL_TYPE_905B;
1326 sc->xl_type = XL_TYPE_90X;
1328 /* Check availability of WOL. */
1329 if ((sc->xl_caps & XL_CAPS_PWRMGMT) != 0 &&
1330 pci_find_cap(dev, PCIY_PMG, &pmcap) == 0) {
1331 sc->xl_pmcap = pmcap;
1332 sc->xl_flags |= XL_FLAG_WOL;
1334 xl_read_eeprom(sc, (caddr_t)&sinfo2, XL_EE_SOFTINFO2, 1, 0);
1335 if ((sinfo2 & XL_SINFO2_AUX_WOL_CON) == 0 && bootverbose)
1337 "No auxiliary remote wakeup connector!\n");
1340 /* Set the TX start threshold for best performance. */
1341 sc->xl_tx_thresh = XL_MIN_FRAMELEN;
1343 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1344 ifp->if_ioctl = xl_ioctl;
1345 ifp->if_capabilities = IFCAP_VLAN_MTU;
1346 if (sc->xl_type == XL_TYPE_905B) {
1347 ifp->if_hwassist = XL905B_CSUM_FEATURES;
1348 #ifdef XL905B_TXCSUM_BROKEN
1349 ifp->if_capabilities |= IFCAP_RXCSUM;
1351 ifp->if_capabilities |= IFCAP_HWCSUM;
1354 if ((sc->xl_flags & XL_FLAG_WOL) != 0)
1355 ifp->if_capabilities |= IFCAP_WOL_MAGIC;
1356 ifp->if_capenable = ifp->if_capabilities;
1357 #ifdef DEVICE_POLLING
1358 ifp->if_capabilities |= IFCAP_POLLING;
1360 ifp->if_start = xl_start;
1361 ifp->if_init = xl_init;
1362 IFQ_SET_MAXLEN(&ifp->if_snd, XL_TX_LIST_CNT - 1);
1363 ifp->if_snd.ifq_drv_maxlen = XL_TX_LIST_CNT - 1;
1364 IFQ_SET_READY(&ifp->if_snd);
1367 * Now we have to see what sort of media we have.
1368 * This includes probing for an MII interace and a
1372 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT);
1374 device_printf(dev, "media options word: %x\n", sc->xl_media);
1376 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0);
1377 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16;
1378 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK;
1379 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS;
1383 if (sc->xl_media & XL_MEDIAOPT_MII ||
1384 sc->xl_media & XL_MEDIAOPT_BTX ||
1385 sc->xl_media & XL_MEDIAOPT_BT4) {
1387 device_printf(dev, "found MII/AUTO\n");
1390 * Attach PHYs only at MII address 24 if !XL_FLAG_PHYOK.
1391 * This is to guard against problems with certain 3Com ASIC
1392 * revisions that incorrectly map the internal transceiver
1393 * control registers at all MII addresses.
1396 if ((sc->xl_flags & XL_FLAG_PHYOK) == 0)
1398 error = mii_attach(dev, &sc->xl_miibus, ifp, xl_ifmedia_upd,
1399 xl_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY,
1400 sc->xl_type == XL_TYPE_905B ? MIIF_DOPAUSE : 0);
1402 device_printf(dev, "attaching PHYs failed\n");
1409 * Sanity check. If the user has selected "auto" and this isn't
1410 * a 10/100 card of some kind, we need to force the transceiver
1411 * type to something sane.
1413 if (sc->xl_xcvr == XL_XCVR_AUTO)
1414 xl_choose_xcvr(sc, bootverbose);
1419 if (sc->xl_media & XL_MEDIAOPT_BT) {
1421 device_printf(dev, "found 10baseT\n");
1422 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1423 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
1424 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1425 ifmedia_add(&sc->ifmedia,
1426 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1429 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
1431 * Check for a 10baseFL board in disguise.
1433 if (sc->xl_type == XL_TYPE_905B &&
1434 sc->xl_media == XL_MEDIAOPT_10FL) {
1436 device_printf(dev, "found 10baseFL\n");
1437 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL);
1438 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX,
1440 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1441 ifmedia_add(&sc->ifmedia,
1442 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL);
1445 device_printf(dev, "found AUI\n");
1446 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
1450 if (sc->xl_media & XL_MEDIAOPT_BNC) {
1452 device_printf(dev, "found BNC\n");
1453 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL);
1456 if (sc->xl_media & XL_MEDIAOPT_BFX) {
1458 device_printf(dev, "found 100baseFX\n");
1459 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL);
1462 media = IFM_ETHER|IFM_100_TX|IFM_FDX;
1463 xl_choose_media(sc, &media);
1465 if (sc->xl_miibus == NULL)
1466 ifmedia_set(&sc->ifmedia, media);
1469 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) {
1471 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS);
1475 * Call MI attach routine.
1477 ether_ifattach(ifp, eaddr);
1479 error = bus_setup_intr(dev, sc->xl_irq, INTR_TYPE_NET | INTR_MPSAFE,
1480 NULL, xl_intr, sc, &sc->xl_intrhand);
1482 device_printf(dev, "couldn't set up irq\n");
1483 ether_ifdetach(ifp);
1495 * Choose a default media.
1496 * XXX This is a leaf function only called by xl_attach() and
1497 * acquires/releases the non-recursible driver mutex to
1498 * satisfy lock assertions.
1501 xl_choose_media(struct xl_softc *sc, int *media)
1506 switch (sc->xl_xcvr) {
1508 *media = IFM_ETHER|IFM_10_T;
1509 xl_setmode(sc, *media);
1512 if (sc->xl_type == XL_TYPE_905B &&
1513 sc->xl_media == XL_MEDIAOPT_10FL) {
1514 *media = IFM_ETHER|IFM_10_FL;
1515 xl_setmode(sc, *media);
1517 *media = IFM_ETHER|IFM_10_5;
1518 xl_setmode(sc, *media);
1522 *media = IFM_ETHER|IFM_10_2;
1523 xl_setmode(sc, *media);
1526 case XL_XCVR_100BTX:
1528 /* Chosen by miibus */
1530 case XL_XCVR_100BFX:
1531 *media = IFM_ETHER|IFM_100_FX;
1534 device_printf(sc->xl_dev, "unknown XCVR type: %d\n",
1537 * This will probably be wrong, but it prevents
1538 * the ifmedia code from panicking.
1540 *media = IFM_ETHER|IFM_10_T;
1548 * Shutdown hardware and free up resources. This can be called any
1549 * time after the mutex has been initialized. It is called in both
1550 * the error case in attach and the normal detach case so it needs
1551 * to be careful about only freeing resources that have actually been
1555 xl_detach(device_t dev)
1557 struct xl_softc *sc;
1561 sc = device_get_softc(dev);
1564 KASSERT(mtx_initialized(&sc->xl_mtx), ("xl mutex not initialized"));
1566 #ifdef DEVICE_POLLING
1567 if (ifp && ifp->if_capenable & IFCAP_POLLING)
1568 ether_poll_deregister(ifp);
1571 if (sc->xl_flags & XL_FLAG_USE_MMIO) {
1573 res = SYS_RES_MEMORY;
1576 res = SYS_RES_IOPORT;
1579 /* These should only be active if attach succeeded */
1580 if (device_is_attached(dev)) {
1584 taskqueue_drain(taskqueue_swi, &sc->xl_task);
1585 callout_drain(&sc->xl_tick_callout);
1586 ether_ifdetach(ifp);
1589 device_delete_child(dev, sc->xl_miibus);
1590 bus_generic_detach(dev);
1591 ifmedia_removeall(&sc->ifmedia);
1593 if (sc->xl_intrhand)
1594 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand);
1596 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq);
1597 if (sc->xl_fres != NULL)
1598 bus_release_resource(dev, SYS_RES_MEMORY,
1599 XL_PCI_FUNCMEM, sc->xl_fres);
1601 bus_release_resource(dev, res, rid, sc->xl_res);
1607 bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap);
1608 bus_dma_tag_destroy(sc->xl_mtag);
1610 if (sc->xl_ldata.xl_rx_tag) {
1611 bus_dmamap_unload(sc->xl_ldata.xl_rx_tag,
1612 sc->xl_ldata.xl_rx_dmamap);
1613 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list,
1614 sc->xl_ldata.xl_rx_dmamap);
1615 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1617 if (sc->xl_ldata.xl_tx_tag) {
1618 bus_dmamap_unload(sc->xl_ldata.xl_tx_tag,
1619 sc->xl_ldata.xl_tx_dmamap);
1620 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list,
1621 sc->xl_ldata.xl_tx_dmamap);
1622 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1625 mtx_destroy(&sc->xl_mtx);
1631 * Initialize the transmit descriptors.
1634 xl_list_tx_init(struct xl_softc *sc)
1636 struct xl_chain_data *cd;
1637 struct xl_list_data *ld;
1644 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1645 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1646 error = bus_dmamap_create(sc->xl_mtag, 0,
1647 &cd->xl_tx_chain[i].xl_map);
1650 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1651 i * sizeof(struct xl_list);
1652 if (i == (XL_TX_LIST_CNT - 1))
1653 cd->xl_tx_chain[i].xl_next = NULL;
1655 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1658 cd->xl_tx_free = &cd->xl_tx_chain[0];
1659 cd->xl_tx_tail = cd->xl_tx_head = NULL;
1661 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE);
1666 * Initialize the transmit descriptors.
1669 xl_list_tx_init_90xB(struct xl_softc *sc)
1671 struct xl_chain_data *cd;
1672 struct xl_list_data *ld;
1679 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1680 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1681 error = bus_dmamap_create(sc->xl_mtag, 0,
1682 &cd->xl_tx_chain[i].xl_map);
1685 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1686 i * sizeof(struct xl_list);
1687 if (i == (XL_TX_LIST_CNT - 1))
1688 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0];
1690 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1692 cd->xl_tx_chain[i].xl_prev =
1693 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1];
1695 cd->xl_tx_chain[i].xl_prev =
1696 &cd->xl_tx_chain[i - 1];
1699 bzero(ld->xl_tx_list, XL_TX_LIST_SZ);
1700 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY);
1706 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE);
1711 * Initialize the RX descriptors and allocate mbufs for them. Note that
1712 * we arrange the descriptors in a closed ring, so that the last descriptor
1713 * points back to the first.
1716 xl_list_rx_init(struct xl_softc *sc)
1718 struct xl_chain_data *cd;
1719 struct xl_list_data *ld;
1728 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1729 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i];
1730 error = bus_dmamap_create(sc->xl_mtag, 0,
1731 &cd->xl_rx_chain[i].xl_map);
1734 error = xl_newbuf(sc, &cd->xl_rx_chain[i]);
1737 if (i == (XL_RX_LIST_CNT - 1))
1741 nextptr = ld->xl_rx_dmaaddr +
1742 next * sizeof(struct xl_list_onefrag);
1743 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next];
1744 ld->xl_rx_list[i].xl_next = htole32(nextptr);
1747 bus_dmamap_sync(ld->xl_rx_tag, ld->xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1748 cd->xl_rx_head = &cd->xl_rx_chain[0];
1754 * Initialize an RX descriptor and attach an MBUF cluster.
1755 * If we fail to do so, we need to leave the old mbuf and
1756 * the old DMA map untouched so that it can be reused.
1759 xl_newbuf(struct xl_softc *sc, struct xl_chain_onefrag *c)
1761 struct mbuf *m_new = NULL;
1763 bus_dma_segment_t segs[1];
1768 m_new = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1772 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1774 /* Force longword alignment for packet payload. */
1775 m_adj(m_new, ETHER_ALIGN);
1777 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, sc->xl_tmpmap, m_new,
1778 segs, &nseg, BUS_DMA_NOWAIT);
1781 device_printf(sc->xl_dev, "can't map mbuf (error %d)\n",
1786 ("%s: too many DMA segments (%d)", __func__, nseg));
1788 bus_dmamap_unload(sc->xl_mtag, c->xl_map);
1790 c->xl_map = sc->xl_tmpmap;
1791 sc->xl_tmpmap = map;
1793 c->xl_ptr->xl_frag.xl_len = htole32(m_new->m_len | XL_LAST_FRAG);
1794 c->xl_ptr->xl_frag.xl_addr = htole32(segs->ds_addr);
1795 c->xl_ptr->xl_status = 0;
1796 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD);
1801 xl_rx_resync(struct xl_softc *sc)
1803 struct xl_chain_onefrag *pos;
1808 pos = sc->xl_cdata.xl_rx_head;
1810 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1811 if (pos->xl_ptr->xl_status)
1816 if (i == XL_RX_LIST_CNT)
1819 sc->xl_cdata.xl_rx_head = pos;
1825 * A frame has been uploaded: pass the resulting mbuf chain up to
1826 * the higher level protocols.
1829 xl_rxeof(struct xl_softc *sc)
1832 struct ifnet *ifp = sc->xl_ifp;
1833 struct xl_chain_onefrag *cur_rx;
1840 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap,
1841 BUS_DMASYNC_POSTREAD);
1842 while ((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) {
1843 #ifdef DEVICE_POLLING
1844 if (ifp->if_capenable & IFCAP_POLLING) {
1845 if (sc->rxcycles <= 0)
1850 cur_rx = sc->xl_cdata.xl_rx_head;
1851 sc->xl_cdata.xl_rx_head = cur_rx->xl_next;
1852 total_len = rxstat & XL_RXSTAT_LENMASK;
1856 * Since we have told the chip to allow large frames,
1857 * we need to trap giant frame errors in software. We allow
1858 * a little more than the normal frame size to account for
1859 * frames with VLAN tags.
1861 if (total_len > XL_MAX_FRAMELEN)
1862 rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE);
1865 * If an error occurs, update stats, clear the
1866 * status word and leave the mbuf cluster in place:
1867 * it should simply get re-used next time this descriptor
1868 * comes up in the ring.
1870 if (rxstat & XL_RXSTAT_UP_ERROR) {
1871 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1872 cur_rx->xl_ptr->xl_status = 0;
1873 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
1874 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1879 * If the error bit was not set, the upload complete
1880 * bit should be set which means we have a valid packet.
1881 * If not, something truly strange has happened.
1883 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) {
1884 device_printf(sc->xl_dev,
1885 "bad receive status -- packet dropped\n");
1886 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1887 cur_rx->xl_ptr->xl_status = 0;
1888 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
1889 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1893 /* No errors; receive the packet. */
1894 bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map,
1895 BUS_DMASYNC_POSTREAD);
1896 m = cur_rx->xl_mbuf;
1899 * Try to conjure up a new mbuf cluster. If that
1900 * fails, it means we have an out of memory condition and
1901 * should leave the buffer in place and continue. This will
1902 * result in a lost packet, but there's little else we
1903 * can do in this situation.
1905 if (xl_newbuf(sc, cur_rx)) {
1906 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1907 cur_rx->xl_ptr->xl_status = 0;
1908 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
1909 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1912 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
1913 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1915 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
1916 m->m_pkthdr.rcvif = ifp;
1917 m->m_pkthdr.len = m->m_len = total_len;
1919 if (ifp->if_capenable & IFCAP_RXCSUM) {
1920 /* Do IP checksum checking. */
1921 if (rxstat & XL_RXSTAT_IPCKOK)
1922 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1923 if (!(rxstat & XL_RXSTAT_IPCKERR))
1924 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1925 if ((rxstat & XL_RXSTAT_TCPCOK &&
1926 !(rxstat & XL_RXSTAT_TCPCKERR)) ||
1927 (rxstat & XL_RXSTAT_UDPCKOK &&
1928 !(rxstat & XL_RXSTAT_UDPCKERR))) {
1929 m->m_pkthdr.csum_flags |=
1930 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1931 m->m_pkthdr.csum_data = 0xffff;
1936 (*ifp->if_input)(ifp, m);
1940 * If we are running from the taskqueue, the interface
1941 * might have been stopped while we were passing the last
1942 * packet up the network stack.
1944 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1949 * Handle the 'end of channel' condition. When the upload
1950 * engine hits the end of the RX ring, it will stall. This
1951 * is our cue to flush the RX ring, reload the uplist pointer
1952 * register and unstall the engine.
1953 * XXX This is actually a little goofy. With the ThunderLAN
1954 * chip, you get an interrupt when the receiver hits the end
1955 * of the receive ring, which tells you exactly when you
1956 * you need to reload the ring pointer. Here we have to
1957 * fake it. I'm mad at myself for not being clever enough
1958 * to avoid the use of a goto here.
1960 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 ||
1961 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) {
1962 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
1964 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr);
1965 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0];
1966 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
1973 * Taskqueue wrapper for xl_rxeof().
1976 xl_rxeof_task(void *arg, int pending)
1978 struct xl_softc *sc = (struct xl_softc *)arg;
1981 if (sc->xl_ifp->if_drv_flags & IFF_DRV_RUNNING)
1987 * A frame was downloaded to the chip. It's safe for us to clean up
1991 xl_txeof(struct xl_softc *sc)
1993 struct xl_chain *cur_tx;
1994 struct ifnet *ifp = sc->xl_ifp;
1999 * Go through our tx list and free mbufs for those
2000 * frames that have been uploaded. Note: the 3c905B
2001 * sets a special bit in the status word to let us
2002 * know that a frame has been downloaded, but the
2003 * original 3c900/3c905 adapters don't do that.
2004 * Consequently, we have to use a different test if
2005 * xl_type != XL_TYPE_905B.
2007 while (sc->xl_cdata.xl_tx_head != NULL) {
2008 cur_tx = sc->xl_cdata.xl_tx_head;
2010 if (CSR_READ_4(sc, XL_DOWNLIST_PTR))
2013 sc->xl_cdata.xl_tx_head = cur_tx->xl_next;
2014 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2015 BUS_DMASYNC_POSTWRITE);
2016 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2017 m_freem(cur_tx->xl_mbuf);
2018 cur_tx->xl_mbuf = NULL;
2019 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
2020 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2022 cur_tx->xl_next = sc->xl_cdata.xl_tx_free;
2023 sc->xl_cdata.xl_tx_free = cur_tx;
2026 if (sc->xl_cdata.xl_tx_head == NULL) {
2027 sc->xl_wdog_timer = 0;
2028 sc->xl_cdata.xl_tx_tail = NULL;
2030 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED ||
2031 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) {
2032 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2033 sc->xl_cdata.xl_tx_head->xl_phys);
2034 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2040 xl_txeof_90xB(struct xl_softc *sc)
2042 struct xl_chain *cur_tx = NULL;
2043 struct ifnet *ifp = sc->xl_ifp;
2048 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2049 BUS_DMASYNC_POSTREAD);
2050 idx = sc->xl_cdata.xl_tx_cons;
2051 while (idx != sc->xl_cdata.xl_tx_prod) {
2052 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2054 if (!(le32toh(cur_tx->xl_ptr->xl_status) &
2055 XL_TXSTAT_DL_COMPLETE))
2058 if (cur_tx->xl_mbuf != NULL) {
2059 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2060 BUS_DMASYNC_POSTWRITE);
2061 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2062 m_freem(cur_tx->xl_mbuf);
2063 cur_tx->xl_mbuf = NULL;
2066 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
2068 sc->xl_cdata.xl_tx_cnt--;
2069 XL_INC(idx, XL_TX_LIST_CNT);
2072 if (sc->xl_cdata.xl_tx_cnt == 0)
2073 sc->xl_wdog_timer = 0;
2074 sc->xl_cdata.xl_tx_cons = idx;
2077 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2081 * TX 'end of channel' interrupt handler. Actually, we should
2082 * only get a 'TX complete' interrupt if there's a transmit error,
2083 * so this is really TX error handler.
2086 xl_txeoc(struct xl_softc *sc)
2092 while ((txstat = CSR_READ_1(sc, XL_TX_STATUS))) {
2093 if (txstat & XL_TXSTATUS_UNDERRUN ||
2094 txstat & XL_TXSTATUS_JABBER ||
2095 txstat & XL_TXSTATUS_RECLAIM) {
2096 device_printf(sc->xl_dev,
2097 "transmission error: 0x%02x\n", txstat);
2098 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2100 if (sc->xl_type == XL_TYPE_905B) {
2101 if (sc->xl_cdata.xl_tx_cnt) {
2105 i = sc->xl_cdata.xl_tx_cons;
2106 c = &sc->xl_cdata.xl_tx_chain[i];
2107 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2109 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2110 sc->xl_wdog_timer = 5;
2113 if (sc->xl_cdata.xl_tx_head != NULL) {
2114 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2115 sc->xl_cdata.xl_tx_head->xl_phys);
2116 sc->xl_wdog_timer = 5;
2120 * Remember to set this for the
2121 * first generation 3c90X chips.
2123 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2124 if (txstat & XL_TXSTATUS_UNDERRUN &&
2125 sc->xl_tx_thresh < XL_PACKET_SIZE) {
2126 sc->xl_tx_thresh += XL_MIN_FRAMELEN;
2127 device_printf(sc->xl_dev,
2128 "tx underrun, increasing tx start threshold to %d bytes\n", sc->xl_tx_thresh);
2130 CSR_WRITE_2(sc, XL_COMMAND,
2131 XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2132 if (sc->xl_type == XL_TYPE_905B) {
2133 CSR_WRITE_2(sc, XL_COMMAND,
2134 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2136 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2137 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2139 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2140 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2143 * Write an arbitrary byte to the TX_STATUS register
2144 * to clear this interrupt/error and advance to the next.
2146 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01);
2153 struct xl_softc *sc = arg;
2154 struct ifnet *ifp = sc->xl_ifp;
2159 #ifdef DEVICE_POLLING
2160 if (ifp->if_capenable & IFCAP_POLLING) {
2167 status = CSR_READ_2(sc, XL_STATUS);
2168 if ((status & XL_INTRS) == 0 || status == 0xFFFF)
2170 CSR_WRITE_2(sc, XL_COMMAND,
2171 XL_CMD_INTR_ACK|(status & XL_INTRS));
2172 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
2175 if (status & XL_STAT_UP_COMPLETE) {
2176 if (xl_rxeof(sc) == 0) {
2177 while (xl_rx_resync(sc))
2182 if (status & XL_STAT_DOWN_COMPLETE) {
2183 if (sc->xl_type == XL_TYPE_905B)
2189 if (status & XL_STAT_TX_COMPLETE) {
2190 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
2194 if (status & XL_STAT_ADFAIL) {
2195 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2200 if (status & XL_STAT_STATSOFLOW)
2201 xl_stats_update(sc);
2204 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2205 ifp->if_drv_flags & IFF_DRV_RUNNING) {
2206 if (sc->xl_type == XL_TYPE_905B)
2207 xl_start_90xB_locked(ifp);
2209 xl_start_locked(ifp);
2215 #ifdef DEVICE_POLLING
2217 xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2219 struct xl_softc *sc = ifp->if_softc;
2223 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2224 rx_npkts = xl_poll_locked(ifp, cmd, count);
2230 xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
2232 struct xl_softc *sc = ifp->if_softc;
2237 sc->rxcycles = count;
2238 rx_npkts = xl_rxeof(sc);
2239 if (sc->xl_type == XL_TYPE_905B)
2244 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
2245 if (sc->xl_type == XL_TYPE_905B)
2246 xl_start_90xB_locked(ifp);
2248 xl_start_locked(ifp);
2251 if (cmd == POLL_AND_CHECK_STATUS) {
2254 status = CSR_READ_2(sc, XL_STATUS);
2255 if (status & XL_INTRS && status != 0xFFFF) {
2256 CSR_WRITE_2(sc, XL_COMMAND,
2257 XL_CMD_INTR_ACK|(status & XL_INTRS));
2259 if (status & XL_STAT_TX_COMPLETE) {
2260 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
2264 if (status & XL_STAT_ADFAIL) {
2265 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2269 if (status & XL_STAT_STATSOFLOW)
2270 xl_stats_update(sc);
2275 #endif /* DEVICE_POLLING */
2280 struct xl_softc *sc = xsc;
2281 struct mii_data *mii;
2285 if (sc->xl_miibus != NULL) {
2286 mii = device_get_softc(sc->xl_miibus);
2290 xl_stats_update(sc);
2291 if (xl_watchdog(sc) == EJUSTRETURN)
2294 callout_reset(&sc->xl_tick_callout, hz, xl_tick, sc);
2298 xl_stats_update(struct xl_softc *sc)
2300 struct ifnet *ifp = sc->xl_ifp;
2301 struct xl_stats xl_stats;
2307 bzero((char *)&xl_stats, sizeof(struct xl_stats));
2309 p = (u_int8_t *)&xl_stats;
2311 /* Read all the stats registers. */
2314 for (i = 0; i < 16; i++)
2315 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i);
2317 if_inc_counter(ifp, IFCOUNTER_IERRORS, xl_stats.xl_rx_overrun);
2319 if_inc_counter(ifp, IFCOUNTER_COLLISIONS,
2320 xl_stats.xl_tx_multi_collision +
2321 xl_stats.xl_tx_single_collision +
2322 xl_stats.xl_tx_late_collision);
2325 * Boomerang and cyclone chips have an extra stats counter
2326 * in window 4 (BadSSD). We have to read this too in order
2327 * to clear out all the stats registers and avoid a statsoflow
2331 CSR_READ_1(sc, XL_W4_BADSSD);
2336 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
2337 * pointers to the fragment pointers.
2340 xl_encap(struct xl_softc *sc, struct xl_chain *c, struct mbuf **m_head)
2343 struct ifnet *ifp = sc->xl_ifp;
2344 int error, i, nseg, total_len;
2349 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map, *m_head,
2350 sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT);
2352 if (error && error != EFBIG) {
2353 if_printf(ifp, "can't map mbuf (error %d)\n", error);
2358 * Handle special case: we used up all 63 fragments,
2359 * but we have more mbufs left in the chain. Copy the
2360 * data into an mbuf cluster. Note that we don't
2361 * bother clearing the values in the other fragment
2362 * pointers/counters; it wouldn't gain us anything,
2363 * and would waste cycles.
2366 m_new = m_collapse(*m_head, M_NOWAIT, XL_MAXFRAGS);
2367 if (m_new == NULL) {
2374 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map,
2375 *m_head, sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT);
2379 if_printf(ifp, "can't map mbuf (error %d)\n", error);
2384 KASSERT(nseg <= XL_MAXFRAGS,
2385 ("%s: too many DMA segments (%d)", __func__, nseg));
2391 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE);
2394 for (i = 0; i < nseg; i++) {
2395 KASSERT(sc->xl_cdata.xl_tx_segs[i].ds_len <= MCLBYTES,
2396 ("segment size too large"));
2397 c->xl_ptr->xl_frag[i].xl_addr =
2398 htole32(sc->xl_cdata.xl_tx_segs[i].ds_addr);
2399 c->xl_ptr->xl_frag[i].xl_len =
2400 htole32(sc->xl_cdata.xl_tx_segs[i].ds_len);
2401 total_len += sc->xl_cdata.xl_tx_segs[i].ds_len;
2403 c->xl_ptr->xl_frag[nseg - 1].xl_len |= htole32(XL_LAST_FRAG);
2405 if (sc->xl_type == XL_TYPE_905B) {
2406 status = XL_TXSTAT_RND_DEFEAT;
2408 #ifndef XL905B_TXCSUM_BROKEN
2409 if ((*m_head)->m_pkthdr.csum_flags) {
2410 if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP)
2411 status |= XL_TXSTAT_IPCKSUM;
2412 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP)
2413 status |= XL_TXSTAT_TCPCKSUM;
2414 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP)
2415 status |= XL_TXSTAT_UDPCKSUM;
2420 c->xl_ptr->xl_status = htole32(status);
2421 c->xl_ptr->xl_next = 0;
2423 c->xl_mbuf = *m_head;
2428 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2429 * to the mbuf data regions directly in the transmit lists. We also save a
2430 * copy of the pointers since the transmit list fragment pointers are
2431 * physical addresses.
2435 xl_start(struct ifnet *ifp)
2437 struct xl_softc *sc = ifp->if_softc;
2441 if (sc->xl_type == XL_TYPE_905B)
2442 xl_start_90xB_locked(ifp);
2444 xl_start_locked(ifp);
2450 xl_start_locked(struct ifnet *ifp)
2452 struct xl_softc *sc = ifp->if_softc;
2453 struct mbuf *m_head;
2454 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2455 struct xl_chain *prev_tx;
2460 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
2464 * Check for an available queue slot. If there are none,
2467 if (sc->xl_cdata.xl_tx_free == NULL) {
2470 if (sc->xl_cdata.xl_tx_free == NULL) {
2471 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2476 start_tx = sc->xl_cdata.xl_tx_free;
2478 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2479 sc->xl_cdata.xl_tx_free != NULL;) {
2480 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2484 /* Pick a descriptor off the free list. */
2486 cur_tx = sc->xl_cdata.xl_tx_free;
2488 /* Pack the data into the descriptor. */
2489 error = xl_encap(sc, cur_tx, &m_head);
2494 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2495 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2499 sc->xl_cdata.xl_tx_free = cur_tx->xl_next;
2500 cur_tx->xl_next = NULL;
2502 /* Chain it together. */
2504 prev->xl_next = cur_tx;
2505 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2510 * If there's a BPF listener, bounce a copy of this frame
2513 BPF_MTAP(ifp, cur_tx->xl_mbuf);
2517 * If there are no packets queued, bail.
2523 * Place the request for the upload interrupt
2524 * in the last descriptor in the chain. This way, if
2525 * we're chaining several packets at once, we'll only
2526 * get an interrupt once for the whole chain rather than
2527 * once for each packet.
2529 cur_tx->xl_ptr->xl_status |= htole32(XL_TXSTAT_DL_INTR);
2532 * Queue the packets. If the TX channel is clear, update
2533 * the downlist pointer register.
2535 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2538 if (sc->xl_cdata.xl_tx_head != NULL) {
2539 sc->xl_cdata.xl_tx_tail->xl_next = start_tx;
2540 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next =
2541 htole32(start_tx->xl_phys);
2542 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status &=
2543 htole32(~XL_TXSTAT_DL_INTR);
2544 sc->xl_cdata.xl_tx_tail = cur_tx;
2546 sc->xl_cdata.xl_tx_head = start_tx;
2547 sc->xl_cdata.xl_tx_tail = cur_tx;
2549 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2550 BUS_DMASYNC_PREWRITE);
2551 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR))
2552 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys);
2554 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2559 * Set a timeout in case the chip goes out to lunch.
2561 sc->xl_wdog_timer = 5;
2564 * XXX Under certain conditions, usually on slower machines
2565 * where interrupts may be dropped, it's possible for the
2566 * adapter to chew up all the buffers in the receive ring
2567 * and stall, without us being able to do anything about it.
2568 * To guard against this, we need to make a pass over the
2569 * RX queue to make sure there aren't any packets pending.
2570 * Doing it here means we can flush the receive ring at the
2571 * same time the chip is DMAing the transmit descriptors we
2574 * 3Com goes to some lengths to emphasize the Parallel Tasking (tm)
2575 * nature of their chips in all their marketing literature;
2576 * we may as well take advantage of it. :)
2578 taskqueue_enqueue(taskqueue_swi, &sc->xl_task);
2582 xl_start_90xB_locked(struct ifnet *ifp)
2584 struct xl_softc *sc = ifp->if_softc;
2585 struct mbuf *m_head;
2586 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2587 struct xl_chain *prev_tx;
2592 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
2596 idx = sc->xl_cdata.xl_tx_prod;
2597 start_tx = &sc->xl_cdata.xl_tx_chain[idx];
2599 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2600 sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL;) {
2601 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) {
2602 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2606 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2611 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2613 /* Pack the data into the descriptor. */
2614 error = xl_encap(sc, cur_tx, &m_head);
2619 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2620 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2624 /* Chain it together. */
2626 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2630 * If there's a BPF listener, bounce a copy of this frame
2633 BPF_MTAP(ifp, cur_tx->xl_mbuf);
2635 XL_INC(idx, XL_TX_LIST_CNT);
2636 sc->xl_cdata.xl_tx_cnt++;
2640 * If there are no packets queued, bail.
2646 * Place the request for the upload interrupt
2647 * in the last descriptor in the chain. This way, if
2648 * we're chaining several packets at once, we'll only
2649 * get an interrupt once for the whole chain rather than
2650 * once for each packet.
2652 cur_tx->xl_ptr->xl_status |= htole32(XL_TXSTAT_DL_INTR);
2654 /* Start transmission */
2655 sc->xl_cdata.xl_tx_prod = idx;
2656 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys);
2657 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2658 BUS_DMASYNC_PREWRITE);
2661 * Set a timeout in case the chip goes out to lunch.
2663 sc->xl_wdog_timer = 5;
2669 struct xl_softc *sc = xsc;
2677 xl_init_locked(struct xl_softc *sc)
2679 struct ifnet *ifp = sc->xl_ifp;
2681 struct mii_data *mii = NULL;
2685 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2688 * Cancel pending I/O and free all RX/TX buffers.
2692 /* Reset the chip to a known state. */
2695 if (sc->xl_miibus == NULL) {
2696 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2699 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2703 if (sc->xl_miibus != NULL)
2704 mii = device_get_softc(sc->xl_miibus);
2707 * Clear WOL status and disable all WOL feature as WOL
2708 * would interfere Rx operation under normal environments.
2710 if ((sc->xl_flags & XL_FLAG_WOL) != 0) {
2712 CSR_READ_2(sc, XL_W7_BM_PME);
2713 CSR_WRITE_2(sc, XL_W7_BM_PME, 0);
2715 /* Init our MAC address */
2717 for (i = 0; i < ETHER_ADDR_LEN; i++) {
2718 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i,
2719 IF_LLADDR(sc->xl_ifp)[i]);
2722 /* Clear the station mask. */
2723 for (i = 0; i < 3; i++)
2724 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0);
2726 /* Reset TX and RX. */
2727 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2729 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2732 /* Init circular RX list. */
2733 error = xl_list_rx_init(sc);
2735 device_printf(sc->xl_dev, "initialization of the rx ring failed (%d)\n",
2741 /* Init TX descriptors. */
2742 if (sc->xl_type == XL_TYPE_905B)
2743 error = xl_list_tx_init_90xB(sc);
2745 error = xl_list_tx_init(sc);
2747 device_printf(sc->xl_dev, "initialization of the tx ring failed (%d)\n",
2754 * Set the TX freethresh value.
2755 * Note that this has no effect on 3c905B "cyclone"
2756 * cards but is required for 3c900/3c905 "boomerang"
2757 * cards in order to enable the download engine.
2759 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2761 /* Set the TX start threshold for best performance. */
2762 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2765 * If this is a 3c905B, also set the tx reclaim threshold.
2766 * This helps cut down on the number of tx reclaim errors
2767 * that could happen on a busy network. The chip multiplies
2768 * the register value by 16 to obtain the actual threshold
2769 * in bytes, so we divide by 16 when setting the value here.
2770 * The existing threshold value can be examined by reading
2771 * the register at offset 9 in window 5.
2773 if (sc->xl_type == XL_TYPE_905B) {
2774 CSR_WRITE_2(sc, XL_COMMAND,
2775 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2778 /* Set RX filter bits. */
2782 * Load the address of the RX list. We have to
2783 * stall the upload engine before we can manipulate
2784 * the uplist pointer register, then unstall it when
2785 * we're finished. We also have to wait for the
2786 * stall command to complete before proceeding.
2787 * Note that we have to do this after any RX resets
2788 * have completed since the uplist register is cleared
2791 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
2793 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr);
2794 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
2797 if (sc->xl_type == XL_TYPE_905B) {
2798 /* Set polling interval */
2799 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2800 /* Load the address of the TX list */
2801 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2803 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2804 sc->xl_cdata.xl_tx_chain[0].xl_phys);
2805 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2810 * If the coax transceiver is on, make sure to enable
2811 * the DC-DC converter.
2814 if (sc->xl_xcvr == XL_XCVR_COAX)
2815 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
2817 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
2820 * increase packet size to allow reception of 802.1q or ISL packets.
2821 * For the 3c90x chip, set the 'allow large packets' bit in the MAC
2822 * control register. For 3c90xB/C chips, use the RX packet size
2826 if (sc->xl_type == XL_TYPE_905B)
2827 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE);
2830 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL);
2831 macctl |= XL_MACCTRL_ALLOW_LARGE_PACK;
2832 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl);
2835 /* Clear out the stats counters. */
2836 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
2837 xl_stats_update(sc);
2839 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE);
2840 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE);
2843 * Enable interrupts.
2845 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF);
2846 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS);
2847 #ifdef DEVICE_POLLING
2848 /* Disable interrupts if we are polling. */
2849 if (ifp->if_capenable & IFCAP_POLLING)
2850 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
2853 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS);
2854 if (sc->xl_flags & XL_FLAG_FUNCREG)
2855 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
2857 /* Set the RX early threshold */
2858 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2));
2859 CSR_WRITE_4(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY);
2861 /* Enable receiver and transmitter. */
2862 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2864 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE);
2867 /* XXX Downcall to miibus. */
2871 /* Select window 7 for normal operations. */
2874 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2875 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2877 sc->xl_wdog_timer = 0;
2878 callout_reset(&sc->xl_tick_callout, hz, xl_tick, sc);
2882 * Set media options.
2885 xl_ifmedia_upd(struct ifnet *ifp)
2887 struct xl_softc *sc = ifp->if_softc;
2888 struct ifmedia *ifm = NULL;
2889 struct mii_data *mii = NULL;
2893 if (sc->xl_miibus != NULL)
2894 mii = device_get_softc(sc->xl_miibus);
2898 ifm = &mii->mii_media;
2900 switch (IFM_SUBTYPE(ifm->ifm_media)) {
2905 xl_setmode(sc, ifm->ifm_media);
2910 if (sc->xl_media & XL_MEDIAOPT_MII ||
2911 sc->xl_media & XL_MEDIAOPT_BTX ||
2912 sc->xl_media & XL_MEDIAOPT_BT4) {
2913 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2916 xl_setmode(sc, ifm->ifm_media);
2925 * Report current media status.
2928 xl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2930 struct xl_softc *sc = ifp->if_softc;
2932 u_int16_t status = 0;
2933 struct mii_data *mii = NULL;
2937 if (sc->xl_miibus != NULL)
2938 mii = device_get_softc(sc->xl_miibus);
2941 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
2944 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK;
2945 icfg >>= XL_ICFG_CONNECTOR_BITS;
2947 ifmr->ifm_active = IFM_ETHER;
2948 ifmr->ifm_status = IFM_AVALID;
2950 if ((status & XL_MEDIASTAT_CARRIER) == 0)
2951 ifmr->ifm_status |= IFM_ACTIVE;
2955 ifmr->ifm_active = IFM_ETHER|IFM_10_T;
2956 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
2957 ifmr->ifm_active |= IFM_FDX;
2959 ifmr->ifm_active |= IFM_HDX;
2962 if (sc->xl_type == XL_TYPE_905B &&
2963 sc->xl_media == XL_MEDIAOPT_10FL) {
2964 ifmr->ifm_active = IFM_ETHER|IFM_10_FL;
2965 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
2966 ifmr->ifm_active |= IFM_FDX;
2968 ifmr->ifm_active |= IFM_HDX;
2970 ifmr->ifm_active = IFM_ETHER|IFM_10_5;
2973 ifmr->ifm_active = IFM_ETHER|IFM_10_2;
2976 * XXX MII and BTX/AUTO should be separate cases.
2979 case XL_XCVR_100BTX:
2984 ifmr->ifm_active = mii->mii_media_active;
2985 ifmr->ifm_status = mii->mii_media_status;
2988 case XL_XCVR_100BFX:
2989 ifmr->ifm_active = IFM_ETHER|IFM_100_FX;
2992 if_printf(ifp, "unknown XCVR type: %d\n", icfg);
3000 xl_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3002 struct xl_softc *sc = ifp->if_softc;
3003 struct ifreq *ifr = (struct ifreq *) data;
3004 int error = 0, mask;
3005 struct mii_data *mii = NULL;
3010 if (ifp->if_flags & IFF_UP) {
3011 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3012 (ifp->if_flags ^ sc->xl_if_flags) &
3013 (IFF_PROMISC | IFF_ALLMULTI))
3018 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3021 sc->xl_if_flags = ifp->if_flags;
3026 /* XXX Downcall from if_addmulti() possibly with locks held. */
3028 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3034 if (sc->xl_miibus != NULL)
3035 mii = device_get_softc(sc->xl_miibus);
3037 error = ifmedia_ioctl(ifp, ifr,
3038 &sc->ifmedia, command);
3040 error = ifmedia_ioctl(ifp, ifr,
3041 &mii->mii_media, command);
3044 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3045 #ifdef DEVICE_POLLING
3046 if ((mask & IFCAP_POLLING) != 0 &&
3047 (ifp->if_capabilities & IFCAP_POLLING) != 0) {
3048 ifp->if_capenable ^= IFCAP_POLLING;
3049 if ((ifp->if_capenable & IFCAP_POLLING) != 0) {
3050 error = ether_poll_register(xl_poll, ifp);
3054 /* Disable interrupts */
3055 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
3056 ifp->if_capenable |= IFCAP_POLLING;
3059 error = ether_poll_deregister(ifp);
3060 /* Enable interrupts. */
3062 CSR_WRITE_2(sc, XL_COMMAND,
3063 XL_CMD_INTR_ACK | 0xFF);
3064 CSR_WRITE_2(sc, XL_COMMAND,
3065 XL_CMD_INTR_ENB | XL_INTRS);
3066 if (sc->xl_flags & XL_FLAG_FUNCREG)
3067 bus_space_write_4(sc->xl_ftag,
3068 sc->xl_fhandle, 4, 0x8000);
3072 #endif /* DEVICE_POLLING */
3074 if ((mask & IFCAP_TXCSUM) != 0 &&
3075 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
3076 ifp->if_capenable ^= IFCAP_TXCSUM;
3077 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
3078 ifp->if_hwassist |= XL905B_CSUM_FEATURES;
3080 ifp->if_hwassist &= ~XL905B_CSUM_FEATURES;
3082 if ((mask & IFCAP_RXCSUM) != 0 &&
3083 (ifp->if_capabilities & IFCAP_RXCSUM) != 0)
3084 ifp->if_capenable ^= IFCAP_RXCSUM;
3085 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
3086 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0)
3087 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
3091 error = ether_ioctl(ifp, command, data);
3099 xl_watchdog(struct xl_softc *sc)
3101 struct ifnet *ifp = sc->xl_ifp;
3102 u_int16_t status = 0;
3107 if (sc->xl_wdog_timer == 0 || --sc->xl_wdog_timer != 0)
3113 if (sc->xl_type == XL_TYPE_905B) {
3115 if (sc->xl_cdata.xl_tx_cnt == 0)
3119 if (sc->xl_cdata.xl_tx_head == NULL)
3123 device_printf(sc->xl_dev,
3124 "watchdog timeout (missed Tx interrupts) -- recovering\n");
3128 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
3130 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
3131 device_printf(sc->xl_dev, "watchdog timeout\n");
3133 if (status & XL_MEDIASTAT_CARRIER)
3134 device_printf(sc->xl_dev,
3135 "no carrier - transceiver cable problem?\n");
3137 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3140 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
3141 if (sc->xl_type == XL_TYPE_905B)
3142 xl_start_90xB_locked(ifp);
3144 xl_start_locked(ifp);
3147 return (EJUSTRETURN);
3151 * Stop the adapter and free any mbufs allocated to the
3155 xl_stop(struct xl_softc *sc)
3158 struct ifnet *ifp = sc->xl_ifp;
3162 sc->xl_wdog_timer = 0;
3164 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE);
3165 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
3166 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB);
3167 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD);
3169 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE);
3170 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
3174 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
3176 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
3180 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH);
3181 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0);
3182 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
3183 if (sc->xl_flags & XL_FLAG_FUNCREG)
3184 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
3186 /* Stop the stats updater. */
3187 callout_stop(&sc->xl_tick_callout);
3190 * Free data in the RX lists.
3192 for (i = 0; i < XL_RX_LIST_CNT; i++) {
3193 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) {
3194 bus_dmamap_unload(sc->xl_mtag,
3195 sc->xl_cdata.xl_rx_chain[i].xl_map);
3196 bus_dmamap_destroy(sc->xl_mtag,
3197 sc->xl_cdata.xl_rx_chain[i].xl_map);
3198 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf);
3199 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL;
3202 if (sc->xl_ldata.xl_rx_list != NULL)
3203 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ);
3205 * Free the TX list buffers.
3207 for (i = 0; i < XL_TX_LIST_CNT; i++) {
3208 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) {
3209 bus_dmamap_unload(sc->xl_mtag,
3210 sc->xl_cdata.xl_tx_chain[i].xl_map);
3211 bus_dmamap_destroy(sc->xl_mtag,
3212 sc->xl_cdata.xl_tx_chain[i].xl_map);
3213 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf);
3214 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL;
3217 if (sc->xl_ldata.xl_tx_list != NULL)
3218 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ);
3220 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
3224 * Stop all chip I/O so that the kernel's probe routines don't
3225 * get confused by errant DMAs when rebooting.
3228 xl_shutdown(device_t dev)
3231 return (xl_suspend(dev));
3235 xl_suspend(device_t dev)
3237 struct xl_softc *sc;
3239 sc = device_get_softc(dev);
3250 xl_resume(device_t dev)
3252 struct xl_softc *sc;
3255 sc = device_get_softc(dev);
3260 if (ifp->if_flags & IFF_UP) {
3261 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3271 xl_setwol(struct xl_softc *sc)
3274 u_int16_t cfg, pmstat;
3276 if ((sc->xl_flags & XL_FLAG_WOL) == 0)
3281 /* Clear any pending PME events. */
3282 CSR_READ_2(sc, XL_W7_BM_PME);
3284 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
3285 cfg |= XL_BM_PME_MAGIC;
3286 CSR_WRITE_2(sc, XL_W7_BM_PME, cfg);
3288 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
3289 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE);
3291 pmstat = pci_read_config(sc->xl_dev,
3292 sc->xl_pmcap + PCIR_POWER_STATUS, 2);
3293 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
3294 pmstat |= PCIM_PSTAT_PMEENABLE;
3296 pmstat &= ~PCIM_PSTAT_PMEENABLE;
3297 pci_write_config(sc->xl_dev,
3298 sc->xl_pmcap + PCIR_POWER_STATUS, pmstat, 2);