2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1997, 1998, 1999
5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
35 #include <sys/cdefs.h>
36 __FBSDID("$FreeBSD$");
39 * 3Com 3c90x Etherlink XL PCI NIC driver
41 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI
42 * bus-master chips (3c90x cards and embedded controllers) including
45 * 3Com 3c900-TPO 10Mbps/RJ-45
46 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC
47 * 3Com 3c905-TX 10/100Mbps/RJ-45
48 * 3Com 3c905-T4 10/100Mbps/RJ-45
49 * 3Com 3c900B-TPO 10Mbps/RJ-45
50 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC
51 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC
52 * 3Com 3c900B-FL 10Mbps/Fiber-optic
53 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC
54 * 3Com 3c905B-TX 10/100Mbps/RJ-45
55 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic
56 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC)
57 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC)
58 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC)
59 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC)
60 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC)
61 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane)
62 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
63 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
64 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
65 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
66 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
67 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
68 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
69 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC)
70 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45
71 * Dell on-board 3c920 10/100Mbps/RJ-45
72 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45
73 * Dell Latitude laptop docking station embedded 3c905-TX
75 * Written by Bill Paul <wpaul@ctr.columbia.edu>
76 * Electrical Engineering Department
77 * Columbia University, New York City
80 * The 3c90x series chips use a bus-master DMA interface for transferring
81 * packets to and from the controller chip. Some of the "vortex" cards
82 * (3c59x) also supported a bus master mode, however for those chips
83 * you could only DMA packets to/from a contiguous memory buffer. For
84 * transmission this would mean copying the contents of the queued mbuf
85 * chain into an mbuf cluster and then DMAing the cluster. This extra
86 * copy would sort of defeat the purpose of the bus master support for
87 * any packet that doesn't fit into a single mbuf.
89 * By contrast, the 3c90x cards support a fragment-based bus master
90 * mode where mbuf chains can be encapsulated using TX descriptors.
91 * This is similar to other PCI chips such as the Texas Instruments
92 * ThunderLAN and the Intel 82557/82558.
94 * The "vortex" driver (if_vx.c) happens to work for the "boomerang"
95 * bus master chips because they maintain the old PIO interface for
96 * backwards compatibility, but starting with the 3c905B and the
97 * "cyclone" chips, the compatibility interface has been dropped.
98 * Since using bus master DMA is a big win, we use this driver to
99 * support the PCI "boomerang" chips even though they work with the
100 * "vortex" driver in order to obtain better performance.
103 #ifdef HAVE_KERNEL_OPTION_HEADERS
104 #include "opt_device_polling.h"
107 #include <sys/param.h>
108 #include <sys/systm.h>
109 #include <sys/sockio.h>
110 #include <sys/endian.h>
111 #include <sys/kernel.h>
112 #include <sys/malloc.h>
113 #include <sys/mbuf.h>
114 #include <sys/module.h>
115 #include <sys/socket.h>
116 #include <sys/taskqueue.h>
119 #include <net/if_var.h>
120 #include <net/if_arp.h>
121 #include <net/ethernet.h>
122 #include <net/if_dl.h>
123 #include <net/if_media.h>
124 #include <net/if_types.h>
128 #include <machine/bus.h>
129 #include <machine/resource.h>
131 #include <sys/rman.h>
133 #include <dev/mii/mii.h>
134 #include <dev/mii/mii_bitbang.h>
135 #include <dev/mii/miivar.h>
137 #include <dev/pci/pcireg.h>
138 #include <dev/pci/pcivar.h>
140 MODULE_DEPEND(xl, pci, 1, 1, 1);
141 MODULE_DEPEND(xl, ether, 1, 1, 1);
142 MODULE_DEPEND(xl, miibus, 1, 1, 1);
144 /* "device miibus" required. See GENERIC if you get errors here. */
145 #include "miibus_if.h"
147 #include <dev/xl/if_xlreg.h>
150 * TX Checksumming is disabled by default for two reasons:
151 * - TX Checksumming will occasionally produce corrupt packets
152 * - TX Checksumming seems to reduce performance
154 * Only 905B/C cards were reported to have this problem, it is possible
155 * that later chips _may_ be immune.
157 #define XL905B_TXCSUM_BROKEN 1
159 #ifdef XL905B_TXCSUM_BROKEN
160 #define XL905B_CSUM_FEATURES 0
162 #define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
166 * Various supported device vendors/types and their names.
168 static const struct xl_type xl_devs[] = {
169 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT,
170 "3Com 3c900-TPO Etherlink XL" },
171 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO,
172 "3Com 3c900-COMBO Etherlink XL" },
173 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT,
174 "3Com 3c905-TX Fast Etherlink XL" },
175 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4,
176 "3Com 3c905-T4 Fast Etherlink XL" },
177 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT,
178 "3Com 3c900B-TPO Etherlink XL" },
179 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO,
180 "3Com 3c900B-COMBO Etherlink XL" },
181 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC,
182 "3Com 3c900B-TPC Etherlink XL" },
183 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL,
184 "3Com 3c900B-FL Etherlink XL" },
185 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT,
186 "3Com 3c905B-TX Fast Etherlink XL" },
187 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4,
188 "3Com 3c905B-T4 Fast Etherlink XL" },
189 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX,
190 "3Com 3c905B-FX/SC Fast Etherlink XL" },
191 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO,
192 "3Com 3c905B-COMBO Fast Etherlink XL" },
193 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT,
194 "3Com 3c905C-TX Fast Etherlink XL" },
195 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B,
196 "3Com 3c920B-EMB Integrated Fast Etherlink XL" },
197 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B_WNM,
198 "3Com 3c920B-EMB-WNM Integrated Fast Etherlink XL" },
199 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV,
200 "3Com 3c980 Fast Etherlink XL" },
201 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV,
202 "3Com 3c980C Fast Etherlink XL" },
203 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX,
204 "3Com 3cSOHO100-TX OfficeConnect" },
205 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT,
206 "3Com 3c450-TX HomeConnect" },
207 { TC_VENDORID, TC_DEVICEID_HURRICANE_555,
208 "3Com 3c555 Fast Etherlink XL" },
209 { TC_VENDORID, TC_DEVICEID_HURRICANE_556,
210 "3Com 3c556 Fast Etherlink XL" },
211 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B,
212 "3Com 3c556B Fast Etherlink XL" },
213 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A,
214 "3Com 3c575TX Fast Etherlink XL" },
215 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B,
216 "3Com 3c575B Fast Etherlink XL" },
217 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C,
218 "3Com 3c575C Fast Etherlink XL" },
219 { TC_VENDORID, TC_DEVICEID_HURRICANE_656,
220 "3Com 3c656 Fast Etherlink XL" },
221 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B,
222 "3Com 3c656B Fast Etherlink XL" },
223 { TC_VENDORID, TC_DEVICEID_TORNADO_656C,
224 "3Com 3c656C Fast Etherlink XL" },
228 static int xl_probe(device_t);
229 static int xl_attach(device_t);
230 static int xl_detach(device_t);
232 static int xl_newbuf(struct xl_softc *, struct xl_chain_onefrag *);
233 static void xl_tick(void *);
234 static void xl_stats_update(struct xl_softc *);
235 static int xl_encap(struct xl_softc *, struct xl_chain *, struct mbuf **);
236 static int xl_rxeof(struct xl_softc *);
237 static void xl_rxeof_task(void *, int);
238 static int xl_rx_resync(struct xl_softc *);
239 static void xl_txeof(struct xl_softc *);
240 static void xl_txeof_90xB(struct xl_softc *);
241 static void xl_txeoc(struct xl_softc *);
242 static void xl_intr(void *);
243 static void xl_start(struct ifnet *);
244 static void xl_start_locked(struct ifnet *);
245 static void xl_start_90xB_locked(struct ifnet *);
246 static int xl_ioctl(struct ifnet *, u_long, caddr_t);
247 static void xl_init(void *);
248 static void xl_init_locked(struct xl_softc *);
249 static void xl_stop(struct xl_softc *);
250 static int xl_watchdog(struct xl_softc *);
251 static int xl_shutdown(device_t);
252 static int xl_suspend(device_t);
253 static int xl_resume(device_t);
254 static void xl_setwol(struct xl_softc *);
256 #ifdef DEVICE_POLLING
257 static int xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
258 static int xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count);
261 static int xl_ifmedia_upd(struct ifnet *);
262 static void xl_ifmedia_sts(struct ifnet *, struct ifmediareq *);
264 static int xl_eeprom_wait(struct xl_softc *);
265 static int xl_read_eeprom(struct xl_softc *, caddr_t, int, int, int);
267 static void xl_rxfilter(struct xl_softc *);
268 static void xl_rxfilter_90x(struct xl_softc *);
269 static void xl_rxfilter_90xB(struct xl_softc *);
270 static void xl_setcfg(struct xl_softc *);
271 static void xl_setmode(struct xl_softc *, int);
272 static void xl_reset(struct xl_softc *);
273 static int xl_list_rx_init(struct xl_softc *);
274 static int xl_list_tx_init(struct xl_softc *);
275 static int xl_list_tx_init_90xB(struct xl_softc *);
276 static void xl_wait(struct xl_softc *);
277 static void xl_mediacheck(struct xl_softc *);
278 static void xl_choose_media(struct xl_softc *sc, int *media);
279 static void xl_choose_xcvr(struct xl_softc *, int);
280 static void xl_dma_map_addr(void *, bus_dma_segment_t *, int, int);
282 static void xl_testpacket(struct xl_softc *);
285 static int xl_miibus_readreg(device_t, int, int);
286 static int xl_miibus_writereg(device_t, int, int, int);
287 static void xl_miibus_statchg(device_t);
288 static void xl_miibus_mediainit(device_t);
293 static uint32_t xl_mii_bitbang_read(device_t);
294 static void xl_mii_bitbang_write(device_t, uint32_t);
296 static const struct mii_bitbang_ops xl_mii_bitbang_ops = {
298 xl_mii_bitbang_write,
300 XL_MII_DATA, /* MII_BIT_MDO */
301 XL_MII_DATA, /* MII_BIT_MDI */
302 XL_MII_CLK, /* MII_BIT_MDC */
303 XL_MII_DIR, /* MII_BIT_DIR_HOST_PHY */
304 0, /* MII_BIT_DIR_PHY_HOST */
308 static device_method_t xl_methods[] = {
309 /* Device interface */
310 DEVMETHOD(device_probe, xl_probe),
311 DEVMETHOD(device_attach, xl_attach),
312 DEVMETHOD(device_detach, xl_detach),
313 DEVMETHOD(device_shutdown, xl_shutdown),
314 DEVMETHOD(device_suspend, xl_suspend),
315 DEVMETHOD(device_resume, xl_resume),
318 DEVMETHOD(miibus_readreg, xl_miibus_readreg),
319 DEVMETHOD(miibus_writereg, xl_miibus_writereg),
320 DEVMETHOD(miibus_statchg, xl_miibus_statchg),
321 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit),
326 static driver_t xl_driver = {
329 sizeof(struct xl_softc)
332 static devclass_t xl_devclass;
334 DRIVER_MODULE_ORDERED(xl, pci, xl_driver, xl_devclass, NULL, NULL,
336 DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, NULL, NULL);
339 xl_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
344 *paddr = segs->ds_addr;
348 * Murphy's law says that it's possible the chip can wedge and
349 * the 'command in progress' bit may never clear. Hence, we wait
350 * only a finite amount of time to avoid getting caught in an
351 * infinite loop. Normally this delay routine would be a macro,
352 * but it isn't called during normal operation so we can afford
353 * to make it a function. Suppress warning when card gone.
356 xl_wait(struct xl_softc *sc)
360 for (i = 0; i < XL_TIMEOUT; i++) {
361 if ((CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY) == 0)
365 if (i == XL_TIMEOUT && bus_child_present(sc->xl_dev))
366 device_printf(sc->xl_dev, "command never completed!\n");
370 * MII access routines are provided for adapters with external
371 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in
372 * autoneg logic that's faked up to look like a PHY (3c905B-TX).
373 * Note: if you don't perform the MDIO operations just right,
374 * it's possible to end up with code that works correctly with
375 * some chips/CPUs/processor speeds/bus speeds/etc but not
380 * Read the MII serial port for the MII bit-bang module.
383 xl_mii_bitbang_read(device_t dev)
388 sc = device_get_softc(dev);
390 /* We're already in window 4. */
391 val = CSR_READ_2(sc, XL_W4_PHY_MGMT);
392 CSR_BARRIER(sc, XL_W4_PHY_MGMT, 2,
393 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
399 * Write the MII serial port for the MII bit-bang module.
402 xl_mii_bitbang_write(device_t dev, uint32_t val)
406 sc = device_get_softc(dev);
408 /* We're already in window 4. */
409 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, val);
410 CSR_BARRIER(sc, XL_W4_PHY_MGMT, 2,
411 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
415 xl_miibus_readreg(device_t dev, int phy, int reg)
419 sc = device_get_softc(dev);
421 /* Select the window 4. */
424 return (mii_bitbang_readreg(dev, &xl_mii_bitbang_ops, phy, reg));
428 xl_miibus_writereg(device_t dev, int phy, int reg, int data)
432 sc = device_get_softc(dev);
434 /* Select the window 4. */
437 mii_bitbang_writereg(dev, &xl_mii_bitbang_ops, phy, reg, data);
443 xl_miibus_statchg(device_t dev)
446 struct mii_data *mii;
449 sc = device_get_softc(dev);
450 mii = device_get_softc(sc->xl_miibus);
454 /* Set ASIC's duplex mode to match the PHY. */
456 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL);
457 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
458 macctl |= XL_MACCTRL_DUPLEX;
459 if (sc->xl_type == XL_TYPE_905B) {
460 if ((IFM_OPTIONS(mii->mii_media_active) &
461 IFM_ETH_RXPAUSE) != 0)
462 macctl |= XL_MACCTRL_FLOW_CONTROL_ENB;
464 macctl &= ~XL_MACCTRL_FLOW_CONTROL_ENB;
467 macctl &= ~XL_MACCTRL_DUPLEX;
468 if (sc->xl_type == XL_TYPE_905B)
469 macctl &= ~XL_MACCTRL_FLOW_CONTROL_ENB;
471 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl);
475 * Special support for the 3c905B-COMBO. This card has 10/100 support
476 * plus BNC and AUI ports. This means we will have both an miibus attached
477 * plus some non-MII media settings. In order to allow this, we have to
478 * add the extra media to the miibus's ifmedia struct, but we can't do
479 * that during xl_attach() because the miibus hasn't been attached yet.
480 * So instead, we wait until the miibus probe/attach is done, at which
481 * point we will get a callback telling is that it's safe to add our
485 xl_miibus_mediainit(device_t dev)
488 struct mii_data *mii;
491 sc = device_get_softc(dev);
492 mii = device_get_softc(sc->xl_miibus);
493 ifm = &mii->mii_media;
495 if (sc->xl_media & (XL_MEDIAOPT_AUI | XL_MEDIAOPT_10FL)) {
497 * Check for a 10baseFL board in disguise.
499 if (sc->xl_type == XL_TYPE_905B &&
500 sc->xl_media == XL_MEDIAOPT_10FL) {
502 device_printf(sc->xl_dev, "found 10baseFL\n");
503 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL, 0, NULL);
504 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL|IFM_HDX, 0,
506 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
508 IFM_ETHER | IFM_10_FL | IFM_FDX, 0, NULL);
511 device_printf(sc->xl_dev, "found AUI\n");
512 ifmedia_add(ifm, IFM_ETHER | IFM_10_5, 0, NULL);
516 if (sc->xl_media & XL_MEDIAOPT_BNC) {
518 device_printf(sc->xl_dev, "found BNC\n");
519 ifmedia_add(ifm, IFM_ETHER | IFM_10_2, 0, NULL);
524 * The EEPROM is slow: give it time to come ready after issuing
528 xl_eeprom_wait(struct xl_softc *sc)
532 for (i = 0; i < 100; i++) {
533 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY)
540 device_printf(sc->xl_dev, "eeprom failed to come ready\n");
548 * Read a sequence of words from the EEPROM. Note that ethernet address
549 * data is stored in the EEPROM in network byte order.
552 xl_read_eeprom(struct xl_softc *sc, caddr_t dest, int off, int cnt, int swap)
555 u_int16_t word = 0, *ptr;
557 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F))
558 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F)
560 * XXX: WARNING! DANGER!
561 * It's easy to accidentally overwrite the rom content!
562 * Note: the 3c575 uses 8bit EEPROM offsets.
566 if (xl_eeprom_wait(sc))
569 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30)
572 for (i = 0; i < cnt; i++) {
573 if (sc->xl_flags & XL_FLAG_8BITROM)
574 CSR_WRITE_2(sc, XL_W0_EE_CMD,
575 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i));
577 CSR_WRITE_2(sc, XL_W0_EE_CMD,
578 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i));
579 err = xl_eeprom_wait(sc);
582 word = CSR_READ_2(sc, XL_W0_EE_DATA);
583 ptr = (u_int16_t *)(dest + (i * 2));
590 return (err ? 1 : 0);
594 xl_rxfilter(struct xl_softc *sc)
597 if (sc->xl_type == XL_TYPE_905B)
598 xl_rxfilter_90xB(sc);
604 * NICs older than the 3c905B have only one multicast option, which
605 * is to enable reception of all multicast frames.
608 xl_rxfilter_90x(struct xl_softc *sc)
611 struct ifmultiaddr *ifma;
619 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
620 rxfilt &= ~(XL_RXFILTER_ALLFRAMES | XL_RXFILTER_ALLMULTI |
621 XL_RXFILTER_BROADCAST | XL_RXFILTER_INDIVIDUAL);
623 /* Set the individual bit to receive frames for this host only. */
624 rxfilt |= XL_RXFILTER_INDIVIDUAL;
625 /* Set capture broadcast bit to capture broadcast frames. */
626 if (ifp->if_flags & IFF_BROADCAST)
627 rxfilt |= XL_RXFILTER_BROADCAST;
629 /* If we want promiscuous mode, set the allframes bit. */
630 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) {
631 if (ifp->if_flags & IFF_PROMISC)
632 rxfilt |= XL_RXFILTER_ALLFRAMES;
633 if (ifp->if_flags & IFF_ALLMULTI)
634 rxfilt |= XL_RXFILTER_ALLMULTI;
637 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
638 if (ifma->ifma_addr->sa_family != AF_LINK)
640 rxfilt |= XL_RXFILTER_ALLMULTI;
643 if_maddr_runlock(ifp);
646 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT);
651 * 3c905B adapters have a hash filter that we can program.
654 xl_rxfilter_90xB(struct xl_softc *sc)
657 struct ifmultiaddr *ifma;
667 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
668 rxfilt &= ~(XL_RXFILTER_ALLFRAMES | XL_RXFILTER_ALLMULTI |
669 XL_RXFILTER_BROADCAST | XL_RXFILTER_INDIVIDUAL |
670 XL_RXFILTER_MULTIHASH);
672 /* Set the individual bit to receive frames for this host only. */
673 rxfilt |= XL_RXFILTER_INDIVIDUAL;
674 /* Set capture broadcast bit to capture broadcast frames. */
675 if (ifp->if_flags & IFF_BROADCAST)
676 rxfilt |= XL_RXFILTER_BROADCAST;
678 /* If we want promiscuous mode, set the allframes bit. */
679 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) {
680 if (ifp->if_flags & IFF_PROMISC)
681 rxfilt |= XL_RXFILTER_ALLFRAMES;
682 if (ifp->if_flags & IFF_ALLMULTI)
683 rxfilt |= XL_RXFILTER_ALLMULTI;
685 /* First, zot all the existing hash bits. */
686 for (i = 0; i < XL_HASHFILT_SIZE; i++)
687 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH | i);
689 /* Now program new ones. */
692 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
693 if (ifma->ifma_addr->sa_family != AF_LINK)
696 * Note: the 3c905B currently only supports a 64-bit
697 * hash table, which means we really only need 6 bits,
698 * but the manual indicates that future chip revisions
699 * will have a 256-bit hash table, hence the routine
700 * is set up to calculate 8 bits of position info in
701 * case we need it some day.
702 * Note II, The Sequel: _CURRENT_ versions of the
703 * 3c905B have a 256 bit hash table. This means we have
704 * to use all 8 bits regardless. On older cards, the
705 * upper 2 bits will be ignored. Grrrr....
707 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
708 ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF;
709 CSR_WRITE_2(sc, XL_COMMAND,
710 h | XL_CMD_RX_SET_HASH | XL_HASH_SET);
713 if_maddr_runlock(ifp);
715 rxfilt |= XL_RXFILTER_MULTIHASH;
718 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT);
723 xl_setcfg(struct xl_softc *sc)
727 /*XL_LOCK_ASSERT(sc);*/
730 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
731 icfg &= ~XL_ICFG_CONNECTOR_MASK;
732 if (sc->xl_media & XL_MEDIAOPT_MII ||
733 sc->xl_media & XL_MEDIAOPT_BT4)
734 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS);
735 if (sc->xl_media & XL_MEDIAOPT_BTX)
736 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS);
738 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
739 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
743 xl_setmode(struct xl_softc *sc, int media)
747 char *pmsg = "", *dmsg = "";
752 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
754 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
756 if (sc->xl_media & XL_MEDIAOPT_BT) {
757 if (IFM_SUBTYPE(media) == IFM_10_T) {
758 pmsg = "10baseT transceiver";
759 sc->xl_xcvr = XL_XCVR_10BT;
760 icfg &= ~XL_ICFG_CONNECTOR_MASK;
761 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS);
762 mediastat |= XL_MEDIASTAT_LINKBEAT |
763 XL_MEDIASTAT_JABGUARD;
764 mediastat &= ~XL_MEDIASTAT_SQEENB;
768 if (sc->xl_media & XL_MEDIAOPT_BFX) {
769 if (IFM_SUBTYPE(media) == IFM_100_FX) {
770 pmsg = "100baseFX port";
771 sc->xl_xcvr = XL_XCVR_100BFX;
772 icfg &= ~XL_ICFG_CONNECTOR_MASK;
773 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS);
774 mediastat |= XL_MEDIASTAT_LINKBEAT;
775 mediastat &= ~XL_MEDIASTAT_SQEENB;
779 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
780 if (IFM_SUBTYPE(media) == IFM_10_5) {
782 sc->xl_xcvr = XL_XCVR_AUI;
783 icfg &= ~XL_ICFG_CONNECTOR_MASK;
784 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
785 mediastat &= ~(XL_MEDIASTAT_LINKBEAT |
786 XL_MEDIASTAT_JABGUARD);
787 mediastat |= ~XL_MEDIASTAT_SQEENB;
789 if (IFM_SUBTYPE(media) == IFM_10_FL) {
790 pmsg = "10baseFL transceiver";
791 sc->xl_xcvr = XL_XCVR_AUI;
792 icfg &= ~XL_ICFG_CONNECTOR_MASK;
793 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
794 mediastat &= ~(XL_MEDIASTAT_LINKBEAT |
795 XL_MEDIASTAT_JABGUARD);
796 mediastat |= ~XL_MEDIASTAT_SQEENB;
800 if (sc->xl_media & XL_MEDIAOPT_BNC) {
801 if (IFM_SUBTYPE(media) == IFM_10_2) {
803 sc->xl_xcvr = XL_XCVR_COAX;
804 icfg &= ~XL_ICFG_CONNECTOR_MASK;
805 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS);
806 mediastat &= ~(XL_MEDIASTAT_LINKBEAT |
807 XL_MEDIASTAT_JABGUARD | XL_MEDIASTAT_SQEENB);
811 if ((media & IFM_GMASK) == IFM_FDX ||
812 IFM_SUBTYPE(media) == IFM_100_FX) {
815 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
819 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
820 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
823 if (IFM_SUBTYPE(media) == IFM_10_2)
824 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
826 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
828 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
830 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat);
835 device_printf(sc->xl_dev, "selecting %s, %s duplex\n", pmsg, dmsg);
839 xl_reset(struct xl_softc *sc)
846 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET |
847 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ?
848 XL_RESETOPT_DISADVFD:0));
851 * If we're using memory mapped register mode, pause briefly
852 * after issuing the reset command before trying to access any
853 * other registers. With my 3c575C CardBus card, failing to do
854 * this results in the system locking up while trying to poll
855 * the command busy bit in the status register.
857 if (sc->xl_flags & XL_FLAG_USE_MMIO)
860 for (i = 0; i < XL_TIMEOUT; i++) {
862 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
867 device_printf(sc->xl_dev, "reset didn't complete\n");
869 /* Reset TX and RX. */
870 /* Note: the RX reset takes an absurd amount of time
871 * on newer versions of the Tornado chips such as those
872 * on the 3c905CX and newer 3c908C cards. We wait an
873 * extra amount of time so that xl_wait() doesn't complain
874 * and annoy the users.
876 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
879 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
882 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR ||
883 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) {
885 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS,
886 CSR_READ_2(sc, XL_W2_RESET_OPTIONS) |
887 ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR) ?
888 XL_RESETOPT_INVERT_LED : 0) |
889 ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR) ?
890 XL_RESETOPT_INVERT_MII : 0));
893 /* Wait a little while for the chip to get its brains in order. */
898 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device
899 * IDs against our list and return a device name if we find a match.
902 xl_probe(device_t dev)
904 const struct xl_type *t;
908 while (t->xl_name != NULL) {
909 if ((pci_get_vendor(dev) == t->xl_vid) &&
910 (pci_get_device(dev) == t->xl_did)) {
911 device_set_desc(dev, t->xl_name);
912 return (BUS_PROBE_DEFAULT);
921 * This routine is a kludge to work around possible hardware faults
922 * or manufacturing defects that can cause the media options register
923 * (or reset options register, as it's called for the first generation
924 * 3c90x adapters) to return an incorrect result. I have encountered
925 * one Dell Latitude laptop docking station with an integrated 3c905-TX
926 * which doesn't have any of the 'mediaopt' bits set. This screws up
927 * the attach routine pretty badly because it doesn't know what media
928 * to look for. If we find ourselves in this predicament, this routine
929 * will try to guess the media options values and warn the user of a
930 * possible manufacturing defect with his adapter/system/whatever.
933 xl_mediacheck(struct xl_softc *sc)
937 * If some of the media options bits are set, assume they are
938 * correct. If not, try to figure it out down below.
939 * XXX I should check for 10baseFL, but I don't have an adapter
942 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) {
944 * Check the XCVR value. If it's not in the normal range
945 * of values, we need to fake it up here.
947 if (sc->xl_xcvr <= XL_XCVR_AUTO)
950 device_printf(sc->xl_dev,
951 "bogus xcvr value in EEPROM (%x)\n", sc->xl_xcvr);
952 device_printf(sc->xl_dev,
953 "choosing new default based on card type\n");
956 if (sc->xl_type == XL_TYPE_905B &&
957 sc->xl_media & XL_MEDIAOPT_10FL)
959 device_printf(sc->xl_dev,
960 "WARNING: no media options bits set in the media options register!!\n");
961 device_printf(sc->xl_dev,
962 "this could be a manufacturing defect in your adapter or system\n");
963 device_printf(sc->xl_dev,
964 "attempting to guess media type; you should probably consult your vendor\n");
967 xl_choose_xcvr(sc, 1);
971 xl_choose_xcvr(struct xl_softc *sc, int verbose)
976 * Read the device ID from the EEPROM.
977 * This is what's loaded into the PCI device ID register, so it has
978 * to be correct otherwise we wouldn't have gotten this far.
980 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0);
983 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */
984 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */
985 sc->xl_media = XL_MEDIAOPT_BT;
986 sc->xl_xcvr = XL_XCVR_10BT;
988 device_printf(sc->xl_dev,
989 "guessing 10BaseT transceiver\n");
991 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */
992 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */
993 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
994 sc->xl_xcvr = XL_XCVR_10BT;
996 device_printf(sc->xl_dev,
997 "guessing COMBO (AUI/BNC/TP)\n");
999 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */
1000 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC;
1001 sc->xl_xcvr = XL_XCVR_10BT;
1003 device_printf(sc->xl_dev, "guessing TPC (BNC/TP)\n");
1005 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */
1006 sc->xl_media = XL_MEDIAOPT_10FL;
1007 sc->xl_xcvr = XL_XCVR_AUI;
1009 device_printf(sc->xl_dev, "guessing 10baseFL\n");
1011 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */
1012 case TC_DEVICEID_HURRICANE_555: /* 3c555 */
1013 case TC_DEVICEID_HURRICANE_556: /* 3c556 */
1014 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */
1015 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */
1016 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */
1017 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */
1018 case TC_DEVICEID_HURRICANE_656: /* 3c656 */
1019 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */
1020 case TC_DEVICEID_TORNADO_656C: /* 3c656C */
1021 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */
1022 case TC_DEVICEID_TORNADO_10_100BT_920B_WNM: /* 3c920B-EMB-WNM */
1023 sc->xl_media = XL_MEDIAOPT_MII;
1024 sc->xl_xcvr = XL_XCVR_MII;
1026 device_printf(sc->xl_dev, "guessing MII\n");
1028 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */
1029 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */
1030 sc->xl_media = XL_MEDIAOPT_BT4;
1031 sc->xl_xcvr = XL_XCVR_MII;
1033 device_printf(sc->xl_dev, "guessing 100baseT4/MII\n");
1035 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */
1036 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */
1037 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */
1038 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */
1039 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */
1040 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */
1041 sc->xl_media = XL_MEDIAOPT_BTX;
1042 sc->xl_xcvr = XL_XCVR_AUTO;
1044 device_printf(sc->xl_dev, "guessing 10/100 internal\n");
1046 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */
1047 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1048 sc->xl_xcvr = XL_XCVR_AUTO;
1050 device_printf(sc->xl_dev,
1051 "guessing 10/100 plus BNC/AUI\n");
1054 device_printf(sc->xl_dev,
1055 "unknown device ID: %x -- defaulting to 10baseT\n", devid);
1056 sc->xl_media = XL_MEDIAOPT_BT;
1062 * Attach the interface. Allocate softc structures, do ifmedia
1063 * setup and ethernet/BPF attach.
1066 xl_attach(device_t dev)
1068 u_char eaddr[ETHER_ADDR_LEN];
1069 u_int16_t sinfo2, xcvr[2];
1070 struct xl_softc *sc;
1073 int error = 0, phy, rid, res, unit;
1076 sc = device_get_softc(dev);
1079 unit = device_get_unit(dev);
1081 mtx_init(&sc->xl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1083 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts);
1085 did = pci_get_device(dev);
1088 if (did == TC_DEVICEID_HURRICANE_555)
1089 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK;
1090 if (did == TC_DEVICEID_HURRICANE_556 ||
1091 did == TC_DEVICEID_HURRICANE_556B)
1092 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK |
1093 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET |
1094 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR;
1095 if (did == TC_DEVICEID_HURRICANE_555 ||
1096 did == TC_DEVICEID_HURRICANE_556)
1097 sc->xl_flags |= XL_FLAG_8BITROM;
1098 if (did == TC_DEVICEID_HURRICANE_556B)
1099 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR;
1101 if (did == TC_DEVICEID_HURRICANE_575B ||
1102 did == TC_DEVICEID_HURRICANE_575C ||
1103 did == TC_DEVICEID_HURRICANE_656B ||
1104 did == TC_DEVICEID_TORNADO_656C)
1105 sc->xl_flags |= XL_FLAG_FUNCREG;
1106 if (did == TC_DEVICEID_HURRICANE_575A ||
1107 did == TC_DEVICEID_HURRICANE_575B ||
1108 did == TC_DEVICEID_HURRICANE_575C ||
1109 did == TC_DEVICEID_HURRICANE_656B ||
1110 did == TC_DEVICEID_TORNADO_656C)
1111 sc->xl_flags |= XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 |
1113 if (did == TC_DEVICEID_HURRICANE_656)
1114 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK;
1115 if (did == TC_DEVICEID_HURRICANE_575B)
1116 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR;
1117 if (did == TC_DEVICEID_HURRICANE_575C)
1118 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1119 if (did == TC_DEVICEID_TORNADO_656C)
1120 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1121 if (did == TC_DEVICEID_HURRICANE_656 ||
1122 did == TC_DEVICEID_HURRICANE_656B)
1123 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR |
1124 XL_FLAG_INVERT_LED_PWR;
1125 if (did == TC_DEVICEID_TORNADO_10_100BT_920B ||
1126 did == TC_DEVICEID_TORNADO_10_100BT_920B_WNM)
1127 sc->xl_flags |= XL_FLAG_PHYOK;
1130 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */
1131 case TC_DEVICEID_HURRICANE_575A:
1132 case TC_DEVICEID_HURRICANE_575B:
1133 case TC_DEVICEID_HURRICANE_575C:
1134 sc->xl_flags |= XL_FLAG_NO_MMIO;
1141 * Map control/status registers.
1143 pci_enable_busmaster(dev);
1145 if ((sc->xl_flags & XL_FLAG_NO_MMIO) == 0) {
1147 res = SYS_RES_MEMORY;
1149 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE);
1152 if (sc->xl_res != NULL) {
1153 sc->xl_flags |= XL_FLAG_USE_MMIO;
1155 device_printf(dev, "using memory mapped I/O\n");
1158 res = SYS_RES_IOPORT;
1159 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE);
1160 if (sc->xl_res == NULL) {
1161 device_printf(dev, "couldn't map ports/memory\n");
1166 device_printf(dev, "using port I/O\n");
1169 sc->xl_btag = rman_get_bustag(sc->xl_res);
1170 sc->xl_bhandle = rman_get_bushandle(sc->xl_res);
1172 if (sc->xl_flags & XL_FLAG_FUNCREG) {
1173 rid = XL_PCI_FUNCMEM;
1174 sc->xl_fres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1177 if (sc->xl_fres == NULL) {
1178 device_printf(dev, "couldn't map funcreg memory\n");
1183 sc->xl_ftag = rman_get_bustag(sc->xl_fres);
1184 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres);
1187 /* Allocate interrupt */
1189 sc->xl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1190 RF_SHAREABLE | RF_ACTIVE);
1191 if (sc->xl_irq == NULL) {
1192 device_printf(dev, "couldn't map interrupt\n");
1197 /* Initialize interface name. */
1198 ifp = sc->xl_ifp = if_alloc(IFT_ETHER);
1200 device_printf(dev, "can not if_alloc()\n");
1205 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1207 /* Reset the adapter. */
1213 * Get station address from the EEPROM.
1215 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) {
1216 device_printf(dev, "failed to read station address\n");
1221 callout_init_mtx(&sc->xl_tick_callout, &sc->xl_mtx, 0);
1222 TASK_INIT(&sc->xl_task, 0, xl_rxeof_task, sc);
1225 * Now allocate a tag for the DMA descriptor lists and a chunk
1226 * of DMA-able memory based on the tag. Also obtain the DMA
1227 * addresses of the RX and TX ring, which we'll need later.
1228 * All of our lists are allocated as a contiguous block
1231 error = bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0,
1232 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1233 XL_RX_LIST_SZ, 1, XL_RX_LIST_SZ, 0, NULL, NULL,
1234 &sc->xl_ldata.xl_rx_tag);
1236 device_printf(dev, "failed to allocate rx dma tag\n");
1240 error = bus_dmamem_alloc(sc->xl_ldata.xl_rx_tag,
1241 (void **)&sc->xl_ldata.xl_rx_list, BUS_DMA_NOWAIT |
1242 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->xl_ldata.xl_rx_dmamap);
1244 device_printf(dev, "no memory for rx list buffers!\n");
1245 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1246 sc->xl_ldata.xl_rx_tag = NULL;
1250 error = bus_dmamap_load(sc->xl_ldata.xl_rx_tag,
1251 sc->xl_ldata.xl_rx_dmamap, sc->xl_ldata.xl_rx_list,
1252 XL_RX_LIST_SZ, xl_dma_map_addr,
1253 &sc->xl_ldata.xl_rx_dmaaddr, BUS_DMA_NOWAIT);
1255 device_printf(dev, "cannot get dma address of the rx ring!\n");
1256 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list,
1257 sc->xl_ldata.xl_rx_dmamap);
1258 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1259 sc->xl_ldata.xl_rx_tag = NULL;
1263 error = bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0,
1264 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1265 XL_TX_LIST_SZ, 1, XL_TX_LIST_SZ, 0, NULL, NULL,
1266 &sc->xl_ldata.xl_tx_tag);
1268 device_printf(dev, "failed to allocate tx dma tag\n");
1272 error = bus_dmamem_alloc(sc->xl_ldata.xl_tx_tag,
1273 (void **)&sc->xl_ldata.xl_tx_list, BUS_DMA_NOWAIT |
1274 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->xl_ldata.xl_tx_dmamap);
1276 device_printf(dev, "no memory for list buffers!\n");
1277 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1278 sc->xl_ldata.xl_tx_tag = NULL;
1282 error = bus_dmamap_load(sc->xl_ldata.xl_tx_tag,
1283 sc->xl_ldata.xl_tx_dmamap, sc->xl_ldata.xl_tx_list,
1284 XL_TX_LIST_SZ, xl_dma_map_addr,
1285 &sc->xl_ldata.xl_tx_dmaaddr, BUS_DMA_NOWAIT);
1287 device_printf(dev, "cannot get dma address of the tx ring!\n");
1288 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list,
1289 sc->xl_ldata.xl_tx_dmamap);
1290 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1291 sc->xl_ldata.xl_tx_tag = NULL;
1296 * Allocate a DMA tag for the mapping of mbufs.
1298 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
1299 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1300 MCLBYTES * XL_MAXFRAGS, XL_MAXFRAGS, MCLBYTES, 0, NULL,
1301 NULL, &sc->xl_mtag);
1303 device_printf(dev, "failed to allocate mbuf dma tag\n");
1307 /* We need a spare DMA map for the RX ring. */
1308 error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap);
1313 * Figure out the card type. 3c905B adapters have the
1314 * 'supportsNoTxLength' bit set in the capabilities
1315 * word in the EEPROM.
1316 * Note: my 3c575C CardBus card lies. It returns a value
1317 * of 0x1578 for its capabilities word, which is somewhat
1318 * nonsensical. Another way to distinguish a 3c90x chip
1319 * from a 3c90xB/C chip is to check for the 'supportsLargePackets'
1320 * bit. This will only be set for 3c90x boomerage chips.
1322 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0);
1323 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH ||
1324 !(sc->xl_caps & XL_CAPS_LARGE_PKTS))
1325 sc->xl_type = XL_TYPE_905B;
1327 sc->xl_type = XL_TYPE_90X;
1329 /* Check availability of WOL. */
1330 if ((sc->xl_caps & XL_CAPS_PWRMGMT) != 0 &&
1331 pci_find_cap(dev, PCIY_PMG, &pmcap) == 0) {
1332 sc->xl_pmcap = pmcap;
1333 sc->xl_flags |= XL_FLAG_WOL;
1335 xl_read_eeprom(sc, (caddr_t)&sinfo2, XL_EE_SOFTINFO2, 1, 0);
1336 if ((sinfo2 & XL_SINFO2_AUX_WOL_CON) == 0 && bootverbose)
1338 "No auxiliary remote wakeup connector!\n");
1341 /* Set the TX start threshold for best performance. */
1342 sc->xl_tx_thresh = XL_MIN_FRAMELEN;
1344 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1345 ifp->if_ioctl = xl_ioctl;
1346 ifp->if_capabilities = IFCAP_VLAN_MTU;
1347 if (sc->xl_type == XL_TYPE_905B) {
1348 ifp->if_hwassist = XL905B_CSUM_FEATURES;
1349 #ifdef XL905B_TXCSUM_BROKEN
1350 ifp->if_capabilities |= IFCAP_RXCSUM;
1352 ifp->if_capabilities |= IFCAP_HWCSUM;
1355 if ((sc->xl_flags & XL_FLAG_WOL) != 0)
1356 ifp->if_capabilities |= IFCAP_WOL_MAGIC;
1357 ifp->if_capenable = ifp->if_capabilities;
1358 #ifdef DEVICE_POLLING
1359 ifp->if_capabilities |= IFCAP_POLLING;
1361 ifp->if_start = xl_start;
1362 ifp->if_init = xl_init;
1363 IFQ_SET_MAXLEN(&ifp->if_snd, XL_TX_LIST_CNT - 1);
1364 ifp->if_snd.ifq_drv_maxlen = XL_TX_LIST_CNT - 1;
1365 IFQ_SET_READY(&ifp->if_snd);
1368 * Now we have to see what sort of media we have.
1369 * This includes probing for an MII interace and a
1373 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT);
1375 device_printf(dev, "media options word: %x\n", sc->xl_media);
1377 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0);
1378 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16;
1379 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK;
1380 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS;
1384 if (sc->xl_media & XL_MEDIAOPT_MII ||
1385 sc->xl_media & XL_MEDIAOPT_BTX ||
1386 sc->xl_media & XL_MEDIAOPT_BT4) {
1388 device_printf(dev, "found MII/AUTO\n");
1391 * Attach PHYs only at MII address 24 if !XL_FLAG_PHYOK.
1392 * This is to guard against problems with certain 3Com ASIC
1393 * revisions that incorrectly map the internal transceiver
1394 * control registers at all MII addresses.
1397 if ((sc->xl_flags & XL_FLAG_PHYOK) == 0)
1399 error = mii_attach(dev, &sc->xl_miibus, ifp, xl_ifmedia_upd,
1400 xl_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY,
1401 sc->xl_type == XL_TYPE_905B ? MIIF_DOPAUSE : 0);
1403 device_printf(dev, "attaching PHYs failed\n");
1410 * Sanity check. If the user has selected "auto" and this isn't
1411 * a 10/100 card of some kind, we need to force the transceiver
1412 * type to something sane.
1414 if (sc->xl_xcvr == XL_XCVR_AUTO)
1415 xl_choose_xcvr(sc, bootverbose);
1420 if (sc->xl_media & XL_MEDIAOPT_BT) {
1422 device_printf(dev, "found 10baseT\n");
1423 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1424 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
1425 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1426 ifmedia_add(&sc->ifmedia,
1427 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1430 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
1432 * Check for a 10baseFL board in disguise.
1434 if (sc->xl_type == XL_TYPE_905B &&
1435 sc->xl_media == XL_MEDIAOPT_10FL) {
1437 device_printf(dev, "found 10baseFL\n");
1438 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL);
1439 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX,
1441 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1442 ifmedia_add(&sc->ifmedia,
1443 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL);
1446 device_printf(dev, "found AUI\n");
1447 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
1451 if (sc->xl_media & XL_MEDIAOPT_BNC) {
1453 device_printf(dev, "found BNC\n");
1454 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL);
1457 if (sc->xl_media & XL_MEDIAOPT_BFX) {
1459 device_printf(dev, "found 100baseFX\n");
1460 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL);
1463 media = IFM_ETHER|IFM_100_TX|IFM_FDX;
1464 xl_choose_media(sc, &media);
1466 if (sc->xl_miibus == NULL)
1467 ifmedia_set(&sc->ifmedia, media);
1470 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) {
1472 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS);
1476 * Call MI attach routine.
1478 ether_ifattach(ifp, eaddr);
1480 error = bus_setup_intr(dev, sc->xl_irq, INTR_TYPE_NET | INTR_MPSAFE,
1481 NULL, xl_intr, sc, &sc->xl_intrhand);
1483 device_printf(dev, "couldn't set up irq\n");
1484 ether_ifdetach(ifp);
1496 * Choose a default media.
1497 * XXX This is a leaf function only called by xl_attach() and
1498 * acquires/releases the non-recursible driver mutex to
1499 * satisfy lock assertions.
1502 xl_choose_media(struct xl_softc *sc, int *media)
1507 switch (sc->xl_xcvr) {
1509 *media = IFM_ETHER|IFM_10_T;
1510 xl_setmode(sc, *media);
1513 if (sc->xl_type == XL_TYPE_905B &&
1514 sc->xl_media == XL_MEDIAOPT_10FL) {
1515 *media = IFM_ETHER|IFM_10_FL;
1516 xl_setmode(sc, *media);
1518 *media = IFM_ETHER|IFM_10_5;
1519 xl_setmode(sc, *media);
1523 *media = IFM_ETHER|IFM_10_2;
1524 xl_setmode(sc, *media);
1527 case XL_XCVR_100BTX:
1529 /* Chosen by miibus */
1531 case XL_XCVR_100BFX:
1532 *media = IFM_ETHER|IFM_100_FX;
1535 device_printf(sc->xl_dev, "unknown XCVR type: %d\n",
1538 * This will probably be wrong, but it prevents
1539 * the ifmedia code from panicking.
1541 *media = IFM_ETHER|IFM_10_T;
1549 * Shutdown hardware and free up resources. This can be called any
1550 * time after the mutex has been initialized. It is called in both
1551 * the error case in attach and the normal detach case so it needs
1552 * to be careful about only freeing resources that have actually been
1556 xl_detach(device_t dev)
1558 struct xl_softc *sc;
1562 sc = device_get_softc(dev);
1565 KASSERT(mtx_initialized(&sc->xl_mtx), ("xl mutex not initialized"));
1567 #ifdef DEVICE_POLLING
1568 if (ifp && ifp->if_capenable & IFCAP_POLLING)
1569 ether_poll_deregister(ifp);
1572 if (sc->xl_flags & XL_FLAG_USE_MMIO) {
1574 res = SYS_RES_MEMORY;
1577 res = SYS_RES_IOPORT;
1580 /* These should only be active if attach succeeded */
1581 if (device_is_attached(dev)) {
1585 taskqueue_drain(taskqueue_swi, &sc->xl_task);
1586 callout_drain(&sc->xl_tick_callout);
1587 ether_ifdetach(ifp);
1590 device_delete_child(dev, sc->xl_miibus);
1591 bus_generic_detach(dev);
1592 ifmedia_removeall(&sc->ifmedia);
1594 if (sc->xl_intrhand)
1595 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand);
1597 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq);
1598 if (sc->xl_fres != NULL)
1599 bus_release_resource(dev, SYS_RES_MEMORY,
1600 XL_PCI_FUNCMEM, sc->xl_fres);
1602 bus_release_resource(dev, res, rid, sc->xl_res);
1608 bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap);
1609 bus_dma_tag_destroy(sc->xl_mtag);
1611 if (sc->xl_ldata.xl_rx_tag) {
1612 bus_dmamap_unload(sc->xl_ldata.xl_rx_tag,
1613 sc->xl_ldata.xl_rx_dmamap);
1614 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list,
1615 sc->xl_ldata.xl_rx_dmamap);
1616 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1618 if (sc->xl_ldata.xl_tx_tag) {
1619 bus_dmamap_unload(sc->xl_ldata.xl_tx_tag,
1620 sc->xl_ldata.xl_tx_dmamap);
1621 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list,
1622 sc->xl_ldata.xl_tx_dmamap);
1623 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1626 mtx_destroy(&sc->xl_mtx);
1632 * Initialize the transmit descriptors.
1635 xl_list_tx_init(struct xl_softc *sc)
1637 struct xl_chain_data *cd;
1638 struct xl_list_data *ld;
1645 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1646 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1647 error = bus_dmamap_create(sc->xl_mtag, 0,
1648 &cd->xl_tx_chain[i].xl_map);
1651 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1652 i * sizeof(struct xl_list);
1653 if (i == (XL_TX_LIST_CNT - 1))
1654 cd->xl_tx_chain[i].xl_next = NULL;
1656 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1659 cd->xl_tx_free = &cd->xl_tx_chain[0];
1660 cd->xl_tx_tail = cd->xl_tx_head = NULL;
1662 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE);
1667 * Initialize the transmit descriptors.
1670 xl_list_tx_init_90xB(struct xl_softc *sc)
1672 struct xl_chain_data *cd;
1673 struct xl_list_data *ld;
1680 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1681 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1682 error = bus_dmamap_create(sc->xl_mtag, 0,
1683 &cd->xl_tx_chain[i].xl_map);
1686 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1687 i * sizeof(struct xl_list);
1688 if (i == (XL_TX_LIST_CNT - 1))
1689 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0];
1691 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1693 cd->xl_tx_chain[i].xl_prev =
1694 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1];
1696 cd->xl_tx_chain[i].xl_prev =
1697 &cd->xl_tx_chain[i - 1];
1700 bzero(ld->xl_tx_list, XL_TX_LIST_SZ);
1701 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY);
1707 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE);
1712 * Initialize the RX descriptors and allocate mbufs for them. Note that
1713 * we arrange the descriptors in a closed ring, so that the last descriptor
1714 * points back to the first.
1717 xl_list_rx_init(struct xl_softc *sc)
1719 struct xl_chain_data *cd;
1720 struct xl_list_data *ld;
1729 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1730 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i];
1731 error = bus_dmamap_create(sc->xl_mtag, 0,
1732 &cd->xl_rx_chain[i].xl_map);
1735 error = xl_newbuf(sc, &cd->xl_rx_chain[i]);
1738 if (i == (XL_RX_LIST_CNT - 1))
1742 nextptr = ld->xl_rx_dmaaddr +
1743 next * sizeof(struct xl_list_onefrag);
1744 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next];
1745 ld->xl_rx_list[i].xl_next = htole32(nextptr);
1748 bus_dmamap_sync(ld->xl_rx_tag, ld->xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1749 cd->xl_rx_head = &cd->xl_rx_chain[0];
1755 * Initialize an RX descriptor and attach an MBUF cluster.
1756 * If we fail to do so, we need to leave the old mbuf and
1757 * the old DMA map untouched so that it can be reused.
1760 xl_newbuf(struct xl_softc *sc, struct xl_chain_onefrag *c)
1762 struct mbuf *m_new = NULL;
1764 bus_dma_segment_t segs[1];
1769 m_new = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1773 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1775 /* Force longword alignment for packet payload. */
1776 m_adj(m_new, ETHER_ALIGN);
1778 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, sc->xl_tmpmap, m_new,
1779 segs, &nseg, BUS_DMA_NOWAIT);
1782 device_printf(sc->xl_dev, "can't map mbuf (error %d)\n",
1787 ("%s: too many DMA segments (%d)", __func__, nseg));
1789 bus_dmamap_unload(sc->xl_mtag, c->xl_map);
1791 c->xl_map = sc->xl_tmpmap;
1792 sc->xl_tmpmap = map;
1794 c->xl_ptr->xl_frag.xl_len = htole32(m_new->m_len | XL_LAST_FRAG);
1795 c->xl_ptr->xl_frag.xl_addr = htole32(segs->ds_addr);
1796 c->xl_ptr->xl_status = 0;
1797 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD);
1802 xl_rx_resync(struct xl_softc *sc)
1804 struct xl_chain_onefrag *pos;
1809 pos = sc->xl_cdata.xl_rx_head;
1811 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1812 if (pos->xl_ptr->xl_status)
1817 if (i == XL_RX_LIST_CNT)
1820 sc->xl_cdata.xl_rx_head = pos;
1826 * A frame has been uploaded: pass the resulting mbuf chain up to
1827 * the higher level protocols.
1830 xl_rxeof(struct xl_softc *sc)
1833 struct ifnet *ifp = sc->xl_ifp;
1834 struct xl_chain_onefrag *cur_rx;
1841 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap,
1842 BUS_DMASYNC_POSTREAD);
1843 while ((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) {
1844 #ifdef DEVICE_POLLING
1845 if (ifp->if_capenable & IFCAP_POLLING) {
1846 if (sc->rxcycles <= 0)
1851 cur_rx = sc->xl_cdata.xl_rx_head;
1852 sc->xl_cdata.xl_rx_head = cur_rx->xl_next;
1853 total_len = rxstat & XL_RXSTAT_LENMASK;
1857 * Since we have told the chip to allow large frames,
1858 * we need to trap giant frame errors in software. We allow
1859 * a little more than the normal frame size to account for
1860 * frames with VLAN tags.
1862 if (total_len > XL_MAX_FRAMELEN)
1863 rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE);
1866 * If an error occurs, update stats, clear the
1867 * status word and leave the mbuf cluster in place:
1868 * it should simply get re-used next time this descriptor
1869 * comes up in the ring.
1871 if (rxstat & XL_RXSTAT_UP_ERROR) {
1872 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1873 cur_rx->xl_ptr->xl_status = 0;
1874 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
1875 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1880 * If the error bit was not set, the upload complete
1881 * bit should be set which means we have a valid packet.
1882 * If not, something truly strange has happened.
1884 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) {
1885 device_printf(sc->xl_dev,
1886 "bad receive status -- packet dropped\n");
1887 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1888 cur_rx->xl_ptr->xl_status = 0;
1889 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
1890 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1894 /* No errors; receive the packet. */
1895 bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map,
1896 BUS_DMASYNC_POSTREAD);
1897 m = cur_rx->xl_mbuf;
1900 * Try to conjure up a new mbuf cluster. If that
1901 * fails, it means we have an out of memory condition and
1902 * should leave the buffer in place and continue. This will
1903 * result in a lost packet, but there's little else we
1904 * can do in this situation.
1906 if (xl_newbuf(sc, cur_rx)) {
1907 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1908 cur_rx->xl_ptr->xl_status = 0;
1909 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
1910 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1913 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
1914 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1916 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
1917 m->m_pkthdr.rcvif = ifp;
1918 m->m_pkthdr.len = m->m_len = total_len;
1920 if (ifp->if_capenable & IFCAP_RXCSUM) {
1921 /* Do IP checksum checking. */
1922 if (rxstat & XL_RXSTAT_IPCKOK)
1923 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1924 if (!(rxstat & XL_RXSTAT_IPCKERR))
1925 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1926 if ((rxstat & XL_RXSTAT_TCPCOK &&
1927 !(rxstat & XL_RXSTAT_TCPCKERR)) ||
1928 (rxstat & XL_RXSTAT_UDPCKOK &&
1929 !(rxstat & XL_RXSTAT_UDPCKERR))) {
1930 m->m_pkthdr.csum_flags |=
1931 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1932 m->m_pkthdr.csum_data = 0xffff;
1937 (*ifp->if_input)(ifp, m);
1941 * If we are running from the taskqueue, the interface
1942 * might have been stopped while we were passing the last
1943 * packet up the network stack.
1945 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1950 * Handle the 'end of channel' condition. When the upload
1951 * engine hits the end of the RX ring, it will stall. This
1952 * is our cue to flush the RX ring, reload the uplist pointer
1953 * register and unstall the engine.
1954 * XXX This is actually a little goofy. With the ThunderLAN
1955 * chip, you get an interrupt when the receiver hits the end
1956 * of the receive ring, which tells you exactly when you
1957 * you need to reload the ring pointer. Here we have to
1958 * fake it. I'm mad at myself for not being clever enough
1959 * to avoid the use of a goto here.
1961 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 ||
1962 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) {
1963 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
1965 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr);
1966 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0];
1967 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
1974 * Taskqueue wrapper for xl_rxeof().
1977 xl_rxeof_task(void *arg, int pending)
1979 struct xl_softc *sc = (struct xl_softc *)arg;
1982 if (sc->xl_ifp->if_drv_flags & IFF_DRV_RUNNING)
1988 * A frame was downloaded to the chip. It's safe for us to clean up
1992 xl_txeof(struct xl_softc *sc)
1994 struct xl_chain *cur_tx;
1995 struct ifnet *ifp = sc->xl_ifp;
2000 * Go through our tx list and free mbufs for those
2001 * frames that have been uploaded. Note: the 3c905B
2002 * sets a special bit in the status word to let us
2003 * know that a frame has been downloaded, but the
2004 * original 3c900/3c905 adapters don't do that.
2005 * Consequently, we have to use a different test if
2006 * xl_type != XL_TYPE_905B.
2008 while (sc->xl_cdata.xl_tx_head != NULL) {
2009 cur_tx = sc->xl_cdata.xl_tx_head;
2011 if (CSR_READ_4(sc, XL_DOWNLIST_PTR))
2014 sc->xl_cdata.xl_tx_head = cur_tx->xl_next;
2015 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2016 BUS_DMASYNC_POSTWRITE);
2017 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2018 m_freem(cur_tx->xl_mbuf);
2019 cur_tx->xl_mbuf = NULL;
2020 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
2021 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2023 cur_tx->xl_next = sc->xl_cdata.xl_tx_free;
2024 sc->xl_cdata.xl_tx_free = cur_tx;
2027 if (sc->xl_cdata.xl_tx_head == NULL) {
2028 sc->xl_wdog_timer = 0;
2029 sc->xl_cdata.xl_tx_tail = NULL;
2031 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED ||
2032 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) {
2033 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2034 sc->xl_cdata.xl_tx_head->xl_phys);
2035 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2041 xl_txeof_90xB(struct xl_softc *sc)
2043 struct xl_chain *cur_tx = NULL;
2044 struct ifnet *ifp = sc->xl_ifp;
2049 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2050 BUS_DMASYNC_POSTREAD);
2051 idx = sc->xl_cdata.xl_tx_cons;
2052 while (idx != sc->xl_cdata.xl_tx_prod) {
2053 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2055 if (!(le32toh(cur_tx->xl_ptr->xl_status) &
2056 XL_TXSTAT_DL_COMPLETE))
2059 if (cur_tx->xl_mbuf != NULL) {
2060 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2061 BUS_DMASYNC_POSTWRITE);
2062 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2063 m_freem(cur_tx->xl_mbuf);
2064 cur_tx->xl_mbuf = NULL;
2067 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
2069 sc->xl_cdata.xl_tx_cnt--;
2070 XL_INC(idx, XL_TX_LIST_CNT);
2073 if (sc->xl_cdata.xl_tx_cnt == 0)
2074 sc->xl_wdog_timer = 0;
2075 sc->xl_cdata.xl_tx_cons = idx;
2078 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2082 * TX 'end of channel' interrupt handler. Actually, we should
2083 * only get a 'TX complete' interrupt if there's a transmit error,
2084 * so this is really TX error handler.
2087 xl_txeoc(struct xl_softc *sc)
2093 while ((txstat = CSR_READ_1(sc, XL_TX_STATUS))) {
2094 if (txstat & XL_TXSTATUS_UNDERRUN ||
2095 txstat & XL_TXSTATUS_JABBER ||
2096 txstat & XL_TXSTATUS_RECLAIM) {
2097 device_printf(sc->xl_dev,
2098 "transmission error: 0x%02x\n", txstat);
2099 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2101 if (sc->xl_type == XL_TYPE_905B) {
2102 if (sc->xl_cdata.xl_tx_cnt) {
2106 i = sc->xl_cdata.xl_tx_cons;
2107 c = &sc->xl_cdata.xl_tx_chain[i];
2108 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2110 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2111 sc->xl_wdog_timer = 5;
2114 if (sc->xl_cdata.xl_tx_head != NULL) {
2115 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2116 sc->xl_cdata.xl_tx_head->xl_phys);
2117 sc->xl_wdog_timer = 5;
2121 * Remember to set this for the
2122 * first generation 3c90X chips.
2124 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2125 if (txstat & XL_TXSTATUS_UNDERRUN &&
2126 sc->xl_tx_thresh < XL_PACKET_SIZE) {
2127 sc->xl_tx_thresh += XL_MIN_FRAMELEN;
2128 device_printf(sc->xl_dev,
2129 "tx underrun, increasing tx start threshold to %d bytes\n", sc->xl_tx_thresh);
2131 CSR_WRITE_2(sc, XL_COMMAND,
2132 XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2133 if (sc->xl_type == XL_TYPE_905B) {
2134 CSR_WRITE_2(sc, XL_COMMAND,
2135 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2137 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2138 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2140 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2141 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2144 * Write an arbitrary byte to the TX_STATUS register
2145 * to clear this interrupt/error and advance to the next.
2147 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01);
2154 struct xl_softc *sc = arg;
2155 struct ifnet *ifp = sc->xl_ifp;
2160 #ifdef DEVICE_POLLING
2161 if (ifp->if_capenable & IFCAP_POLLING) {
2168 status = CSR_READ_2(sc, XL_STATUS);
2169 if ((status & XL_INTRS) == 0 || status == 0xFFFF)
2171 CSR_WRITE_2(sc, XL_COMMAND,
2172 XL_CMD_INTR_ACK|(status & XL_INTRS));
2173 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
2176 if (status & XL_STAT_UP_COMPLETE) {
2177 if (xl_rxeof(sc) == 0) {
2178 while (xl_rx_resync(sc))
2183 if (status & XL_STAT_DOWN_COMPLETE) {
2184 if (sc->xl_type == XL_TYPE_905B)
2190 if (status & XL_STAT_TX_COMPLETE) {
2191 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
2195 if (status & XL_STAT_ADFAIL) {
2196 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2201 if (status & XL_STAT_STATSOFLOW)
2202 xl_stats_update(sc);
2205 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2206 ifp->if_drv_flags & IFF_DRV_RUNNING) {
2207 if (sc->xl_type == XL_TYPE_905B)
2208 xl_start_90xB_locked(ifp);
2210 xl_start_locked(ifp);
2216 #ifdef DEVICE_POLLING
2218 xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2220 struct xl_softc *sc = ifp->if_softc;
2224 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2225 rx_npkts = xl_poll_locked(ifp, cmd, count);
2231 xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
2233 struct xl_softc *sc = ifp->if_softc;
2238 sc->rxcycles = count;
2239 rx_npkts = xl_rxeof(sc);
2240 if (sc->xl_type == XL_TYPE_905B)
2245 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
2246 if (sc->xl_type == XL_TYPE_905B)
2247 xl_start_90xB_locked(ifp);
2249 xl_start_locked(ifp);
2252 if (cmd == POLL_AND_CHECK_STATUS) {
2255 status = CSR_READ_2(sc, XL_STATUS);
2256 if (status & XL_INTRS && status != 0xFFFF) {
2257 CSR_WRITE_2(sc, XL_COMMAND,
2258 XL_CMD_INTR_ACK|(status & XL_INTRS));
2260 if (status & XL_STAT_TX_COMPLETE) {
2261 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
2265 if (status & XL_STAT_ADFAIL) {
2266 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2270 if (status & XL_STAT_STATSOFLOW)
2271 xl_stats_update(sc);
2276 #endif /* DEVICE_POLLING */
2281 struct xl_softc *sc = xsc;
2282 struct mii_data *mii;
2286 if (sc->xl_miibus != NULL) {
2287 mii = device_get_softc(sc->xl_miibus);
2291 xl_stats_update(sc);
2292 if (xl_watchdog(sc) == EJUSTRETURN)
2295 callout_reset(&sc->xl_tick_callout, hz, xl_tick, sc);
2299 xl_stats_update(struct xl_softc *sc)
2301 struct ifnet *ifp = sc->xl_ifp;
2302 struct xl_stats xl_stats;
2308 bzero((char *)&xl_stats, sizeof(struct xl_stats));
2310 p = (u_int8_t *)&xl_stats;
2312 /* Read all the stats registers. */
2315 for (i = 0; i < 16; i++)
2316 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i);
2318 if_inc_counter(ifp, IFCOUNTER_IERRORS, xl_stats.xl_rx_overrun);
2320 if_inc_counter(ifp, IFCOUNTER_COLLISIONS,
2321 xl_stats.xl_tx_multi_collision +
2322 xl_stats.xl_tx_single_collision +
2323 xl_stats.xl_tx_late_collision);
2326 * Boomerang and cyclone chips have an extra stats counter
2327 * in window 4 (BadSSD). We have to read this too in order
2328 * to clear out all the stats registers and avoid a statsoflow
2332 CSR_READ_1(sc, XL_W4_BADSSD);
2337 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
2338 * pointers to the fragment pointers.
2341 xl_encap(struct xl_softc *sc, struct xl_chain *c, struct mbuf **m_head)
2344 struct ifnet *ifp = sc->xl_ifp;
2345 int error, i, nseg, total_len;
2350 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map, *m_head,
2351 sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT);
2353 if (error && error != EFBIG) {
2354 if_printf(ifp, "can't map mbuf (error %d)\n", error);
2359 * Handle special case: we used up all 63 fragments,
2360 * but we have more mbufs left in the chain. Copy the
2361 * data into an mbuf cluster. Note that we don't
2362 * bother clearing the values in the other fragment
2363 * pointers/counters; it wouldn't gain us anything,
2364 * and would waste cycles.
2367 m_new = m_collapse(*m_head, M_NOWAIT, XL_MAXFRAGS);
2368 if (m_new == NULL) {
2375 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map,
2376 *m_head, sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT);
2380 if_printf(ifp, "can't map mbuf (error %d)\n", error);
2385 KASSERT(nseg <= XL_MAXFRAGS,
2386 ("%s: too many DMA segments (%d)", __func__, nseg));
2392 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE);
2395 for (i = 0; i < nseg; i++) {
2396 KASSERT(sc->xl_cdata.xl_tx_segs[i].ds_len <= MCLBYTES,
2397 ("segment size too large"));
2398 c->xl_ptr->xl_frag[i].xl_addr =
2399 htole32(sc->xl_cdata.xl_tx_segs[i].ds_addr);
2400 c->xl_ptr->xl_frag[i].xl_len =
2401 htole32(sc->xl_cdata.xl_tx_segs[i].ds_len);
2402 total_len += sc->xl_cdata.xl_tx_segs[i].ds_len;
2404 c->xl_ptr->xl_frag[nseg - 1].xl_len |= htole32(XL_LAST_FRAG);
2406 if (sc->xl_type == XL_TYPE_905B) {
2407 status = XL_TXSTAT_RND_DEFEAT;
2409 #ifndef XL905B_TXCSUM_BROKEN
2410 if ((*m_head)->m_pkthdr.csum_flags) {
2411 if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP)
2412 status |= XL_TXSTAT_IPCKSUM;
2413 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP)
2414 status |= XL_TXSTAT_TCPCKSUM;
2415 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP)
2416 status |= XL_TXSTAT_UDPCKSUM;
2421 c->xl_ptr->xl_status = htole32(status);
2422 c->xl_ptr->xl_next = 0;
2424 c->xl_mbuf = *m_head;
2429 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2430 * to the mbuf data regions directly in the transmit lists. We also save a
2431 * copy of the pointers since the transmit list fragment pointers are
2432 * physical addresses.
2436 xl_start(struct ifnet *ifp)
2438 struct xl_softc *sc = ifp->if_softc;
2442 if (sc->xl_type == XL_TYPE_905B)
2443 xl_start_90xB_locked(ifp);
2445 xl_start_locked(ifp);
2451 xl_start_locked(struct ifnet *ifp)
2453 struct xl_softc *sc = ifp->if_softc;
2454 struct mbuf *m_head;
2455 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2456 struct xl_chain *prev_tx;
2461 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
2465 * Check for an available queue slot. If there are none,
2468 if (sc->xl_cdata.xl_tx_free == NULL) {
2471 if (sc->xl_cdata.xl_tx_free == NULL) {
2472 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2477 start_tx = sc->xl_cdata.xl_tx_free;
2479 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2480 sc->xl_cdata.xl_tx_free != NULL;) {
2481 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2485 /* Pick a descriptor off the free list. */
2487 cur_tx = sc->xl_cdata.xl_tx_free;
2489 /* Pack the data into the descriptor. */
2490 error = xl_encap(sc, cur_tx, &m_head);
2495 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2496 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2500 sc->xl_cdata.xl_tx_free = cur_tx->xl_next;
2501 cur_tx->xl_next = NULL;
2503 /* Chain it together. */
2505 prev->xl_next = cur_tx;
2506 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2511 * If there's a BPF listener, bounce a copy of this frame
2514 BPF_MTAP(ifp, cur_tx->xl_mbuf);
2518 * If there are no packets queued, bail.
2524 * Place the request for the upload interrupt
2525 * in the last descriptor in the chain. This way, if
2526 * we're chaining several packets at once, we'll only
2527 * get an interrupt once for the whole chain rather than
2528 * once for each packet.
2530 cur_tx->xl_ptr->xl_status |= htole32(XL_TXSTAT_DL_INTR);
2533 * Queue the packets. If the TX channel is clear, update
2534 * the downlist pointer register.
2536 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2539 if (sc->xl_cdata.xl_tx_head != NULL) {
2540 sc->xl_cdata.xl_tx_tail->xl_next = start_tx;
2541 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next =
2542 htole32(start_tx->xl_phys);
2543 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status &=
2544 htole32(~XL_TXSTAT_DL_INTR);
2545 sc->xl_cdata.xl_tx_tail = cur_tx;
2547 sc->xl_cdata.xl_tx_head = start_tx;
2548 sc->xl_cdata.xl_tx_tail = cur_tx;
2550 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2551 BUS_DMASYNC_PREWRITE);
2552 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR))
2553 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys);
2555 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2560 * Set a timeout in case the chip goes out to lunch.
2562 sc->xl_wdog_timer = 5;
2565 * XXX Under certain conditions, usually on slower machines
2566 * where interrupts may be dropped, it's possible for the
2567 * adapter to chew up all the buffers in the receive ring
2568 * and stall, without us being able to do anything about it.
2569 * To guard against this, we need to make a pass over the
2570 * RX queue to make sure there aren't any packets pending.
2571 * Doing it here means we can flush the receive ring at the
2572 * same time the chip is DMAing the transmit descriptors we
2575 * 3Com goes to some lengths to emphasize the Parallel Tasking (tm)
2576 * nature of their chips in all their marketing literature;
2577 * we may as well take advantage of it. :)
2579 taskqueue_enqueue(taskqueue_swi, &sc->xl_task);
2583 xl_start_90xB_locked(struct ifnet *ifp)
2585 struct xl_softc *sc = ifp->if_softc;
2586 struct mbuf *m_head;
2587 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2588 struct xl_chain *prev_tx;
2593 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
2597 idx = sc->xl_cdata.xl_tx_prod;
2598 start_tx = &sc->xl_cdata.xl_tx_chain[idx];
2600 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2601 sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL;) {
2602 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) {
2603 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2607 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2612 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2614 /* Pack the data into the descriptor. */
2615 error = xl_encap(sc, cur_tx, &m_head);
2620 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2621 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2625 /* Chain it together. */
2627 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2631 * If there's a BPF listener, bounce a copy of this frame
2634 BPF_MTAP(ifp, cur_tx->xl_mbuf);
2636 XL_INC(idx, XL_TX_LIST_CNT);
2637 sc->xl_cdata.xl_tx_cnt++;
2641 * If there are no packets queued, bail.
2647 * Place the request for the upload interrupt
2648 * in the last descriptor in the chain. This way, if
2649 * we're chaining several packets at once, we'll only
2650 * get an interrupt once for the whole chain rather than
2651 * once for each packet.
2653 cur_tx->xl_ptr->xl_status |= htole32(XL_TXSTAT_DL_INTR);
2655 /* Start transmission */
2656 sc->xl_cdata.xl_tx_prod = idx;
2657 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys);
2658 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2659 BUS_DMASYNC_PREWRITE);
2662 * Set a timeout in case the chip goes out to lunch.
2664 sc->xl_wdog_timer = 5;
2670 struct xl_softc *sc = xsc;
2678 xl_init_locked(struct xl_softc *sc)
2680 struct ifnet *ifp = sc->xl_ifp;
2682 struct mii_data *mii = NULL;
2686 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2689 * Cancel pending I/O and free all RX/TX buffers.
2693 /* Reset the chip to a known state. */
2696 if (sc->xl_miibus == NULL) {
2697 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2700 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2704 if (sc->xl_miibus != NULL)
2705 mii = device_get_softc(sc->xl_miibus);
2708 * Clear WOL status and disable all WOL feature as WOL
2709 * would interfere Rx operation under normal environments.
2711 if ((sc->xl_flags & XL_FLAG_WOL) != 0) {
2713 CSR_READ_2(sc, XL_W7_BM_PME);
2714 CSR_WRITE_2(sc, XL_W7_BM_PME, 0);
2716 /* Init our MAC address */
2718 for (i = 0; i < ETHER_ADDR_LEN; i++) {
2719 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i,
2720 IF_LLADDR(sc->xl_ifp)[i]);
2723 /* Clear the station mask. */
2724 for (i = 0; i < 3; i++)
2725 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0);
2727 /* Reset TX and RX. */
2728 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2730 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2733 /* Init circular RX list. */
2734 error = xl_list_rx_init(sc);
2736 device_printf(sc->xl_dev, "initialization of the rx ring failed (%d)\n",
2742 /* Init TX descriptors. */
2743 if (sc->xl_type == XL_TYPE_905B)
2744 error = xl_list_tx_init_90xB(sc);
2746 error = xl_list_tx_init(sc);
2748 device_printf(sc->xl_dev, "initialization of the tx ring failed (%d)\n",
2755 * Set the TX freethresh value.
2756 * Note that this has no effect on 3c905B "cyclone"
2757 * cards but is required for 3c900/3c905 "boomerang"
2758 * cards in order to enable the download engine.
2760 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2762 /* Set the TX start threshold for best performance. */
2763 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2766 * If this is a 3c905B, also set the tx reclaim threshold.
2767 * This helps cut down on the number of tx reclaim errors
2768 * that could happen on a busy network. The chip multiplies
2769 * the register value by 16 to obtain the actual threshold
2770 * in bytes, so we divide by 16 when setting the value here.
2771 * The existing threshold value can be examined by reading
2772 * the register at offset 9 in window 5.
2774 if (sc->xl_type == XL_TYPE_905B) {
2775 CSR_WRITE_2(sc, XL_COMMAND,
2776 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2779 /* Set RX filter bits. */
2783 * Load the address of the RX list. We have to
2784 * stall the upload engine before we can manipulate
2785 * the uplist pointer register, then unstall it when
2786 * we're finished. We also have to wait for the
2787 * stall command to complete before proceeding.
2788 * Note that we have to do this after any RX resets
2789 * have completed since the uplist register is cleared
2792 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
2794 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr);
2795 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
2798 if (sc->xl_type == XL_TYPE_905B) {
2799 /* Set polling interval */
2800 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2801 /* Load the address of the TX list */
2802 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2804 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2805 sc->xl_cdata.xl_tx_chain[0].xl_phys);
2806 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2811 * If the coax transceiver is on, make sure to enable
2812 * the DC-DC converter.
2815 if (sc->xl_xcvr == XL_XCVR_COAX)
2816 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
2818 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
2821 * increase packet size to allow reception of 802.1q or ISL packets.
2822 * For the 3c90x chip, set the 'allow large packets' bit in the MAC
2823 * control register. For 3c90xB/C chips, use the RX packet size
2827 if (sc->xl_type == XL_TYPE_905B)
2828 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE);
2831 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL);
2832 macctl |= XL_MACCTRL_ALLOW_LARGE_PACK;
2833 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl);
2836 /* Clear out the stats counters. */
2837 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
2838 xl_stats_update(sc);
2840 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE);
2841 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE);
2844 * Enable interrupts.
2846 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF);
2847 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS);
2848 #ifdef DEVICE_POLLING
2849 /* Disable interrupts if we are polling. */
2850 if (ifp->if_capenable & IFCAP_POLLING)
2851 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
2854 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS);
2855 if (sc->xl_flags & XL_FLAG_FUNCREG)
2856 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
2858 /* Set the RX early threshold */
2859 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2));
2860 CSR_WRITE_4(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY);
2862 /* Enable receiver and transmitter. */
2863 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2865 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE);
2868 /* XXX Downcall to miibus. */
2872 /* Select window 7 for normal operations. */
2875 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2876 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2878 sc->xl_wdog_timer = 0;
2879 callout_reset(&sc->xl_tick_callout, hz, xl_tick, sc);
2883 * Set media options.
2886 xl_ifmedia_upd(struct ifnet *ifp)
2888 struct xl_softc *sc = ifp->if_softc;
2889 struct ifmedia *ifm = NULL;
2890 struct mii_data *mii = NULL;
2894 if (sc->xl_miibus != NULL)
2895 mii = device_get_softc(sc->xl_miibus);
2899 ifm = &mii->mii_media;
2901 switch (IFM_SUBTYPE(ifm->ifm_media)) {
2906 xl_setmode(sc, ifm->ifm_media);
2911 if (sc->xl_media & XL_MEDIAOPT_MII ||
2912 sc->xl_media & XL_MEDIAOPT_BTX ||
2913 sc->xl_media & XL_MEDIAOPT_BT4) {
2914 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2917 xl_setmode(sc, ifm->ifm_media);
2926 * Report current media status.
2929 xl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2931 struct xl_softc *sc = ifp->if_softc;
2933 u_int16_t status = 0;
2934 struct mii_data *mii = NULL;
2938 if (sc->xl_miibus != NULL)
2939 mii = device_get_softc(sc->xl_miibus);
2942 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
2945 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK;
2946 icfg >>= XL_ICFG_CONNECTOR_BITS;
2948 ifmr->ifm_active = IFM_ETHER;
2949 ifmr->ifm_status = IFM_AVALID;
2951 if ((status & XL_MEDIASTAT_CARRIER) == 0)
2952 ifmr->ifm_status |= IFM_ACTIVE;
2956 ifmr->ifm_active = IFM_ETHER|IFM_10_T;
2957 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
2958 ifmr->ifm_active |= IFM_FDX;
2960 ifmr->ifm_active |= IFM_HDX;
2963 if (sc->xl_type == XL_TYPE_905B &&
2964 sc->xl_media == XL_MEDIAOPT_10FL) {
2965 ifmr->ifm_active = IFM_ETHER|IFM_10_FL;
2966 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
2967 ifmr->ifm_active |= IFM_FDX;
2969 ifmr->ifm_active |= IFM_HDX;
2971 ifmr->ifm_active = IFM_ETHER|IFM_10_5;
2974 ifmr->ifm_active = IFM_ETHER|IFM_10_2;
2977 * XXX MII and BTX/AUTO should be separate cases.
2980 case XL_XCVR_100BTX:
2985 ifmr->ifm_active = mii->mii_media_active;
2986 ifmr->ifm_status = mii->mii_media_status;
2989 case XL_XCVR_100BFX:
2990 ifmr->ifm_active = IFM_ETHER|IFM_100_FX;
2993 if_printf(ifp, "unknown XCVR type: %d\n", icfg);
3001 xl_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3003 struct xl_softc *sc = ifp->if_softc;
3004 struct ifreq *ifr = (struct ifreq *) data;
3005 int error = 0, mask;
3006 struct mii_data *mii = NULL;
3011 if (ifp->if_flags & IFF_UP) {
3012 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3013 (ifp->if_flags ^ sc->xl_if_flags) &
3014 (IFF_PROMISC | IFF_ALLMULTI))
3019 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3022 sc->xl_if_flags = ifp->if_flags;
3027 /* XXX Downcall from if_addmulti() possibly with locks held. */
3029 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3035 if (sc->xl_miibus != NULL)
3036 mii = device_get_softc(sc->xl_miibus);
3038 error = ifmedia_ioctl(ifp, ifr,
3039 &sc->ifmedia, command);
3041 error = ifmedia_ioctl(ifp, ifr,
3042 &mii->mii_media, command);
3045 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3046 #ifdef DEVICE_POLLING
3047 if ((mask & IFCAP_POLLING) != 0 &&
3048 (ifp->if_capabilities & IFCAP_POLLING) != 0) {
3049 ifp->if_capenable ^= IFCAP_POLLING;
3050 if ((ifp->if_capenable & IFCAP_POLLING) != 0) {
3051 error = ether_poll_register(xl_poll, ifp);
3055 /* Disable interrupts */
3056 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
3057 ifp->if_capenable |= IFCAP_POLLING;
3060 error = ether_poll_deregister(ifp);
3061 /* Enable interrupts. */
3063 CSR_WRITE_2(sc, XL_COMMAND,
3064 XL_CMD_INTR_ACK | 0xFF);
3065 CSR_WRITE_2(sc, XL_COMMAND,
3066 XL_CMD_INTR_ENB | XL_INTRS);
3067 if (sc->xl_flags & XL_FLAG_FUNCREG)
3068 bus_space_write_4(sc->xl_ftag,
3069 sc->xl_fhandle, 4, 0x8000);
3073 #endif /* DEVICE_POLLING */
3075 if ((mask & IFCAP_TXCSUM) != 0 &&
3076 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
3077 ifp->if_capenable ^= IFCAP_TXCSUM;
3078 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
3079 ifp->if_hwassist |= XL905B_CSUM_FEATURES;
3081 ifp->if_hwassist &= ~XL905B_CSUM_FEATURES;
3083 if ((mask & IFCAP_RXCSUM) != 0 &&
3084 (ifp->if_capabilities & IFCAP_RXCSUM) != 0)
3085 ifp->if_capenable ^= IFCAP_RXCSUM;
3086 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
3087 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0)
3088 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
3092 error = ether_ioctl(ifp, command, data);
3100 xl_watchdog(struct xl_softc *sc)
3102 struct ifnet *ifp = sc->xl_ifp;
3103 u_int16_t status = 0;
3108 if (sc->xl_wdog_timer == 0 || --sc->xl_wdog_timer != 0)
3114 if (sc->xl_type == XL_TYPE_905B) {
3116 if (sc->xl_cdata.xl_tx_cnt == 0)
3120 if (sc->xl_cdata.xl_tx_head == NULL)
3124 device_printf(sc->xl_dev,
3125 "watchdog timeout (missed Tx interrupts) -- recovering\n");
3129 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
3131 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
3132 device_printf(sc->xl_dev, "watchdog timeout\n");
3134 if (status & XL_MEDIASTAT_CARRIER)
3135 device_printf(sc->xl_dev,
3136 "no carrier - transceiver cable problem?\n");
3138 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3141 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
3142 if (sc->xl_type == XL_TYPE_905B)
3143 xl_start_90xB_locked(ifp);
3145 xl_start_locked(ifp);
3148 return (EJUSTRETURN);
3152 * Stop the adapter and free any mbufs allocated to the
3156 xl_stop(struct xl_softc *sc)
3159 struct ifnet *ifp = sc->xl_ifp;
3163 sc->xl_wdog_timer = 0;
3165 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE);
3166 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
3167 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB);
3168 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD);
3170 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE);
3171 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
3175 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
3177 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
3181 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH);
3182 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0);
3183 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
3184 if (sc->xl_flags & XL_FLAG_FUNCREG)
3185 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
3187 /* Stop the stats updater. */
3188 callout_stop(&sc->xl_tick_callout);
3191 * Free data in the RX lists.
3193 for (i = 0; i < XL_RX_LIST_CNT; i++) {
3194 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) {
3195 bus_dmamap_unload(sc->xl_mtag,
3196 sc->xl_cdata.xl_rx_chain[i].xl_map);
3197 bus_dmamap_destroy(sc->xl_mtag,
3198 sc->xl_cdata.xl_rx_chain[i].xl_map);
3199 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf);
3200 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL;
3203 if (sc->xl_ldata.xl_rx_list != NULL)
3204 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ);
3206 * Free the TX list buffers.
3208 for (i = 0; i < XL_TX_LIST_CNT; i++) {
3209 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) {
3210 bus_dmamap_unload(sc->xl_mtag,
3211 sc->xl_cdata.xl_tx_chain[i].xl_map);
3212 bus_dmamap_destroy(sc->xl_mtag,
3213 sc->xl_cdata.xl_tx_chain[i].xl_map);
3214 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf);
3215 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL;
3218 if (sc->xl_ldata.xl_tx_list != NULL)
3219 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ);
3221 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
3225 * Stop all chip I/O so that the kernel's probe routines don't
3226 * get confused by errant DMAs when rebooting.
3229 xl_shutdown(device_t dev)
3232 return (xl_suspend(dev));
3236 xl_suspend(device_t dev)
3238 struct xl_softc *sc;
3240 sc = device_get_softc(dev);
3251 xl_resume(device_t dev)
3253 struct xl_softc *sc;
3256 sc = device_get_softc(dev);
3261 if (ifp->if_flags & IFF_UP) {
3262 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3272 xl_setwol(struct xl_softc *sc)
3275 u_int16_t cfg, pmstat;
3277 if ((sc->xl_flags & XL_FLAG_WOL) == 0)
3282 /* Clear any pending PME events. */
3283 CSR_READ_2(sc, XL_W7_BM_PME);
3285 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
3286 cfg |= XL_BM_PME_MAGIC;
3287 CSR_WRITE_2(sc, XL_W7_BM_PME, cfg);
3289 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
3290 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE);
3292 pmstat = pci_read_config(sc->xl_dev,
3293 sc->xl_pmcap + PCIR_POWER_STATUS, 2);
3294 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
3295 pmstat |= PCIM_PSTAT_PMEENABLE;
3297 pmstat &= ~PCIM_PSTAT_PMEENABLE;
3298 pci_write_config(sc->xl_dev,
3299 sc->xl_pmcap + PCIR_POWER_STATUS, pmstat, 2);