2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1997, 1998
5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
37 #define XL_EE_READ 0x0080 /* read, 5 bit address */
38 #define XL_EE_WRITE 0x0040 /* write, 5 bit address */
39 #define XL_EE_ERASE 0x00c0 /* erase, 5 bit address */
40 #define XL_EE_EWEN 0x0030 /* erase, no data needed */
41 #define XL_EE_8BIT_READ 0x0200 /* read, 8 bit address */
42 #define XL_EE_BUSY 0x8000
44 #define XL_EE_EADDR0 0x00 /* station address, first word */
45 #define XL_EE_EADDR1 0x01 /* station address, next word, */
46 #define XL_EE_EADDR2 0x02 /* station address, last word */
47 #define XL_EE_PRODID 0x03 /* product ID code */
48 #define XL_EE_MDATA_DATE 0x04 /* manufacturing data, date */
49 #define XL_EE_MDATA_DIV 0x05 /* manufacturing data, division */
50 #define XL_EE_MDATA_PCODE 0x06 /* manufacturing data, product code */
51 #define XL_EE_MFG_ID 0x07
52 #define XL_EE_PCI_PARM 0x08
53 #define XL_EE_ROM_ONFO 0x09
54 #define XL_EE_OEM_ADR0 0x0A
55 #define XL_EE_OEM_ADR1 0x0B
56 #define XL_EE_OEM_ADR2 0x0C
57 #define XL_EE_SOFTINFO1 0x0D
58 #define XL_EE_COMPAT 0x0E
59 #define XL_EE_SOFTINFO2 0x0F
60 #define XL_EE_CAPS 0x10 /* capabilities word */
61 #define XL_EE_RSVD0 0x11
62 #define XL_EE_ICFG_0 0x12
63 #define XL_EE_ICFG_1 0x13
64 #define XL_EE_RSVD1 0x14
65 #define XL_EE_SOFTINFO3 0x15
66 #define XL_EE_RSVD_2 0x16
69 * Bits in the capabilities word
71 #define XL_CAPS_PNP 0x0001
72 #define XL_CAPS_FULL_DUPLEX 0x0002
73 #define XL_CAPS_LARGE_PKTS 0x0004
74 #define XL_CAPS_SLAVE_DMA 0x0008
75 #define XL_CAPS_SECOND_DMA 0x0010
76 #define XL_CAPS_FULL_BM 0x0020
77 #define XL_CAPS_FRAG_BM 0x0040
78 #define XL_CAPS_CRC_PASSTHRU 0x0080
79 #define XL_CAPS_TXDONE 0x0100
80 #define XL_CAPS_NO_TXLENGTH 0x0200
81 #define XL_CAPS_RX_REPEAT 0x0400
82 #define XL_CAPS_SNOOPING 0x0800
83 #define XL_CAPS_100MBPS 0x1000
84 #define XL_CAPS_PWRMGMT 0x2000
87 * Bits in the software information 2 word
89 #define XL_SINFO2_FIXED_BCAST_RX_BUG 0x0002
90 #define XL_SINFO2_FIXED_ENDEC_LOOP_BUG 0x0004
91 #define XL_SINFO2_AUX_WOL_CON 0x0008
92 #define XL_SINFO2_PME_PULSED 0x0010
93 #define XL_SINFO2_FIXED_MWI_BUG 0x0020
94 #define XL_SINFO2_WOL_AFTER_PWR_LOSS 0x0040
95 #define XL_SINFO2_AUTO_RST_TO_D0 0x0080
97 #define XL_PACKET_SIZE 1540
98 #define XL_MAX_FRAMELEN (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN)
103 #define XL_COMMAND 0x0E
104 #define XL_STATUS 0x0E
106 #define XL_TX_STATUS 0x1B
107 #define XL_TX_FREE 0x1C
108 #define XL_DMACTL 0x20
109 #define XL_DOWNLIST_PTR 0x24
110 #define XL_DOWN_POLL 0x2D /* 3c90xB only */
111 #define XL_TX_FREETHRESH 0x2F
112 #define XL_UPLIST_PTR 0x38
113 #define XL_UPLIST_STATUS 0x30
114 #define XL_UP_POLL 0x3D /* 3c90xB only */
116 #define XL_PKTSTAT_UP_STALLED 0x00002000
117 #define XL_PKTSTAT_UP_ERROR 0x00004000
118 #define XL_PKTSTAT_UP_CMPLT 0x00008000
120 #define XL_DMACTL_DN_CMPLT_REQ 0x00000002
121 #define XL_DMACTL_DOWN_STALLED 0x00000004
122 #define XL_DMACTL_UP_CMPLT 0x00000008
123 #define XL_DMACTL_DOWN_CMPLT 0x00000010
124 #define XL_DMACTL_UP_RX_EARLY 0x00000020
125 #define XL_DMACTL_ARM_COUNTDOWN 0x00000040
126 #define XL_DMACTL_DOWN_INPROG 0x00000080
127 #define XL_DMACTL_COUNTER_SPEED 0x00000100
128 #define XL_DMACTL_DOWNDOWN_MODE 0x00000200
129 #define XL_DMACTL_UP_ALTSEQ_DIS 0x00010000 /* 3c90xB/3c90xC */
130 #define XL_DMACTL_DOWN_ALTSEQ_DIS 0x00020000 /* 3c90xC only */
131 #define XL_DMACTL_DEFEAT_MWI 0x00100000 /* 3c90xB/3c90xC */
132 #define XL_DMACTL_DEFEAT_MRL 0x00100000 /* 3c90xB/3c90xC */
133 #define XL_DMACTL_UP_OVERRUN_DISC_DIS 0x00200000 /* 3c90xB/3c90xC */
134 #define XL_DMACTL_TARGET_ABORT 0x40000000
135 #define XL_DMACTL_MASTER_ABORT 0x80000000
138 * Command codes. Some command codes require that we wait for
139 * the CMD_BUSY flag to clear. Those codes are marked as 'mustwait.'
141 #define XL_CMD_RESET 0x0000 /* mustwait */
142 #define XL_CMD_WINSEL 0x0800
143 #define XL_CMD_COAX_START 0x1000
144 #define XL_CMD_RX_DISABLE 0x1800
145 #define XL_CMD_RX_ENABLE 0x2000
146 #define XL_CMD_RX_RESET 0x2800 /* mustwait */
147 #define XL_CMD_UP_STALL 0x3000 /* mustwait */
148 #define XL_CMD_UP_UNSTALL 0x3001
149 #define XL_CMD_DOWN_STALL 0x3002 /* mustwait */
150 #define XL_CMD_DOWN_UNSTALL 0x3003
151 #define XL_CMD_RX_DISCARD 0x4000
152 #define XL_CMD_TX_ENABLE 0x4800
153 #define XL_CMD_TX_DISABLE 0x5000
154 #define XL_CMD_TX_RESET 0x5800 /* mustwait */
155 #define XL_CMD_INTR_FAKE 0x6000
156 #define XL_CMD_INTR_ACK 0x6800
157 #define XL_CMD_INTR_ENB 0x7000
158 #define XL_CMD_STAT_ENB 0x7800
159 #define XL_CMD_RX_SET_FILT 0x8000
160 #define XL_CMD_RX_SET_THRESH 0x8800
161 #define XL_CMD_TX_SET_THRESH 0x9000
162 #define XL_CMD_TX_SET_START 0x9800
163 #define XL_CMD_DMA_UP 0xA000
164 #define XL_CMD_DMA_STOP 0xA001
165 #define XL_CMD_STATS_ENABLE 0xA800
166 #define XL_CMD_STATS_DISABLE 0xB000
167 #define XL_CMD_COAX_STOP 0xB800
169 #define XL_CMD_SET_TX_RECLAIM 0xC000 /* 3c905B only */
170 #define XL_CMD_RX_SET_HASH 0xC800 /* 3c905B only */
172 #define XL_HASH_SET 0x0400
173 #define XL_HASHFILT_SIZE 256
177 * Note that bits 15 to 13 indicate the currently visible register window
178 * which may be anything from 0 to 7.
180 #define XL_STAT_INTLATCH 0x0001 /* 0 */
181 #define XL_STAT_ADFAIL 0x0002 /* 1 */
182 #define XL_STAT_TX_COMPLETE 0x0004 /* 2 */
183 #define XL_STAT_TX_AVAIL 0x0008 /* 3 first generation */
184 #define XL_STAT_RX_COMPLETE 0x0010 /* 4 */
185 #define XL_STAT_RX_EARLY 0x0020 /* 5 */
186 #define XL_STAT_INTREQ 0x0040 /* 6 */
187 #define XL_STAT_STATSOFLOW 0x0080 /* 7 */
188 #define XL_STAT_DMADONE 0x0100 /* 8 first generation */
189 #define XL_STAT_LINKSTAT 0x0100 /* 8 3c509B */
190 #define XL_STAT_DOWN_COMPLETE 0x0200 /* 9 */
191 #define XL_STAT_UP_COMPLETE 0x0400 /* 10 */
192 #define XL_STAT_DMABUSY 0x0800 /* 11 first generation */
193 #define XL_STAT_CMDBUSY 0x1000 /* 12 */
196 * Interrupts we normally want enabled.
199 (XL_STAT_UP_COMPLETE|XL_STAT_STATSOFLOW|XL_STAT_ADFAIL| \
200 XL_STAT_DOWN_COMPLETE|XL_STAT_TX_COMPLETE|XL_STAT_INTLATCH)
205 #define XL_W0_EE_DATA 0x0C
206 #define XL_W0_EE_CMD 0x0A
207 #define XL_W0_RSRC_CFG 0x08
208 #define XL_W0_ADDR_CFG 0x06
209 #define XL_W0_CFG_CTRL 0x04
211 #define XL_W0_PROD_ID 0x02
212 #define XL_W0_MFG_ID 0x00
218 #define XL_W1_TX_FIFO 0x10
220 #define XL_W1_FREE_TX 0x0C
221 #define XL_W1_TX_STATUS 0x0B
222 #define XL_W1_TX_TIMER 0x0A
223 #define XL_W1_RX_STATUS 0x08
224 #define XL_W1_RX_FIFO 0x00
229 #define XL_RXSTATUS_OVERRUN 0x01
230 #define XL_RXSTATUS_RUNT 0x02
231 #define XL_RXSTATUS_ALIGN 0x04
232 #define XL_RXSTATUS_CRC 0x08
233 #define XL_RXSTATUS_OVERSIZE 0x10
234 #define XL_RXSTATUS_DRIBBLE 0x20
239 #define XL_TXSTATUS_RECLAIM 0x02 /* 3c905B only */
240 #define XL_TXSTATUS_OVERFLOW 0x04
241 #define XL_TXSTATUS_MAXCOLS 0x08
242 #define XL_TXSTATUS_UNDERRUN 0x10
243 #define XL_TXSTATUS_JABBER 0x20
244 #define XL_TXSTATUS_INTREQ 0x40
245 #define XL_TXSTATUS_COMPLETE 0x80
250 #define XL_W2_RESET_OPTIONS 0x0C /* 3c905B only */
251 #define XL_W2_STATION_MASK_HI 0x0A
252 #define XL_W2_STATION_MASK_MID 0x08
253 #define XL_W2_STATION_MASK_LO 0x06
254 #define XL_W2_STATION_ADDR_HI 0x04
255 #define XL_W2_STATION_ADDR_MID 0x02
256 #define XL_W2_STATION_ADDR_LO 0x00
258 #define XL_RESETOPT_FEATUREMASK (0x0001 | 0x0002 | 0x004)
259 #define XL_RESETOPT_D3RESETDIS 0x0008
260 #define XL_RESETOPT_DISADVFD 0x0010
261 #define XL_RESETOPT_DISADV100 0x0020
262 #define XL_RESETOPT_DISAUTONEG 0x0040
263 #define XL_RESETOPT_DEBUGMODE 0x0080
264 #define XL_RESETOPT_FASTAUTO 0x0100
265 #define XL_RESETOPT_FASTEE 0x0200
266 #define XL_RESETOPT_FORCEDCONF 0x0400
267 #define XL_RESETOPT_TESTPDTPDR 0x0800
268 #define XL_RESETOPT_TEST100TX 0x1000
269 #define XL_RESETOPT_TEST100RX 0x2000
271 #define XL_RESETOPT_INVERT_LED 0x0010
272 #define XL_RESETOPT_INVERT_MII 0x4000
275 * Window 3 (fifo management)
277 #define XL_W3_INTERNAL_CFG 0x00
278 #define XL_W3_MAXPKTSIZE 0x04 /* 3c905B only */
279 #define XL_W3_RESET_OPT 0x08
280 #define XL_W3_FREE_TX 0x0C
281 #define XL_W3_FREE_RX 0x0A
282 #define XL_W3_MAC_CTRL 0x06
284 #define XL_ICFG_CONNECTOR_MASK 0x00F00000
285 #define XL_ICFG_CONNECTOR_BITS 20
287 #define XL_ICFG_RAMSIZE_MASK 0x00000007
288 #define XL_ICFG_RAMWIDTH 0x00000008
289 #define XL_ICFG_ROMSIZE_MASK (0x00000040 | 0x00000080)
290 #define XL_ICFG_DISABLE_BASSD 0x00000100
291 #define XL_ICFG_RAMLOC 0x00000200
292 #define XL_ICFG_RAMPART (0x00010000 | 0x00020000)
293 #define XL_ICFG_XCVRSEL (0x00100000 | 0x00200000 | 0x00400000)
294 #define XL_ICFG_AUTOSEL 0x01000000
296 #define XL_XCVR_10BT 0x00
297 #define XL_XCVR_AUI 0x01
298 #define XL_XCVR_RSVD_0 0x02
299 #define XL_XCVR_COAX 0x03
300 #define XL_XCVR_100BTX 0x04
301 #define XL_XCVR_100BFX 0x05
302 #define XL_XCVR_MII 0x06
303 #define XL_XCVR_RSVD_1 0x07
304 #define XL_XCVR_AUTO 0x08 /* 3c905B only */
306 #define XL_MACCTRL_DEFER_EXT_END 0x0001
307 #define XL_MACCTRL_DEFER_0 0x0002
308 #define XL_MACCTRL_DEFER_1 0x0004
309 #define XL_MACCTRL_DEFER_2 0x0008
310 #define XL_MACCTRL_DEFER_3 0x0010
311 #define XL_MACCTRL_DUPLEX 0x0020
312 #define XL_MACCTRL_ALLOW_LARGE_PACK 0x0040
313 #define XL_MACCTRL_EXTEND_AFTER_COL 0x0080 /* 3c905B only */
314 #define XL_MACCTRL_FLOW_CONTROL_ENB 0x0100 /* 3c905B only */
315 #define XL_MACCTRL_VLT_END 0x0200 /* 3c905B only */
318 * The 'reset options' register contains power-on reset values
319 * loaded from the EEPROM. This includes the supported media
320 * types on the card. It is also known as the media options register.
322 #define XL_W3_MEDIA_OPT 0x08
324 #define XL_MEDIAOPT_BT4 0x0001 /* MII */
325 #define XL_MEDIAOPT_BTX 0x0002 /* on-chip */
326 #define XL_MEDIAOPT_BFX 0x0004 /* on-chip */
327 #define XL_MEDIAOPT_BT 0x0008 /* on-chip */
328 #define XL_MEDIAOPT_BNC 0x0010 /* on-chip */
329 #define XL_MEDIAOPT_AUI 0x0020 /* on-chip */
330 #define XL_MEDIAOPT_MII 0x0040 /* MII */
331 #define XL_MEDIAOPT_VCO 0x0100 /* 1st gen chip only */
333 #define XL_MEDIAOPT_10FL 0x0100 /* 3x905B only, on-chip */
334 #define XL_MEDIAOPT_MASK 0x01FF
337 * Window 4 (diagnostics)
339 #define XL_W4_UPPERBYTESOK 0x0D
340 #define XL_W4_BADSSD 0x0C
341 #define XL_W4_MEDIA_STATUS 0x0A
342 #define XL_W4_PHY_MGMT 0x08
343 #define XL_W4_NET_DIAG 0x06
344 #define XL_W4_FIFO_DIAG 0x04
345 #define XL_W4_VCO_DIAG 0x02
347 #define XL_W4_CTRLR_STAT 0x08
348 #define XL_W4_TX_DIAG 0x00
350 #define XL_MII_CLK 0x01
351 #define XL_MII_DATA 0x02
352 #define XL_MII_DIR 0x04
354 #define XL_MEDIA_SQE 0x0008
355 #define XL_MEDIA_10TP 0x00C0
356 #define XL_MEDIA_LNK 0x0080
357 #define XL_MEDIA_LNKBEAT 0x0800
359 #define XL_MEDIASTAT_CRCSTRIP 0x0004
360 #define XL_MEDIASTAT_SQEENB 0x0008
361 #define XL_MEDIASTAT_COLDET 0x0010
362 #define XL_MEDIASTAT_CARRIER 0x0020
363 #define XL_MEDIASTAT_JABGUARD 0x0040
364 #define XL_MEDIASTAT_LINKBEAT 0x0080
365 #define XL_MEDIASTAT_JABDETECT 0x0200
366 #define XL_MEDIASTAT_POLREVERS 0x0400
367 #define XL_MEDIASTAT_LINKDETECT 0x0800
368 #define XL_MEDIASTAT_TXINPROG 0x1000
369 #define XL_MEDIASTAT_DCENB 0x4000
370 #define XL_MEDIASTAT_AUIDIS 0x8000
372 #define XL_NETDIAG_TEST_LOWVOLT 0x0001
373 #define XL_NETDIAG_ASIC_REVMASK \
374 (0x0002 | 0x0004 | 0x0008 | 0x0010 | 0x0020)
375 #define XL_NETDIAG_UPPER_BYTES_ENABLE 0x0040
376 #define XL_NETDIAG_STATS_ENABLED 0x0080
377 #define XL_NETDIAG_TX_FATALERR 0x0100
378 #define XL_NETDIAG_TRANSMITTING 0x0200
379 #define XL_NETDIAG_RX_ENABLED 0x0400
380 #define XL_NETDIAG_TX_ENABLED 0x0800
381 #define XL_NETDIAG_FIFO_LOOPBACK 0x1000
382 #define XL_NETDIAG_MAC_LOOPBACK 0x2000
383 #define XL_NETDIAG_ENDEC_LOOPBACK 0x4000
384 #define XL_NETDIAG_EXTERNAL_LOOP 0x8000
389 #define XL_W5_STAT_ENB 0x0C
390 #define XL_W5_INTR_ENB 0x0A
391 #define XL_W5_RECLAIM_THRESH 0x09 /* 3c905B only */
392 #define XL_W5_RX_FILTER 0x08
393 #define XL_W5_RX_EARLYTHRESH 0x06
394 #define XL_W5_TX_AVAILTHRESH 0x02
395 #define XL_W5_TX_STARTTHRESH 0x00
400 #define XL_RXFILTER_INDIVIDUAL 0x01
401 #define XL_RXFILTER_ALLMULTI 0x02
402 #define XL_RXFILTER_BROADCAST 0x04
403 #define XL_RXFILTER_ALLFRAMES 0x08
404 #define XL_RXFILTER_MULTIHASH 0x10 /* 3c905B only */
409 #define XL_W6_TX_BYTES_OK 0x0C
410 #define XL_W6_RX_BYTES_OK 0x0A
411 #define XL_W6_UPPER_FRAMES_OK 0x09
412 #define XL_W6_DEFERRED 0x08
413 #define XL_W6_RX_OK 0x07
414 #define XL_W6_TX_OK 0x06
415 #define XL_W6_RX_OVERRUN 0x05
416 #define XL_W6_COL_LATE 0x04
417 #define XL_W6_COL_SINGLE 0x03
418 #define XL_W6_COL_MULTIPLE 0x02
419 #define XL_W6_SQE_ERRORS 0x01
420 #define XL_W6_CARRIER_LOST 0x00
423 * Window 7 (bus master control)
425 #define XL_W7_BM_ADDR 0x00
426 #define XL_W7_BM_LEN 0x06
427 #define XL_W7_BM_STATUS 0x0B
428 #define XL_W7_BM_TIMEr 0x0A
429 #define XL_W7_BM_PME 0x0C
431 #define XL_BM_PME_WAKE 0x0001
432 #define XL_BM_PME_MAGIC 0x0002
433 #define XL_BM_PME_LINKCHG 0x0004
434 #define XL_BM_PME_WAKETIMER 0x0008
436 * bus master control registers
438 #define XL_BM_PKTSTAT 0x20
439 #define XL_BM_DOWNLISTPTR 0x24
440 #define XL_BM_FRAGADDR 0x28
441 #define XL_BM_FRAGLEN 0x2C
442 #define XL_BM_TXFREETHRESH 0x2F
443 #define XL_BM_UPPKTSTAT 0x30
444 #define XL_BM_UPLISTPTR 0x38
446 #define XL_LAST_FRAG 0x80000000
448 #define XL_MAXFRAGS 63
449 #define XL_RX_LIST_CNT 128
450 #define XL_TX_LIST_CNT 256
451 #define XL_RX_LIST_SZ \
452 (XL_RX_LIST_CNT * sizeof(struct xl_list_onefrag))
453 #define XL_TX_LIST_SZ \
454 (XL_TX_LIST_CNT * sizeof(struct xl_list))
455 #define XL_MIN_FRAMELEN 60
456 #define ETHER_ALIGN 2
457 #define XL_INC(x, y) (x) = (x + 1) % y
460 * Boomerang/Cyclone TX/RX list structure.
461 * For the TX lists, bits 0 to 12 of the status word indicate
463 * This looks suspiciously like the ThunderLAN, doesn't it.
466 u_int32_t xl_addr; /* 63 addr/len pairs */
471 u_int32_t xl_next; /* final entry has 0 nextptr */
473 struct xl_frag xl_frag[XL_MAXFRAGS];
476 struct xl_list_onefrag {
477 u_int32_t xl_next; /* final entry has 0 nextptr */
478 volatile u_int32_t xl_status;
479 volatile struct xl_frag xl_frag;
482 struct xl_list_data {
483 struct xl_list_onefrag *xl_rx_list;
484 struct xl_list *xl_tx_list;
485 u_int32_t xl_rx_dmaaddr;
486 bus_dma_tag_t xl_rx_tag;
487 bus_dmamap_t xl_rx_dmamap;
488 u_int32_t xl_tx_dmaaddr;
489 bus_dma_tag_t xl_tx_tag;
490 bus_dmamap_t xl_tx_dmamap;
494 struct xl_list *xl_ptr;
495 struct mbuf *xl_mbuf;
496 struct xl_chain *xl_next;
497 struct xl_chain *xl_prev;
502 struct xl_chain_onefrag {
503 struct xl_list_onefrag *xl_ptr;
504 struct mbuf *xl_mbuf;
505 struct xl_chain_onefrag *xl_next;
509 struct xl_chain_data {
510 struct xl_chain_onefrag xl_rx_chain[XL_RX_LIST_CNT];
511 struct xl_chain xl_tx_chain[XL_TX_LIST_CNT];
512 bus_dma_segment_t xl_tx_segs[XL_MAXFRAGS];
514 struct xl_chain_onefrag *xl_rx_head;
516 /* 3c90x "boomerang" queuing stuff */
517 struct xl_chain *xl_tx_head;
518 struct xl_chain *xl_tx_tail;
519 struct xl_chain *xl_tx_free;
521 /* 3c90xB "cyclone/hurricane/tornado" stuff */
527 #define XL_RXSTAT_LENMASK 0x00001FFF
528 #define XL_RXSTAT_UP_ERROR 0x00004000
529 #define XL_RXSTAT_UP_CMPLT 0x00008000
530 #define XL_RXSTAT_UP_OVERRUN 0x00010000
531 #define XL_RXSTAT_RUNT 0x00020000
532 #define XL_RXSTAT_ALIGN 0x00040000
533 #define XL_RXSTAT_CRC 0x00080000
534 #define XL_RXSTAT_OVERSIZE 0x00100000
535 #define XL_RXSTAT_DRIBBLE 0x00800000
536 #define XL_RXSTAT_UP_OFLOW 0x01000000
537 #define XL_RXSTAT_IPCKERR 0x02000000 /* 3c905B only */
538 #define XL_RXSTAT_TCPCKERR 0x04000000 /* 3c905B only */
539 #define XL_RXSTAT_UDPCKERR 0x08000000 /* 3c905B only */
540 #define XL_RXSTAT_BUFEN 0x10000000 /* 3c905B only */
541 #define XL_RXSTAT_IPCKOK 0x20000000 /* 3c905B only */
542 #define XL_RXSTAT_TCPCOK 0x40000000 /* 3c905B only */
543 #define XL_RXSTAT_UDPCKOK 0x80000000 /* 3c905B only */
545 #define XL_TXSTAT_LENMASK 0x00001FFF
546 #define XL_TXSTAT_CRCDIS 0x00002000
547 #define XL_TXSTAT_TX_INTR 0x00008000
548 #define XL_TXSTAT_DL_COMPLETE 0x00010000
549 #define XL_TXSTAT_IPCKSUM 0x02000000 /* 3c905B only */
550 #define XL_TXSTAT_TCPCKSUM 0x04000000 /* 3c905B only */
551 #define XL_TXSTAT_UDPCKSUM 0x08000000 /* 3c905B only */
552 #define XL_TXSTAT_RND_DEFEAT 0x10000000 /* 3c905B only */
553 #define XL_TXSTAT_EMPTY 0x20000000 /* 3c905B only */
554 #define XL_TXSTAT_DL_INTR 0x80000000
556 #define XL_CAPABILITY_BM 0x20
565 * The 3C905B adapters implement a few features that we want to
566 * take advantage of, namely the multicast hash filter. With older
567 * chips, you only have the option of turning on reception of all
568 * multicast frames, which is kind of lame.
570 * We also use this to decide on a transmit strategy. For the 3c90xB
571 * cards, we can use polled descriptor mode, which reduces CPU overhead.
573 #define XL_TYPE_905B 1
574 #define XL_TYPE_90X 2
576 #define XL_FLAG_FUNCREG 0x0001
577 #define XL_FLAG_PHYOK 0x0002
578 #define XL_FLAG_EEPROM_OFFSET_30 0x0004
579 #define XL_FLAG_WEIRDRESET 0x0008
580 #define XL_FLAG_8BITROM 0x0010
581 #define XL_FLAG_INVERT_LED_PWR 0x0020
582 #define XL_FLAG_INVERT_MII_PWR 0x0040
583 #define XL_FLAG_NO_XCVR_PWR 0x0080
584 #define XL_FLAG_USE_MMIO 0x0100
585 #define XL_FLAG_NO_MMIO 0x0200
586 #define XL_FLAG_WOL 0x0400
588 #define XL_NO_XCVR_PWR_MAGICBITS 0x0900
591 struct ifnet *xl_ifp; /* interface info */
592 device_t xl_dev; /* device info */
593 struct ifmedia ifmedia; /* media info */
594 bus_space_handle_t xl_bhandle;
595 bus_space_tag_t xl_btag;
597 struct resource *xl_irq;
598 struct resource *xl_res;
600 const struct xl_type *xl_info; /* 3Com adapter info */
601 bus_dma_tag_t xl_mtag;
602 bus_dmamap_t xl_tmpmap; /* spare DMA map */
607 u_int16_t xl_tx_thresh;
610 struct xl_list_data xl_ldata;
611 struct xl_chain_data xl_cdata;
612 struct callout xl_tick_callout;
615 struct resource *xl_fres;
616 bus_space_handle_t xl_fhandle;
617 bus_space_tag_t xl_ftag;
620 #ifdef DEVICE_POLLING
625 #define XL_LOCK(_sc) mtx_lock(&(_sc)->xl_mtx)
626 #define XL_UNLOCK(_sc) mtx_unlock(&(_sc)->xl_mtx)
627 #define XL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->xl_mtx, MA_OWNED)
629 #define xl_rx_goodframes(x) \
630 ((x.xl_upper_frames_ok & 0x03) << 8) | x.xl_rx_frames_ok
632 #define xl_tx_goodframes(x) \
633 ((x.xl_upper_frames_ok & 0x30) << 4) | x.xl_tx_frames_ok
636 u_int8_t xl_carrier_lost;
637 u_int8_t xl_sqe_errs;
638 u_int8_t xl_tx_multi_collision;
639 u_int8_t xl_tx_single_collision;
640 u_int8_t xl_tx_late_collision;
641 u_int8_t xl_rx_overrun;
642 u_int8_t xl_tx_frames_ok;
643 u_int8_t xl_rx_frames_ok;
644 u_int8_t xl_tx_deferred;
645 u_int8_t xl_upper_frames_ok;
646 u_int16_t xl_rx_bytes_ok;
647 u_int16_t xl_tx_bytes_ok;
652 * register space access macros
654 #define CSR_WRITE_4(sc, reg, val) \
655 bus_space_write_4(sc->xl_btag, sc->xl_bhandle, reg, val)
656 #define CSR_WRITE_2(sc, reg, val) \
657 bus_space_write_2(sc->xl_btag, sc->xl_bhandle, reg, val)
658 #define CSR_WRITE_1(sc, reg, val) \
659 bus_space_write_1(sc->xl_btag, sc->xl_bhandle, reg, val)
661 #define CSR_READ_4(sc, reg) \
662 bus_space_read_4(sc->xl_btag, sc->xl_bhandle, reg)
663 #define CSR_READ_2(sc, reg) \
664 bus_space_read_2(sc->xl_btag, sc->xl_bhandle, reg)
665 #define CSR_READ_1(sc, reg) \
666 bus_space_read_1(sc->xl_btag, sc->xl_bhandle, reg)
668 #define CSR_BARRIER(sc, reg, length, flags) \
669 bus_space_barrier(sc->xl_btag, sc->xl_bhandle, reg, length, flags)
671 #define XL_SEL_WIN(x) do { \
672 CSR_BARRIER(sc, XL_COMMAND, 2, \
673 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); \
674 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_WINSEL | x); \
675 CSR_BARRIER(sc, XL_COMMAND, 2, \
676 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); \
679 #define XL_TIMEOUT 1000
682 * General constants that are fun to know.
686 #define TC_VENDORID 0x10B7
689 * 3Com chip device IDs.
691 #define TC_DEVICEID_BOOMERANG_10BT 0x9000
692 #define TC_DEVICEID_BOOMERANG_10BT_COMBO 0x9001
693 #define TC_DEVICEID_BOOMERANG_10_100BT 0x9050
694 #define TC_DEVICEID_BOOMERANG_100BT4 0x9051
695 #define TC_DEVICEID_KRAKATOA_10BT 0x9004
696 #define TC_DEVICEID_KRAKATOA_10BT_COMBO 0x9005
697 #define TC_DEVICEID_KRAKATOA_10BT_TPC 0x9006
698 #define TC_DEVICEID_CYCLONE_10FL 0x900A
699 #define TC_DEVICEID_HURRICANE_10_100BT 0x9055
700 #define TC_DEVICEID_CYCLONE_10_100BT4 0x9056
701 #define TC_DEVICEID_CYCLONE_10_100_COMBO 0x9058
702 #define TC_DEVICEID_CYCLONE_10_100FX 0x905A
703 #define TC_DEVICEID_TORNADO_10_100BT 0x9200
704 #define TC_DEVICEID_TORNADO_10_100BT_920B 0x9201
705 #define TC_DEVICEID_TORNADO_10_100BT_920B_WNM 0x9202
706 #define TC_DEVICEID_HURRICANE_10_100BT_SERV 0x9800
707 #define TC_DEVICEID_TORNADO_10_100BT_SERV 0x9805
708 #define TC_DEVICEID_HURRICANE_SOHO100TX 0x7646
709 #define TC_DEVICEID_TORNADO_HOMECONNECT 0x4500
710 #define TC_DEVICEID_HURRICANE_555 0x5055
711 #define TC_DEVICEID_HURRICANE_556 0x6055
712 #define TC_DEVICEID_HURRICANE_556B 0x6056
713 #define TC_DEVICEID_HURRICANE_575A 0x5057
714 #define TC_DEVICEID_HURRICANE_575B 0x5157
715 #define TC_DEVICEID_HURRICANE_575C 0x5257
716 #define TC_DEVICEID_HURRICANE_656 0x6560
717 #define TC_DEVICEID_HURRICANE_656B 0x6562
718 #define TC_DEVICEID_TORNADO_656C 0x6564
721 * PCI low memory base and low I/O base register, and
722 * other PCI registers. Note: some are only available on
723 * the 3c905B, in particular those that related to power management.
725 #define XL_PCI_VENDOR_ID 0x00
726 #define XL_PCI_DEVICE_ID 0x02
727 #define XL_PCI_COMMAND 0x04
728 #define XL_PCI_STATUS 0x06
729 #define XL_PCI_CLASSCODE 0x09
730 #define XL_PCI_LATENCY_TIMER 0x0D
731 #define XL_PCI_HEADER_TYPE 0x0E
732 #define XL_PCI_LOIO 0x10
733 #define XL_PCI_LOMEM 0x14
734 #define XL_PCI_FUNCMEM 0x18
735 #define XL_PCI_BIOSROM 0x30
736 #define XL_PCI_INTLINE 0x3C
737 #define XL_PCI_INTPIN 0x3D
738 #define XL_PCI_MINGNT 0x3E
739 #define XL_PCI_MINLAT 0x0F
740 #define XL_PCI_RESETOPT 0x48
741 #define XL_PCI_EEPROM_DATA 0x4C
743 /* 3c905B-only registers */
744 #define XL_PCI_CAPID 0xDC /* 8 bits */
745 #define XL_PCI_NEXTPTR 0xDD /* 8 bits */
746 #define XL_PCI_PWRMGMTCAP 0xDE /* 16 bits */
747 #define XL_PCI_PWRMGMTCTRL 0xE0 /* 16 bits */
749 #define XL_PSTATE_MASK 0x0003
750 #define XL_PSTATE_D0 0x0000
751 #define XL_PSTATE_D1 0x0002
752 #define XL_PSTATE_D2 0x0002
753 #define XL_PSTATE_D3 0x0003
754 #define XL_PME_EN 0x0010
755 #define XL_PME_STATUS 0x8000
758 #define IFM_10_FL 13 /* 10baseFL - Fiber */