2 * Copyright (c) 1994 Gordon W. Ross
3 * Copyright (c) 1992, 1993
4 * The Regents of the University of California. All rights reserved.
6 * This software was developed by the Computer Systems Engineering group
7 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
8 * contributed to Berkeley.
10 * All advertising materials mentioning features or use of this software
11 * must display the following acknowledgement:
12 * This product includes software developed by the University of
13 * California, Lawrence Berkeley Laboratory.
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 * 4. Neither the name of the University nor the names of its contributors
24 * may be used to endorse or promote products derived from this software
25 * without specific prior written permission.
27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
39 * @(#)zs.c 8.1 (Berkeley) 7/19/93
42 #include <sys/cdefs.h>
43 __FBSDID("$FreeBSD$");
45 * Copyright (c) 2003 Jake Burkholder.
46 * All rights reserved.
48 * Redistribution and use in source and binary forms, with or without
49 * modification, are permitted provided that the following conditions
51 * 1. Redistributions of source code must retain the above copyright
52 * notice, this list of conditions and the following disclaimer.
53 * 2. Redistributions in binary form must reproduce the above copyright
54 * notice, this list of conditions and the following disclaimer in the
55 * documentation and/or other materials provided with the distribution.
57 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
58 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
59 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
60 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
61 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
62 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
63 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
64 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
65 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
66 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
72 * Zilog Z8530 Dual UART driver.
75 #include "opt_comconsole.h"
77 #include <sys/param.h>
78 #include <sys/systm.h>
82 #include <sys/fcntl.h>
83 #include <sys/interrupt.h>
85 #include <sys/kernel.h>
87 #include <sys/mutex.h>
89 #include <machine/bus.h>
90 #include <machine/resource.h>
92 #include <sys/serial.h>
93 #include <sys/syslog.h>
96 #include <dev/zs/z8530reg.h>
97 #include <dev/zs/z8530var.h>
99 #define ZS_READ(sc, r) \
100 bus_space_read_1((sc)->sc_bt, (r), 0)
101 #define ZS_WRITE(sc, r, v) \
102 bus_space_write_1((sc)->sc_bt, (r), 0, (v))
104 #define ZS_READ_REG(sc, r) ({ \
105 ZS_WRITE((sc), (sc)->sc_csr, (r)); \
106 ZS_READ((sc), (sc)->sc_csr); \
109 #define ZS_WRITE_REG(sc, r, v) ({ \
110 ZS_WRITE((sc), (sc)->sc_csr, (r)); \
111 ZS_WRITE((sc), (sc)->sc_csr, (v)); \
114 #define ZSTTY_LOCK(sz) mtx_lock_spin(&(sc)->sc_mtx)
115 #define ZSTTY_UNLOCK(sz) mtx_unlock_spin(&(sc)->sc_mtx)
117 static void zs_softintr(void *v);
118 static void zs_shutdown(void *v);
120 static int zstty_intr(struct zstty_softc *sc, uint8_t rr3);
121 static void zstty_softintr(struct zstty_softc *sc) __unused;
122 static int zstty_param(struct zstty_softc *sc, struct tty *tp,
124 static void zstty_flush(struct zstty_softc *sc) __unused;
125 static int zstty_speed(struct zstty_softc *sc, int rate);
126 static void zstty_load_regs(struct zstty_softc *sc);
128 static cn_probe_t zs_cnprobe;
129 static cn_init_t zs_cninit;
130 static cn_term_t zs_cnterm;
131 static cn_getc_t zs_cngetc;
132 static cn_checkc_t zs_cncheckc;
133 static cn_putc_t zs_cnputc;
134 static cn_dbctl_t zs_cndbctl;
136 static int zstty_cngetc(struct zstty_softc *sc);
137 static int zstty_cncheckc(struct zstty_softc *sc);
138 static void zstty_cnputc(struct zstty_softc *sc, int c);
140 static d_open_t zsttyopen;
141 static d_close_t zsttyclose;
143 static void zsttystart(struct tty *tp);
144 static void zsttystop(struct tty *tp, int rw);
145 static int zsttyparam(struct tty *tp, struct termios *t);
146 static void zsttybreak(struct tty *tp, int brk);
147 static int zsttymodem(struct tty *tp, int biton, int bitoff);
149 static struct cdevsw zstty_cdevsw = {
150 .d_version = D_VERSION,
152 .d_close = zsttyclose,
154 .d_flags = D_TTY | D_NEEDGIANT,
157 static struct zstty_softc *zstty_cons;
159 CONS_DRIVER(zs, zs_cnprobe, zs_cninit, zs_cnterm, zs_cngetc, zs_cncheckc,
160 zs_cnputc, zs_cndbctl);
163 zs_probe(device_t dev)
166 device_set_desc(dev, "Zilog Z8530");
171 zs_attach(device_t dev)
173 struct device *child[ZS_NCHAN];
177 sc = device_get_softc(dev);
180 for (i = 0; i < ZS_NCHAN; i++)
181 child[i] = device_add_child(dev, "zstty", -1);
182 bus_generic_attach(dev);
183 for (i = 0; i < ZS_NCHAN; i++)
184 sc->sc_child[i] = device_get_softc(child[i]);
186 swi_add(&tty_ithd, "tty:zs", zs_softintr, sc, SWI_TTY,
187 INTR_TYPE_TTY, &sc->sc_softih);
189 ZS_WRITE_REG(sc->sc_child[0], 2, sc->sc_child[0]->sc_creg[2]);
190 ZS_WRITE_REG(sc->sc_child[0], 9, sc->sc_child[0]->sc_creg[9]);
192 if (zstty_cons != NULL) {
197 EVENTHANDLER_REGISTER(shutdown_final, zs_shutdown, sc,
198 SHUTDOWN_PRI_DEFAULT);
206 struct zs_softc *sc = v;
211 * There is only one status register, which is on channel a. In order
212 * to avoid needing to know which channel we're on in the tty interrupt
213 * handler we shift the channel a status bits into the channel b
214 * bit positions and always test the channel b bits.
217 rr3 = ZS_READ_REG(sc->sc_child[0], 3);
218 if ((rr3 & (ZSRR3_IP_A_RX | ZSRR3_IP_A_TX | ZSRR3_IP_A_STAT)) != 0)
219 needsoft |= zstty_intr(sc->sc_child[0], rr3 >> 3);
220 if ((rr3 & (ZSRR3_IP_B_RX | ZSRR3_IP_B_TX | ZSRR3_IP_B_STAT)) != 0)
221 needsoft |= zstty_intr(sc->sc_child[1], rr3);
223 swi_sched(sc->sc_softih, 0);
229 struct zs_softc *sc = v;
231 zstty_softintr(sc->sc_child[0]);
232 zstty_softintr(sc->sc_child[1]);
241 zstty_probe(device_t dev)
247 zstty_attach(device_t dev)
249 struct zstty_softc *sc;
259 sc = device_get_softc(dev);
260 mtx_init(&sc->sc_mtx, "zstty", NULL, MTX_SPIN);
262 sc->sc_iput = sc->sc_iget = sc->sc_ibuf;
263 sc->sc_oget = sc->sc_obuf;
267 sc->sc_si = make_dev(&zstty_cdevsw, device_get_unit(dev),
268 UID_ROOT, GID_WHEEL, 0600, "%s", device_get_desc(dev));
269 sc->sc_si->si_drv1 = sc;
270 sc->sc_si->si_tty = tp;
271 tp->t_dev = sc->sc_si;
274 tp->t_oproc = zsttystart;
275 tp->t_param = zsttyparam;
276 tp->t_modem = zsttymodem;
277 tp->t_break = zsttybreak;
278 tp->t_stop = zsttystop;
279 ttyinitmode(tp, 0, 0);
280 tp->t_cflag = CREAD | CLOCAL | CS8;
282 if (zstty_console(dev, mode, sizeof(mode))) {
284 /* format: 9600,8,n,1,- */
285 if (sscanf(mode, "%d,%d,%c,%d,%c", &baud, &clen, &parity,
289 tp->t_cflag = CREAD | CLOCAL;
307 tp->t_cflag |= PARENB;
308 else if (parity == 'o')
309 tp->t_cflag |= PARENB | PARODD;
312 tp->t_cflag |= CSTOPB;
314 device_printf(dev, "console %s\n", mode);
318 if ((device_get_unit(dev) & 1) == 0)
319 reset = ZSWR9_A_RESET;
321 reset = ZSWR9_B_RESET;
322 ZS_WRITE_REG(sc, 9, reset);
329 * Note that the rr3 value is shifted so the channel a status bits are in the
330 * channel b bit positions, which makes the bit positions uniform for both
334 zstty_intr(struct zstty_softc *sc, uint8_t rr3)
344 ZS_WRITE(sc, sc->sc_csr, ZSWR0_CLR_INTR);
348 if ((rr3 & ZSRR3_IP_B_RX) != 0) {
352 * First read the status, because reading the received
353 * char destroys the status of this char.
355 rr1 = ZS_READ_REG(sc, 1);
356 c = ZS_READ(sc, sc->sc_data);
358 if ((rr1 & (ZSRR1_FE | ZSRR1_DO | ZSRR1_PE)) != 0)
359 ZS_WRITE(sc, sc->sc_csr, ZSWR0_RESET_ERRORS);
360 #if defined(KDB) && defined(ALT_BREAK_TO_DEBUGGER)
361 if (sc->sc_console != 0)
362 brk = kdb_alt_break(c,
363 &sc->sc_alt_break_state);
366 *sc->sc_iput++ = rr1;
367 if (sc->sc_iput == sc->sc_ibuf + sizeof(sc->sc_ibuf))
368 sc->sc_iput = sc->sc_ibuf;
369 } while ((ZS_READ(sc, sc->sc_csr) & ZSRR0_RX_READY) != 0);
372 if ((rr3 & ZSRR3_IP_B_STAT) != 0) {
373 rr0 = ZS_READ(sc, sc->sc_csr);
374 ZS_WRITE(sc, sc->sc_csr, ZSWR0_RESET_STATUS);
375 #if defined(KDB) && defined(BREAK_TO_DEBUGGER)
376 if (sc->sc_console != 0 && (rr0 & ZSRR0_BREAK) != 0)
379 /* XXX do something about flow control */
382 if ((rr3 & ZSRR3_IP_B_TX) != 0) {
384 * If we've delayed a paramter change, do it now.
386 if (sc->sc_preg_held) {
387 sc->sc_preg_held = 0;
390 if (sc->sc_ocnt > 0) {
391 ZS_WRITE(sc, sc->sc_data, *sc->sc_oget++);
395 * Disable transmit completion interrupts if
398 if ((sc->sc_preg[1] & ZSWR1_TIE) != 0) {
399 sc->sc_preg[1] &= ~ZSWR1_TIE;
400 sc->sc_creg[1] = sc->sc_preg[1];
401 ZS_WRITE_REG(sc, 1, sc->sc_creg[1]);
418 zstty_softintr(struct zstty_softc *sc)
420 struct tty *tp = sc->sc_tty;
424 if ((tp->t_state & TS_ISOPEN) == 0)
427 while (sc->sc_iget != sc->sc_iput) {
428 data = *sc->sc_iget++;
429 stat = *sc->sc_iget++;
430 if ((stat & ZSRR1_PE) != 0)
432 if ((stat & ZSRR1_FE) != 0)
434 if (sc->sc_iget == sc->sc_ibuf + sizeof(sc->sc_ibuf))
435 sc->sc_iget = sc->sc_ibuf;
437 ttyld_rint(tp, data);
440 if (sc->sc_tx_done != 0) {
442 tp->t_state &= ~TS_BUSY;
448 zsttyopen(struct cdev *dev, int flags, int mode, struct thread *td)
450 struct zstty_softc *sc;
457 if ((tp->t_state & TS_ISOPEN) != 0 &&
458 (tp->t_state & TS_XCLUDE) != 0 &&
462 if ((tp->t_state & TS_ISOPEN) == 0) {
466 * Enable receive and status interrupts in zstty_param.
468 sc->sc_preg[1] |= ZSWR1_RIE | ZSWR1_SIE;
469 sc->sc_iput = sc->sc_iget = sc->sc_ibuf;
471 ttyconsolemode(tp, 0);
472 /* Make sure zstty_param() will do something. */
474 (void)zstty_param(sc, tp, &t);
478 /* XXX turn on DTR */
480 /* XXX handle initial DCD */
483 error = tty_open(dev, tp);
487 error = ttyld_open(tp, dev);
495 zsttyclose(struct cdev *dev, int flags, int mode, struct thread *td)
501 if ((tp->t_state & TS_ISOPEN) == 0)
504 ttyld_close(tp, flags);
511 zsttystart(struct tty *tp)
513 struct zstty_softc *sc;
518 if ((tp->t_state & TS_TBLOCK) != 0)
523 if ((tp->t_state & (TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) != 0) {
528 if (tp->t_outq.c_cc <= tp->t_olowat) {
529 if ((tp->t_state & TS_SO_OLOWAT) != 0) {
530 tp->t_state &= ~TS_SO_OLOWAT;
531 wakeup(TSA_OLOWAT(tp));
533 selwakeuppri(&tp->t_wsel, TTOPRI);
534 if (tp->t_outq.c_cc == 0) {
535 if ((tp->t_state & (TS_BUSY | TS_SO_OCOMPLETE)) ==
536 TS_SO_OCOMPLETE && tp->t_outq.c_cc == 0) {
537 tp->t_state &= ~TS_SO_OCOMPLETE;
538 wakeup(TSA_OCOMPLETE(tp));
544 sc->sc_ocnt = q_to_b(&tp->t_outq, sc->sc_obuf, sizeof(sc->sc_obuf));
545 if (sc->sc_ocnt == 0)
548 sc->sc_oget = sc->sc_obuf + 1;
551 tp->t_state |= TS_BUSY;
555 * Enable transmit interrupts if necessary and send the first
556 * character to start up the transmitter.
558 if ((sc->sc_preg[1] & ZSWR1_TIE) == 0) {
559 sc->sc_preg[1] |= ZSWR1_TIE;
560 sc->sc_creg[1] = sc->sc_preg[1];
561 ZS_WRITE_REG(sc, 1, sc->sc_creg[1]);
563 ZS_WRITE(sc, sc->sc_data, c);
569 zsttystop(struct tty *tp, int flag)
571 struct zstty_softc *sc;
575 if ((flag & FREAD) != 0) {
576 /* XXX stop reading, anything to do? */;
579 if ((flag & FWRITE) != 0) {
580 if ((tp->t_state & TS_BUSY) != 0) {
582 if ((tp->t_state & TS_TTSTOP) == 0)
583 tp->t_state |= TS_FLUSH;
589 zsttyparam(struct tty *tp, struct termios *t)
591 struct zstty_softc *sc;
594 return (zstty_param(sc, tp, t));
599 zsttybreak(struct tty *tp, int brk)
601 struct zstty_softc *sc;
606 ZS_WRITE_REG(sc, 5, ZS_READ_REG(sc, 5) | ZSWR5_BREAK);
608 ZS_WRITE_REG(sc, 5, ZS_READ_REG(sc, 5) & ~ZSWR5_BREAK);
612 zsttymodem(struct tty *tp, int biton, int bitoff)
619 zstty_param(struct zstty_softc *sc, struct tty *tp, struct termios *t)
627 ospeed = zstty_speed(sc, t->c_ospeed);
628 if (ospeed < 0 || (t->c_ispeed && t->c_ispeed != t->c_ospeed))
632 * If there were no changes, don't do anything. This avoids dropping
633 * input and improves performance when all we did was frob things like
636 if (tp->t_ospeed == t->c_ospeed &&
637 tp->t_cflag == t->c_cflag)
640 if (t->c_ospeed != 0)
641 zsttymodem(tp, SER_DTR, 0);
643 zsttymodem(tp, 0, SER_DTR);
647 if (sc->sc_console != 0) {
652 wr3 = ZSWR3_RX_ENABLE;
653 wr5 = ZSWR5_TX_ENABLE | ZSWR5_DTR | ZSWR5_RTS;
655 switch (cflag & CSIZE) {
675 wr4 = ZSWR4_CLK_X16 | (cflag & CSTOPB ? ZSWR4_TWOSB : ZSWR4_ONESB);
676 if ((cflag & PARODD) == 0)
682 tp->t_ospeed = t->c_ospeed;
689 sc->sc_preg[3] = wr3;
690 sc->sc_preg[4] = wr4;
691 sc->sc_preg[5] = wr5;
693 zstty_set_speed(sc, ospeed);
696 sc->sc_preg[15] |= ZSWR15_CTS_IE;
698 sc->sc_preg[15] &= ~ZSWR15_CTS_IE;
708 zstty_flush(struct zstty_softc *sc)
715 rr0 = ZS_READ(sc, sc->sc_csr);
716 if ((rr0 & ZSRR0_RX_READY) == 0)
719 rr1 = ZS_READ_REG(sc, 1);
720 c = ZS_READ(sc, sc->sc_data);
722 if (rr1 & (ZSRR1_FE | ZSRR1_DO | ZSRR1_PE))
723 ZS_WRITE(sc, sc->sc_data, ZSWR0_RESET_ERRORS);
728 zstty_load_regs(struct zstty_softc *sc)
732 * If the transmitter may be active, just hold the change and do it
733 * in the tx interrupt handler. Changing the registers while tx is
734 * active may hang the chip.
736 if (sc->sc_tx_busy != 0) {
737 sc->sc_preg_held = 1;
741 /* If the regs are the same do nothing. */
742 if (bcmp(sc->sc_preg, sc->sc_creg, 16) == 0)
745 bcopy(sc->sc_preg, sc->sc_creg, 16);
747 /* XXX: reset error condition */
748 ZS_WRITE(sc, sc->sc_csr, ZSM_RESET_ERR);
750 /* disable interrupts */
751 ZS_WRITE_REG(sc, 1, sc->sc_creg[1] & ~ZSWR1_IMASK);
753 /* baud clock divisor, stop bits, parity */
754 ZS_WRITE_REG(sc, 4, sc->sc_creg[4]);
756 /* misc. TX/RX control bits */
757 ZS_WRITE_REG(sc, 10, sc->sc_creg[10]);
759 /* char size, enable (RX/TX) */
760 ZS_WRITE_REG(sc, 3, sc->sc_creg[3] & ~ZSWR3_RX_ENABLE);
761 ZS_WRITE_REG(sc, 5, sc->sc_creg[5] & ~ZSWR5_TX_ENABLE);
763 /* Shut down the BRG */
764 ZS_WRITE_REG(sc, 14, sc->sc_creg[14] & ~ZSWR14_BAUD_ENA);
766 /* clock mode control */
767 ZS_WRITE_REG(sc, 11, sc->sc_creg[11]);
769 /* baud rate (lo/hi) */
770 ZS_WRITE_REG(sc, 12, sc->sc_creg[12]);
771 ZS_WRITE_REG(sc, 13, sc->sc_creg[13]);
773 /* Misc. control bits */
774 ZS_WRITE_REG(sc, 14, sc->sc_creg[14]);
776 /* which lines cause status interrupts */
777 ZS_WRITE_REG(sc, 15, sc->sc_creg[15]);
780 * Zilog docs recommend resetting external status twice at this
781 * point. Mainly as the status bits are latched, and the first
782 * interrupt clear might unlatch them to new values, generating
783 * a second interrupt request.
785 ZS_WRITE(sc, sc->sc_csr, ZSM_RESET_STINT);
786 ZS_WRITE(sc, sc->sc_csr, ZSM_RESET_STINT);
788 /* char size, enable (RX/TX)*/
789 ZS_WRITE_REG(sc, 3, sc->sc_creg[3]);
790 ZS_WRITE_REG(sc, 5, sc->sc_creg[5]);
792 /* interrupt enables: RX, TX, STATUS */
793 ZS_WRITE_REG(sc, 1, sc->sc_creg[1]);
797 zstty_speed(struct zstty_softc *sc, int rate)
803 tconst = BPS_TO_TCONST(sc->sc_brg_clk, rate);
804 if (tconst < 0 || TCONST_TO_BPS(sc->sc_brg_clk, tconst) != rate)
810 zs_cnprobe(struct consdev *cn)
812 struct zstty_softc *sc = zstty_cons;
815 cn->cn_pri = CN_DEAD;
817 cn->cn_pri = CN_REMOTE;
818 strcpy(cn->cn_name, devtoname(sc->sc_si));
819 cn->cn_tp = sc->sc_tty;
824 zs_cninit(struct consdev *cn)
829 zs_cnterm(struct consdev *cn)
834 zs_cngetc(struct consdev *cn)
836 struct zstty_softc *sc = zstty_cons;
840 return (zstty_cngetc(sc));
844 zs_cncheckc(struct consdev *cn)
846 struct zstty_softc *sc = zstty_cons;
850 return (zstty_cncheckc(sc));
854 zs_cnputc(struct consdev *cn, int c)
856 struct zstty_softc *sc = zstty_cons;
864 zs_cndbctl(struct consdev *cn, int c)
869 zstty_cnopen(struct zstty_softc *sc)
874 zstty_cnclose(struct zstty_softc *sc)
879 zstty_cngetc(struct zstty_softc *sc)
884 while ((ZS_READ(sc, sc->sc_csr) & ZSRR0_RX_READY) == 0)
886 c = ZS_READ(sc, sc->sc_data);
892 zstty_cncheckc(struct zstty_softc *sc)
898 if ((ZS_READ(sc, sc->sc_csr) & ZSRR0_RX_READY) != 0)
899 c = ZS_READ(sc, sc->sc_data);
905 zstty_cnputc(struct zstty_softc *sc, int c)
909 while ((ZS_READ(sc, sc->sc_csr) & ZSRR0_TX_READY) == 0)
911 ZS_WRITE(sc, sc->sc_data, c);