2 * Copyright (c) 2013 Ruslan Bukin <br@bsdpad.com>
3 * Copyright (c) 2015 Semihalf
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 model = "annapurna,alpine";
47 compatible = "arm,cortex-a15";
49 d-cache-line-size = <64>; // 64 bytes
50 i-cache-line-size = <64>; // 64 bytes
51 d-cache-size = <0x8000>; // L1, 32K
52 i-cache-size = <0x8000>; // L1, 32K
53 timebase-frequency = <0>;
54 bus-frequency = <375000000>;
55 clock-frequency = <0>;
60 compatible = "arm,cortex-a15";
62 d-cache-line-size = <64>; // 64 bytes
63 i-cache-line-size = <64>; // 64 bytes
64 d-cache-size = <0x8000>; // L1, 32K
65 i-cache-size = <0x8000>; // L1, 32K
66 timebase-frequency = <0>;
67 bus-frequency = <375000000>;
68 clock-frequency = <0>;
73 compatible = "arm,cortex-a15";
75 d-cache-line-size = <64>; // 64 bytes
76 i-cache-line-size = <64>; // 64 bytes
77 d-cache-size = <0x8000>; // L1, 32K
78 i-cache-size = <0x8000>; // L1, 32K
79 timebase-frequency = <0>;
80 bus-frequency = <375000000>;
81 clock-frequency = <0>;
86 compatible = "arm,cortex-a15";
88 d-cache-line-size = <64>; // 64 bytes
89 i-cache-line-size = <64>; // 64 bytes
90 d-cache-size = <0x8000>; // L1, 32K
91 i-cache-size = <0x8000>; // L1, 32K
92 timebase-frequency = <0>;
93 bus-frequency = <375000000>;
94 clock-frequency = <0>;
99 device_type = "memory";
100 reg = <0x00100000 0x7ff00000>; // 2047MB at 1MB
104 #address-cells = <1>;
106 compatible = "simple-bus";
107 ranges = <0x0 0xfb000000 0x03000000>;
110 MPIC: interrupt-controller {
111 compatible = "arm,gic";
112 reg = < 0x1000 0x1000 >, /* Distributor Registers */
113 < 0x2000 0x2000 >; /* CPU Interface Registers */
114 interrupt-controller;
115 #address-cells = <0>;
116 #interrupt-cells = <3>;
118 // In intr[2], bits[3:0] are trigger type and level flags.
119 // 1 = low-to-high edge triggered
120 // 2 = high-to-low edge triggered
121 // 4 = active high level-sensitive
122 // 8 = active low level-sensitive
123 // The hardware only supports active-high-level or rising-edge.
128 compatible = "arm,sp804";
129 reg = <0x02890000 0x1000>;
130 interrupts = <0 9 4>;
131 interrupt-parent = <&MPIC>;
132 clock-frequency = <375000000>;
136 compatible = "annapurna-labs,al-cpu-resume";
137 reg = <0x00ff5ec0 0x30>;
141 compatible = "annapurna-labs,al-ccu";
142 reg = <0x00090000 0x10000>;
147 compatible = "annapurna-labs,al-nb-service";
148 reg = <0x00070000 0x10000>;
149 interrupts = <0 32 4>,
153 interrupt-parent = <&MPIC>;
157 compatible = "arm,sp805", "arm,primecell";
158 reg = <0x288c000 0x1000>;
159 interrupt-parent = <&MPIC>;
164 compatible = "annapurna-labs,al-serdes";
165 reg = <0x28c0000 0x1000>;
168 serial0: serial@2883000 {
169 compatible = "ns16550";
170 reg = <0x2883000 0x20>;
172 current-speed = <115200>;
173 clock-frequency = <375000000>;
174 interrupts = <0 17 4>;
175 interrupt-parent = <&MPIC>;
179 /* MSIX Configuration */
181 compatible = "annapurna-labs,al-msix";
182 #address-cells = <2>;
184 reg = <0xfbe00000 0x100000>;
185 interrupts = <0 96 1 0 159 1>;
186 interrupt-parent = <&MPIC>;
190 compatible = "annapurna-labs,al-internal-pcie";
193 #address-cells = <3>;
194 reg = <0xfbc00000 0x100000>;
195 interrupt-parent = <&MPIC>;
196 interrupt-map-mask = <0xf800 0 0 7>;
197 interrupt-map = <0x3000 0 0 1 &MPIC 0 32 4>, // USB adapter
198 <0x3800 0 0 1 &MPIC 0 36 4>,
199 <0x4000 0 0 1 &MPIC 0 43 4>, // SATA 0 (PCIe expander)
200 <0x4800 0 0 1 &MPIC 0 44 1>; // SATA 1 (onboard)
201 msi-parent = <&msix>;
204 // - ECAM - non prefetchable config space
205 // - 32 bit non prefetchable memory space
206 ranges = <0x00000000 0x0 0xfbc00000 0xfbc00000 0x0 0x100000
207 0x02000000 0x0 0xfe000000 0xfe000000 0x0 0x1000000>;
209 bus-range = <0x00 0x00>;
212 // WORKAROUND: enabling PCIe controller when no card is plugged in
213 // leads to kernel panic because u-boot disables PCIe controller if no link
214 // is detected. Just be kind and compatible with Linux
215 /* // External PCIe Controller 0
217 compatible = "annapurna-labs,al-external-pcie";
218 reg = <0xfd800000 0x00020000>;
221 #address-cells = <3>;
222 interrupt-parent = <&MPIC>;
223 interrupt-map-mask = <0x00 0 0 7>;
224 interrupt-map = <0x0000 0 0 1 &MPIC 0 40 4>;
228 // - ECAM - non prefetchable config space: 2MB
229 // - IO - IO port space 64KB, reserve 64KB from target memory windows
230 // real IO address on the pci bus starts at 0x10000
231 // - 32 bit non prefetchable memory space: 128MB - 64KB
233 ranges = <0x00000000 0x0 0xfb600000 0xfb600000 0x0 0x00200000
234 0x01000000 0x0 0x00010000 0xe0000000 0x0 0x00010000
235 0x02000000 0x0 0xe1000000 0xe1000000 0x0 0x06f00000>;
237 bus-range = <0x00 0xff>;
240 // External PCIe Controllers 1
242 compatible = "annapurna-labs,al-external-pcie";
243 reg = <0xfd820000 0x00020000>;
246 #address-cells = <3>;
247 interrupt-parent = <&MPIC>;
248 interrupt-map-mask = <0x0 0 0 7>;
249 interrupt-map = <0x0000 0 0 1 &MPIC 0 41 4>;
252 // - ECAM - non prefetchable config space: 2MB
253 // - IO - IO port space 64KB, reserve 64KB from target memory windows
254 // real IO address on the pci bus starts at 0x20000
255 // - 32 bit non prefetchable memory space: 64MB - 64KB
256 ranges = <0x00000000 0x0 0xfb800000 0xfb800000 0x0 0x00200000
257 0x01000000 0x0 0x00020000 0xe8000000 0x0 0x00010000
258 0x02000000 0x0 0xe8100000 0xe8100000 0x0 0x02ff0000>;
260 bus-range = <0x00 0xff>;