2 * Device Tree Include file for Marvell Armada 380 SoC.
4 * Copyright (C) 2014 Marvell
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 * This file is dual-licensed: you can use it either under the terms
11 * of the GPL or the X11 license, at your option. Note that this dual
12 * licensing only applies to this file, and not this project as a
15 * a) This file is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of the
18 * License, or (at your option) any later version.
20 * This file is distributed in the hope that it will be useful
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
27 * b) Permission is hereby granted, free of charge, to any person
28 * obtaining a copy of this software and associated documentation
29 * files (the "Software"), to deal in the Software without
30 * restriction, including without limitation the rights to use
31 * copy, modify, merge, publish, distribute, sublicense, and/or
32 * sell copies of the Software, and to permit persons to whom the
33 * Software is furnished to do so, subject to the following
36 * The above copyright notice and this permission notice shall be
37 * included in all copies or substantial portions of the Software.
39 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
40 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
41 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
44 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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51 #include "armada-38x.dtsi"
54 model = "Marvell Armada 380 family SoC";
55 compatible = "marvell,armada380";
60 enable-method = "marvell,armada-380-smp";
64 compatible = "arm,cortex-a9";
72 compatible = "marvell,mv88f6810-pinctrl";
77 compatible = "marvell,armada-370-pcie";
85 bus-range = <0x00 0xff>;
88 <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
89 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
90 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
91 0x82000000 0x0 0xf1200000 MBUS_ID(0x08, 0xe8) 0xf1200000 0 0x00100000 /* Port 0 MEM */
92 0x81000000 0x0 0xf1300000 MBUS_ID(0x08, 0xe0) 0xf1300000 0 0x00100000 /* Port 0 IO */
93 0x82000000 0x0 0xf1400000 MBUS_ID(0x04, 0xe8) 0xf1400000 0 0x00100000 /* Port 1 MEM */
94 0x81000000 0x0 0xf1500000 MBUS_ID(0x04, 0xe0) 0xf1500000 0 0x00100000 /* Port 1 IO */
95 0x82000000 0x0 0xf1600000 MBUS_ID(0x04, 0xd8) 0xf1600000 0 0x00100000 /* Port 2 MEM */
96 0x81000000 0x0 0xf1700000 MBUS_ID(0x04, 0xd0) 0xf1700000 0 0x00100000 /* Port 2 IO */
101 compatible = "mrvl,pcie";
103 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
104 reg = <0x0 0x0 0x80000 0x0 0x2000>;
105 #address-cells = <3>;
107 #interrupt-cells = <3>;
109 ranges = <0x82000000 0x0 0x0 0x82000000 0x0 0xf1200000 0x0 0x00100000
110 0x81000000 0x0 0x0 0x81000000 0x0 0xf1300000 0x0 0x00100000>;
111 interrupt-map-mask = <0 0 0 0>;
112 interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
113 interrupt-parent = <&gic>;
114 marvell,pcie-port = <0>;
115 marvell,pcie-lane = <0>;
116 clocks = <&gateclk 8>;
122 compatible = "mrvl,pcie";
124 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
125 reg = <0x0 0x0 0x40000 0x0 0x2000>;
126 #address-cells = <3>;
128 #interrupt-cells = <3>;
130 ranges = <0x82000000 0x0 0x0 0x82000000 0x0 0xf1400000 0x0 0x00100000
131 0x81000000 0x0 0x0 0x81000000 0x0 0xf1500000 0x0 0x00100000>;
132 interrupt-map-mask = <0 0 0 0>;
133 interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
134 interrupt-parent = <&gic>;
135 marvell,pcie-port = <1>;
136 marvell,pcie-lane = <0>;
137 clocks = <&gateclk 5>;
143 compatible = "mrvl,pcie";
145 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
146 reg = <0x0 0x0 0x44000 0x0 0x2000>;
147 #address-cells = <3>;
149 #interrupt-cells = <3>;
151 ranges = <0x82000000 0x0 0x0 0x82000000 0x0 0xf1600000 0x0 0x00100000
152 0x81000000 0x0 0x0 0x81000000 0x0 0xf1700000 0x0 0x00100000>;
153 interrupt-map-mask = <0 0 0 0>;
154 interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
155 interrupt-parent = <&gic>;
156 marvell,pcie-port = <2>;
157 marvell,pcie-lane = <0>;
158 clocks = <&gateclk 6>;