2 * Device Tree Include file for Marvell Armada 385 SoC.
4 * Copyright (C) 2014 Marvell
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 * This file is dual-licensed: you can use it either under the terms
11 * of the GPL or the X11 license, at your option. Note that this dual
12 * licensing only applies to this file, and not this project as a
15 * a) This file is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of the
18 * License, or (at your option) any later version.
20 * This file is distributed in the hope that it will be useful
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
27 * b) Permission is hereby granted, free of charge, to any person
28 * obtaining a copy of this software and associated documentation
29 * files (the "Software"), to deal in the Software without
30 * restriction, including without limitation the rights to use
31 * copy, modify, merge, publish, distribute, sublicense, and/or
32 * sell copies of the Software, and to permit persons to whom the
33 * Software is furnished to do so, subject to the following
36 * The above copyright notice and this permission notice shall be
37 * included in all copies or substantial portions of the Software.
39 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
40 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
41 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
44 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
46 * OTHER DEALINGS IN THE SOFTWARE.
51 #include "armada-38x.dtsi"
54 model = "Marvell Armada 385 family SoC";
55 compatible = "marvell,armada385", "marvell,armada380";
60 enable-method = "marvell,armada-380-smp";
64 compatible = "arm,cortex-a9";
69 compatible = "arm,cortex-a9";
77 compatible = "marvell,mv88f6820-pinctrl";
82 compatible = "marvell,armada-370-pcie";
90 bus-range = <0x00 0xff>;
93 <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
94 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
95 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
96 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
97 0x82000000 0x0 0xf1200000 MBUS_ID(0x08, 0xe8) 0xf1200000 0 0x00100000 /* Port 0 MEM */
98 0x81000000 0x0 0xf1300000 MBUS_ID(0x08, 0xe0) 0xf1300000 0 0x00100000 /* Port 0 IO */
99 0x82000000 0x0 0xf1400000 MBUS_ID(0x04, 0xe8) 0xf1400000 0 0x00100000 /* Port 1 MEM */
100 0x81000000 0x0 0xf1500000 MBUS_ID(0x04, 0xe0) 0xf1500000 0 0x00100000 /* Port 1 IO */
101 0x82000000 0x0 0xf1600000 MBUS_ID(0x04, 0xd8) 0xf1600000 0 0x00100000 /* Port 2 MEM */
102 0x81000000 0x0 0xf1700000 MBUS_ID(0x04, 0xd0) 0xf1700000 0 0x00100000 /* Port 2 IO */
103 0x82000000 0x0 0xf1800000 MBUS_ID(0x04, 0xb8) 0xf1800000 0 0x00100000 /* Port 3 MEM */
104 0x81000000 0x0 0xf1900000 MBUS_ID(0x04, 0xb0) 0xf1900000 0 0x00100000 /* Port 3 IO */
108 * This port can be either x4 or x1. When
109 * configured in x4 by the bootloader, then
110 * pcie@4,0 is not available.
113 compatible = "mrvl,pcie";
115 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
116 reg = <0x0 0x0 0x80000 0x0 0x2000>;
117 #address-cells = <3>;
119 #interrupt-cells = <3>;
121 ranges = <0x82000000 0x0 0x0 0x82000000 0x0 0xf1200000 0x0 0x00100000
122 0x81000000 0x0 0x0 0x81000000 0x0 0xf1300000 0x0 0x00100000>;
123 interrupt-map-mask = <0 0 0 0>;
124 interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
125 interrupt-parent = <&gic>;
126 marvell,pcie-port = <0>;
127 marvell,pcie-lane = <0>;
128 clocks = <&gateclk 8>;
134 compatible = "mrvl,pcie";
136 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
137 reg = <0x0 0x0 0x40000 0x0 0x2000>;
138 #address-cells = <3>;
140 #interrupt-cells = <3>;
142 ranges = <0x82000000 0x0 0x0 0x82000000 0x0 0xf1400000 0x0 0x00100000
143 0x81000000 0x0 0x0 0x81000000 0x0 0xf1500000 0x0 0x00100000>;
144 interrupt-map-mask = <0 0 0 0>;
145 interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
146 interrupt-parent = <&gic>;
147 marvell,pcie-port = <1>;
148 marvell,pcie-lane = <0>;
149 clocks = <&gateclk 5>;
155 compatible = "mrvl,pcie";
157 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
158 reg = <0x0 0x0 0x44000 0x0 0x2000>;
159 #address-cells = <3>;
161 #interrupt-cells = <3>;
163 ranges = <0x82000000 0x0 0x0 0x82000000 0x0 0xf1600000 0x0 0x00100000
164 0x81000000 0x0 0x0 0x81000000 0x0 0xf1700000 0x0 0x00100000>;
165 interrupt-map-mask = <0 0 0 0>;
166 interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
167 interrupt-parent = <&gic>;
168 marvell,pcie-port = <2>;
169 marvell,pcie-lane = <0>;
170 clocks = <&gateclk 6>;
175 * x1 port only available when pcie@1,0 is
176 * configured as a x1 port
179 compatible = "mrvl,pcie";
181 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
182 reg = <0x0 0x0 0x48000 0x0 0x2000>;
183 #address-cells = <3>;
185 #interrupt-cells = <3>;
187 ranges = <0x82000000 0x0 0x0 0x82000000 0x0 0xf1800000 0x0 0x00100000
188 0x81000000 0x0 0x0 0x81000000 0x0 0xf1900000 0x0 0x00100000>;
189 interrupt-map-mask = <0 0 0 0>;
190 interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
191 interrupt-parent = <&gic>;
192 marvell,pcie-port = <3>;
193 marvell,pcie-lane = <0>;
194 clocks = <&gateclk 7>;