sys/dts/arm/rk3188.dtsi

   1 /*-
   2  * Copyright (c) 2013 Ganbold Tsagaankhuu <ganbold@freebsd.org>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  *
  26  * $FreeBSD$
  27  */
  28
  29 / {
  30         compatible = "rockchip,rk3188";
  31         #address-cells = <1>;
  32         #size-cells = <1>;
  33
  34         interrupt-parent = <&GIC>;
  35
  36         aliases {
  37                 soc = &SOC;
  38         };
  39
  40         SOC: rk3188 {
  41                 #address-cells = <1>;
  42                 #size-cells = <1>;
  43                 compatible = "simple-bus";
  44                 ranges;
  45                 bus-frequency = <0>;
  46
  47                 GIC: interrupt-controller@1013d000 {
  48                         compatible = "arm,gic";
  49                         reg =   <0x1013d000 0x1000>,    /* Distributor Registers */
  50                                 <0x1013c100 0x0100>;    /* CPU Interface Registers */
  51                         interrupt-controller;
  52                         #interrupt-cells = <1>;
  53                 };
  54
  55                 pmu@20004000 {
  56                         compatible = "rockchip,rk30xx-pmu";
  57                         #address-cells = <1>;
  58                         #size-cells = <1>;
  59                         reg = <0x20004000 0x100>;
  60                 };
  61
  62                 grf@20008000 {
  63                         compatible = "rockchip,rk30xx-grf";
  64                         #address-cells = <1>;
  65                         #size-cells = <1>;
  66                         reg = < 0x20008000 0x2000 >;
  67                 };
  68
  69                 mp_tmr@1013c600 {
  70                         compatible = "arm,mpcore-timers";
  71                         #address-cells = <1>;
  72                         #size-cells = <0>;
  73                         clock-frequency = < 148500000 >;
  74                         reg =   <0x1013c200 0x100>,     /* Global Timer Regs */
  75                                 <0x1013c600 0x20>;      /* Private Timer Regs */
  76                         interrupts = < 27 29 >;
  77                         interrupt-parent = <&GIC>;
  78                 };
  79
  80                 timer@20038000 {
  81                         compatible = "rockchip,rk30xx-timer";
  82                         reg = <0x20038000 0x20>;
  83                         interrupts = <76>;
  84                         clock-frequency = <24000000>;
  85                         status = "disabled";
  86                 };
  87
  88                 timer@20038020 {
  89                         compatible = "rockchip,rk30xx-timer";
  90                         reg = <0x20038020 0x20>;
  91                         interrupts = <77>;
  92                         clock-frequency = <24000000>;
  93                         status = "disabled";
  94                 };
  95
  96                 timer@20038060 {
  97                         compatible = "rockchip,rk30xx-timer";
  98                         reg = <0x20038060 0x20>;
  99                         interrupts = <91>;
 100                         clock-frequency = <24000000>;
 101                         status = "disabled";
 102                 };
 103
 104                 timer@20038080 {
 105                         compatible = "rockchip,rk30xx-timer";
 106                         reg = <0x20038080 0x20>;
 107                         interrupts = <92>;
 108                         clock-frequency = <24000000>;
 109                         status = "disabled";
 110                 };
 111
 112                 timer@200380a0 {
 113                         compatible = "rockchip,rk30xx-timer";
 114                         reg = <0x200380a0 0x20>;
 115                         interrupts = <96>;
 116                         clock-frequency = <24000000>;
 117                         status = "disabled";
 118                 };
 119
 120                 watchdog@2004c000 {
 121                         compatible = "rockchip,rk30xx-wdt";
 122                         reg = <0x2004c000 0x100>;
 123                         clock-frequency = < 66000000 >;
 124                 };
 125
 126                 gpio0: gpio@2000a000 {
 127                         compatible = "rockchip,rk30xx-gpio";
 128                         gpio-controller;
 129                         #gpio-cells = <2>;
 130                         reg = <0x2000a000 0x100>;
 131                         interrupts = <86>;
 132                         interrupt-parent = <&GIC>;
 133                 };
 134
 135                 gpio1: gpio@2003c000 {
 136                         compatible = "rockchip,rk30xx-gpio";
 137                         gpio-controller;
 138                         #gpio-cells = <2>;
 139                         reg = <0x2003c000 0x100>;
 140                         interrupts = <87>;
 141                         interrupt-parent = <&GIC>;
 142                 };
 143
 144                 gpio2: gpio@2003e000 {
 145                         compatible = "rockchip,rk30xx-gpio";
 146                         gpio-controller;
 147                         #gpio-cells = <2>;
 148                         reg = <0x2003e000 0x100>;
 149                         interrupts = <88>;
 150                         interrupt-parent = <&GIC>;
 151                 };
 152
 153                 gpio3: gpio@20080000 {
 154                         compatible = "rockchip,rk30xx-gpio";
 155                         gpio-controller;
 156                         #gpio-cells = <2>;
 157                         reg = <0x20080000 0x100>;
 158                         interrupts = <89>;
 159                         interrupt-parent = <&GIC>;
 160                 };
 161
 162                 usb0: usb@10180000 {
 163                         compatible = "synopsys,designware-hs-otg2";
 164                         reg = <0x10180000 0x40000>;
 165                         interrupts = <48>;
 166                         interrupt-parent = <&GIC>;
 167                         #address-cells = <1>;
 168                         #size-cells = <0>;
 169                 };
 170
 171                 usb1: usb@101c0000 {
 172                         compatible = "synopsys,designware-hs-otg2";
 173                         reg = <0x101c0000 0x40000>;
 174                         interrupts = < 49 >;
 175                         interrupt-parent = <&GIC>;
 176                         #address-cells = <1>;
 177                         #size-cells = <0>;
 178                         gpios = <&gpio0 3 2 2>;
 179                 };
 180
 181                 uart0: serial@10124000 {
 182                         compatible = "snps,dw-apb-uart";
 183                         reg = <0x10124000 0x400>;
 184                         reg-shift = <2>;
 185                         interrupts = <66>;
 186                         interrupt-parent = <&GIC>;
 187                         current-speed = <115200>;
 188                         clock-frequency = < 24000000 >;
 189                         broken-txfifo = <1>;
 190                         status = "disabled";
 191                 };
 192
 193                 uart1: serial@10126000 {
 194                         compatible = "snps,dw-apb-uart";
 195                         reg = <0x10126000 0x400>;
 196                         reg-shift = <2>;
 197                         interrupts = <67>;
 198                         interrupt-parent = <&GIC>;
 199                         current-speed = <115200>;
 200                         clock-frequency = < 24000000 >;
 201                         broken-txfifo = <1>;
 202                         status = "disabled";
 203                 };
 204
 205                 uart2: serial@20064000 {
 206                         compatible = "snps,dw-apb-uart";
 207                         reg = <0x20064000 0x400>;
 208                         reg-shift = <2>;
 209                         interrupts = <68>;
 210                         interrupt-parent = <&GIC>;
 211                         current-speed = <115200>;
 212                         clock-frequency = < 24000000 >;
 213                         broken-txfifo = <1>;
 214                         status = "disabled";
 215                 };
 216
 217                 uart3: serial@20068000 {
 218                         compatible = "snps,dw-apb-uart";
 219                         reg = <0x20068000 0x400>;
 220                         reg-shift = <2>;
 221                         interrupts = <69>;
 222                         interrupt-parent = <&GIC>;
 223                         current-speed = <115200>;
 224                         clock-frequency = < 24000000 >;
 225                         broken-txfifo = <1>;
 226                         status = "disabled";
 227                 };
 228
 229                 mmc@10214000 {
 230                         compatible = "rockchip,rk2928-dw-mshc";
 231                         reg = <0x10214000 0x1000>;
 232                         interrupts = <55>;
 233                         #address-cells = <1>;
 234                         #size-cells = <0>;
 235                         bus-frequency = <48000000>;     /* TODO: verify freq */
 236                         fifo-depth = <0x40>;
 237                         num-slots = <1>;
 238                         status = "disabled";
 239                 };
 240
 241                 mmc@10218000 {
 242                         compatible = "rockchip,rk2928-dw-mshc";
 243                         reg = <0x10218000 0x1000>;
 244                         interrupts = <56>;
 245                         #address-cells = <1>;
 246                         #size-cells = <0>;
 247                         bus-frequency = <48000000>;     /* TODO: verify freq */
 248                         fifo-depth = <0x40>;
 249                         num-slots = <1>;
 250                         status = "disabled";
 251                 };
 252         };
 253 };
 254