2 * Copyright (c) 2017 Ruslan Bukin <br@bsdpad.com>
5 * This software was developed by SRI International and the University of
6 * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
7 * ("CTSRD"), as part of the DARPA CRASH research programme.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include "socfpga_arria10_socdk.dtsi"
35 model = "Altera SOCFPGA Arria 10";
36 compatible = "altr,socfpga-arria10", "altr,socfpga";
38 /* Reserve first page for secondary CPU trampoline code */
39 memreserve = < 0x00000000 0x1000 >;
44 clock-frequency = <200000000>;
48 global_timer: timer@ffffc200 {
49 compatible = "arm,cortex-a9-global-timer";
50 reg = <0xffffc200 0x20>;
51 interrupts = <1 11 0x301>;
52 clock-frequency = <200000000>;
63 clock-frequency = < 50000000 >;
72 bus-frequency = <200000000>;
77 compatible = "newhaven,nhd-0216k3z-nsw-bbw";
89 dmas = <&pdma 24>, <&pdma 25>;
90 dma-names = "tx", "rx";
95 compatible = "n25q00aa";
97 spi-max-frequency = <100000000>;
100 cdns,page-size = <256>;
101 cdns,block-size = <16>;
102 cdns,read-delay = <4>;
103 cdns,tshsl-ns = <50>;
104 cdns,tsd2d-ns = <50>;
108 partition@qspi-boot {
110 reg = <0x0 0x2720000>;
113 partition@qspi-rootfs {
115 reg = <0x2720000 0x58E0000>;