2 * Copyright (c) 2012-2013 Robert N. M. Watson
3 * Copyright (c) 2013 SRI International
4 * Copyright (c) 2013-2014 Bjoern A. Zeeb
7 * This software was developed by SRI International and the University of
8 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
9 * ("CTSRD"), as part of the DARPA CRASH research programme.
11 * This software was developed by SRI International and the University of
12 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-11-C-0249)
13 * ("MRC2"), as part of the DARPA MRC research programme.
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
42 * Device names here have been largely made up on the spot, especially for the
43 * "compatible" strings, and might want to be revised.
47 model = "SRI/Cambridge Beri (NetFPGA)";
48 compatible = "sri-cambridge,beri-netfpga";
57 * Secondary CPUs all start disabled and use the
58 * spin-table enable method. cpu-release-addr must be
59 * specified for each cpu other than cpu@0. Values of
60 * cpu-release-addr grow down from 0x100000 (kernel).
63 enable-method = "spin-table";
67 compatible = "sri-cambridge,beri";
76 compatible = "sri-cambridge,beri";
79 // XXX: should we need cached prefix?
80 cpu-release-addr = <0xffffffff 0x800fffe0>;
86 device_type = "memory";
87 reg = <0x0 0x0FFFFFFF>; // ~256M at 0x0
92 #interrupt-cells = <1>;
94 compatible = "mti,cpu-interrupt-controller";
97 beripic: beripic@7f804000 {
98 compatible = "sri-cambridge,beri-pic";
100 #address-cells = <0>;
101 #interrupt-cells = <1>;
102 reg = <0x7f804000 0x400
106 interrupts = < 2 3 4 5 6 >;
107 hard-interrupt-sources = <64>;
108 soft-interrupt-sources = <64>;
109 interrupt-parent = <&cpuintc>;
113 #address-cells = <1>;
115 #interrupt-cells = <1>;
117 compatible = "simple-bus", "mips,mips4k";
120 serial0: serial@7f000000 {
121 compatible = "altera,jtag_uart-11_0";
122 reg = <0x7f000000 0x40>;
125 interrupt-parent = <&beripic>;
130 serial0: serial@7f002100 {
131 compatible = "ns16550";
132 reg = <0x7f002100 0x20>;
134 clock-frequency = <100000000>;
136 interrupt-parent = <&beripic>;
141 compatible = "netfpag10g,nf10bmac";
142 // LOOP, TX, RX, INTR
143 reg = <0x7f005000 0x20
149 interrupt-parent = <&beripic>;