sys/dts/mips/beripad-de4.dts

   1 /*-
   2  * Copyright (c) 2012-2013 Robert N. M. Watson
   3  * Copyright (c) 2013 SRI International
   4  * All rights reserved.
   5  *
   6  * This software was developed by SRI International and the University of
   7  * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
   8  * ("CTSRD"), as part of the DARPA CRASH research programme.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  23  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  24  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  25  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  29  * SUCH DAMAGE.
  30  *
  31  * $FreeBSD$
  32  */
  33
  34 /dts-v1/;
  35
  36 /*
  37  * Device names here have been largely made up on the spot, especially for the
  38  * "compatible" strings, and might want to be revised.
  39  *
  40  * For now, use 32-bit addressing as our Avalon bus is 32-bit.  However, in
  41  * the future, we should likely change to 64-bit.
  42  */
  43
  44 / {
  45         model = "SRI/Cambridge BeriPad (DE4)";
  46         compatible = "sri-cambridge,beripad-de4";
  47         #address-cells = <1>;
  48         #size-cells = <1>;
  49
  50         cpus {
  51                 #address-cells = <1>;
  52                 #size-cells = <1>;
  53
  54                 /*
  55                  * Secondary CPUs all start disabled and use the
  56                  * spin-table enable method.  cpu-release-addr must be
  57                  * specified for each cpu other than cpu@0.  Values of
  58                  * cpu-release-addr grow down from 0x100000 (kernel).
  59                  */
  60                 status = "disabled";
  61                 enable-method = "spin-table";
  62
  63                 cpu@0 {
  64                         device-type = "cpu";
  65                         compatible = "sri-cambridge,beri";
  66
  67                         reg = <0 1>;
  68                         status = "okay";
  69                 };
  70
  71 /*
  72                 cpu@1 {
  73                         device-type = "cpu";
  74                         compatible = "sri-cambridge,beri";
  75
  76                         reg = <1 1>;
  77                         // XXX: should we need cached prefix?
  78                         cpu-release-addr = <0xffffffff 0x800fffe0>;
  79                 };
  80 */
  81         };
  82
  83         memory {
  84                 device_type = "memory";
  85                 reg = <0x0 0x40000000>;         // 1G at 0x0
  86         };
  87
  88         cpuintc: cpuintc@0 {
  89                 #address-cells = <0>;
  90                 #interrupt-cells = <1>;
  91                 interrupt-controller;
  92                 compatible = "mti,cpu-interrupt-controller";
  93         };
  94
  95         beripic0: beripic@7f804000 {
  96                 compatible = "sri-cambridge,beri-pic";
  97                 interrupt-controller;
  98                 #address-cells = <0>;
  99                 #interrupt-cells = <1>;
 100                 reg = <0x7f804000 0x400
 101                        0x7f806000 0x10
 102                        0x7f806080 0x10
 103                        0x7f806100 0x10>;
 104                 interrupts = < 2 3 4 5 6 >;
 105                 hard-interrupt-sources = <64>;
 106                 soft-interrupt-sources = <64>;
 107                 interrupt-parent = <&cpuintc>;
 108         };
 109
 110 /*
 111         beripic1: beripic@7f808000 {
 112                 compatible = "sri-cambridge,beri-pic";
 113                 interrupt-controller;
 114                 #address-cells = <0>;
 115                 #interrupt-cells = <1>;
 116                 reg = <0x7f808000 0x400
 117                        0x7f80a000 0x10
 118                        0x7f80a080 0x10
 119                        0x7f80a100 0x10>;
 120                 interrupts = < 2 3 4 5 6 >;
 121                 hard-interrupt-sources = <64>;
 122                 soft-interrupt-sources = <64>;
 123                 interrupt-parent = <&cpuintc>;
 124         };
 125 */
 126
 127         soc {
 128                 #address-cells = <1>;
 129                 #size-cells = <1>;
 130                 #interrupt-cells = <1>;
 131
 132                 compatible = "simple-bus", "mips,mips4k";
 133                 ranges;
 134
 135                 serial@7f002100 {
 136                         compatible = "ns16550";
 137                         reg = <0x7f002100 0x20>;
 138                         reg-shift = <2>;
 139                         clock-frequency = <50000000>;
 140                         interrupts = <6>;
 141                         interrupt-parent = <&beripic0>;
 142                 };
 143
 144                 serial@7f000000 {
 145                         compatible = "altera,jtag_uart-11_0";
 146                         reg = <0x7f000000 0x40>;
 147                         interrupts = <0>;
 148                         interrupt-parent = <&beripic0>;
 149                 };
 150
 151                 serial@7f001000 {
 152                         compatible = "altera,jtag_uart-11_0";
 153                         reg = <0x7f001000 0x40>;
 154                 };
 155
 156                 serial@7f002000 {
 157                         compatible = "altera,jtag_uart-11_0";
 158                         reg = <0x7f002000 0x40>;
 159                 };
 160
 161                 sdcard@7f008000 {
 162                         compatible = "altera,sdcard_11_2011";
 163                         reg = <0x7f008000 0x400>;
 164                 };
 165
 166                 led@7f006000 {
 167                         compatible = "sri-cambridge,de4led";
 168                         reg = <0x7f006000 0x1>;
 169                 };
 170
 171                 /*
 172                  * XXX-BZ keep flash before ethernet so that atse can read the
 173                  * Ethernet addresses for now.
 174                  */
 175                 flash@74000000 {
 176                         #address-cells = <1>;
 177                         #size-cells = <1>;
 178                         compatible = "cfi-flash";
 179                         reg = <0x74000000 0x4000000>;
 180
 181                         /* Board configuration */
 182                         partition@0 {
 183                                 reg = <0x0 0x20000>;
 184                                 label = "config";
 185                         };
 186
 187                         /* Power up FPGA image */
 188                         partition@20000 {
 189                                 reg = <0x20000 0xc00000>;
 190                                 label = "fpga0";
 191                         };
 192
 193                         /* Secondary FPGA image (on RE_CONFIGn button) */
 194                         partition@C20000 {
 195                                 reg = <0xc20000 0xc00000>;
 196                                 label = "fpga1";
 197                         };
 198
 199                         /* Space for operating system use */
 200                         partition@1820000 {
 201                                 reg = <0x1820000 0x027c0000>;
 202                                 label = "os";
 203                         };
 204
 205                         /* Second stage bootloader */
 206                         parition@3fe0000 {
 207                                 reg = <0x3fe0000 0x20000>;
 208                                 label = "boot";
 209                         };
 210                 };
 211
 212                 msgdma0: msgdma@80004080 {
 213                         compatible = "altr,msgdma-16.0", "altr,msgdma-1.0";
 214                         reg = <0x80004080 0x00000020>,
 215                               <0x800040a0 0x00000020>;
 216                         reg-names = "csr", "descriptor_slave";
 217                         interrupts = <14>;
 218                         interrupt-parent = <&beripic0>;
 219                         #dma-cells = <3>;
 220                 };
 221
 222                 msgdma1: msgdma@80004000 {
 223                         compatible = "altr,msgdma-16.0", "altr,msgdma-1.0";
 224                         reg = <0x80004000 0x00000020>,
 225                               <0x80004020 0x00000020>;
 226                         reg-names = "csr", "descriptor_slave";
 227                         interrupts = <13>;
 228                         interrupt-parent = <&beripic0>;
 229                         #dma-cells = <3>;
 230                 };
 231
 232                 softdma0: softdma@7f007400 {
 233                         compatible = "altr,softdma";
 234                         reg = < 0x7f007400 0x8          /* tx */
 235                                 0x7f007420 0x20 >;      /* txc */
 236                         interrupts = <2>;
 237                         interrupt-parent = <&beripic0>;
 238                         #dma-cells = <3>;
 239                 };
 240
 241                 softdma1: softdma@7f007500 {
 242                         compatible = "altr,softdma";
 243                         reg = < 0x7f007500 0x8          /* rx */
 244                                 0x7f007520 0x20 >;      /* rxc */
 245                         interrupts = <1>;
 246                         interrupt-parent = <&beripic0>;
 247                         #dma-cells = <3>;
 248                 };
 249
 250                 softdma2: softdma@7f005400 {
 251                         compatible = "altr,softdma";
 252                         reg = < 0x7f005400 0x8          /* tx */
 253                                 0x7f005420 0x20 >;      /* txc */
 254                         interrupts = <12>;
 255                         interrupt-parent = <&beripic0>;
 256                         #dma-cells = <3>;
 257                 };
 258
 259                 softdma3: softdma@7f005500 {
 260                         compatible = "altr,softdma";
 261                         reg = < 0x7f005500 0x8          /* rx */
 262                                 0x7f005520 0x20 >;      /* rxc */
 263                         interrupts = <11>;
 264                         interrupt-parent = <&beripic0>;
 265                         #dma-cells = <3>;
 266                 };
 267
 268                 ethernet@80007000 {
 269                         compatible = "altera,atse";
 270                         reg = <0x80007000 0x400>;               /* mac */
 271                         dmas = <&msgdma0 0 0 0xffffffff>,
 272                                <&msgdma1 1 1 0xffffffff>;
 273                         dma-names = "tx", "rx";
 274                         status = "disabled";
 275                 };
 276
 277                 ethernet@7f007000 {
 278                         compatible = "altera,atse";
 279                         reg = <0x7f007000 0x400>;               /* mac */
 280                         dmas = <&softdma0 0 0 0xffffffff>,
 281                                <&softdma1 1 1 0xffffffff>;
 282                         dma-names = "tx", "rx";
 283                         status = "okay";
 284                 };
 285
 286                 ethernet@7f005000 {
 287                         compatible = "altera,atse";
 288                         reg = <0x7f005000 0x400>;
 289                         dmas = <&softdma2 0 0 0xffffffff>,
 290                                <&softdma3 1 1 0xffffffff>;
 291                         dma-names = "tx", "rx";
 292                         status = "disabled";
 293                 };
 294
 295                 touchscreen@70400000 {
 296                         compatible = "sri-cambridge,mtl";
 297                         panel-size = < 800 480 >;
 298                         reg = <0x70400000 0x1000
 299                                0x70000000 0x177000
 300                                0x70177000 0x2000>;
 301                 };
 302
 303                 usb@0x7f100000 {
 304                         compatible = "nxp,usb-isp1761";
 305                         reg = <0x7f100000 0x40000
 306                                0x7f140000 0x4>;
 307                         // IRQ 4 is DC, IRQ 5 is HC.
 308                         interrupts = <4 5>;
 309                         interrupt-parent = <&beripic0>;
 310                 };
 311
 312                 avgen@0x7f009000 {
 313                         compatible = "sri-cambridge,avgen";
 314                         reg = <0x7f009000 0x2>;
 315                         sri-cambridge,width = <1>;
 316                         sri-cambridge,fileio = "r";
 317                         sri-cambridge,devname = "de4bsw";
 318                 };
 319
 320                 avgen@0x7f00a000 {
 321                         compatible = "sri-cambridge,avgen";
 322                         reg = <0x7f00a000 0x14>;
 323                         sri-cambridge,width = <4>;
 324                         sri-cambridge,fileio = "rw";
 325                         sri-cambridge,devname = "berirom";
 326                 };
 327
 328                 avgen@0x7f00c000 {
 329                         compatible = "sri-cambridge,avgen";
 330                         reg = <0x7f00c000 0x8>;
 331                         sri-cambridge,width = <4>;
 332                         sri-cambridge,fileio = "rw";
 333                         sri-cambridge,devname = "de4tempfan";
 334                 };
 335         };
 336 };