2 * MPC8572 DS Device Tree Source
4 * Copyright 2007-2009 Freescale Semiconductor Inc. All rights reserved
6 * Neither the name of Freescale Semiconductor, Inc nor the names of
7 * its contributors may be used to endorse or promote products derived
8 * from this software without specific prior written permission.
10 * Freescale hereby publishes it under the following licenses:
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
18 * Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
21 * Redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in
23 * the documentation and/or other materials provided with the
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
27 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
29 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
30 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
32 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
33 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
35 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGE.
40 * GNU General Public License, version 2
42 * This program is free software; you can redistribute it and/or
43 * modify it under the terms of the GNU General Public License
44 * as published by the Free Software Foundation; either version 2
45 * of the License, or (at your option) any later version.
47 * This program is distributed in the hope that it will be useful,
48 * but WITHOUT ANY WARRANTY; without even the implied warranty of
49 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
50 * GNU General Public License for more details.
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53 * along with this program; if not, write to the Free Software
54 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
57 * You may select the license of your choice.
58 *------------------------------------------------------------------
65 model = "fsl,MPC8572DS";
66 compatible = "fsl,MPC8572DS";
89 d-cache-line-size = <32>; // 32 bytes
90 i-cache-line-size = <32>; // 32 bytes
91 d-cache-size = <0x8000>; // L1, 32K
92 i-cache-size = <0x8000>; // L1, 32K
93 timebase-frequency = <0>;
95 clock-frequency = <0>;
96 next-level-cache = <&L2>;
102 d-cache-line-size = <32>; // 32 bytes
103 i-cache-line-size = <32>; // 32 bytes
104 d-cache-size = <0x8000>; // L1, 32K
105 i-cache-size = <0x8000>; // L1, 32K
106 timebase-frequency = <0>;
108 clock-frequency = <0>;
109 next-level-cache = <&L2>;
114 device_type = "memory";
118 #address-cells = <2>;
120 compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
121 reg = <0 0xffe05000 0 0x1000>;
123 interrupt-parent = <&mpic>;
125 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000>;
128 #address-cells = <1>;
130 compatible = "cfi-flash";
131 reg = <0x0 0x0 0x8000000>;
136 reg = <0x0 0x03000000>;
137 label = "ramdisk-nor";
142 reg = <0x03000000 0x00e00000>;
143 label = "diagnostic-nor";
148 reg = <0x03e00000 0x00200000>;
154 reg = <0x04000000 0x00400000>;
155 label = "kernel-nor";
160 reg = <0x04400000 0x03b00000>;
165 reg = <0x07f00000 0x00080000>;
171 reg = <0x07f80000 0x00080000>;
172 label = "u-boot-nor";
178 #address-cells = <1>;
180 compatible = "fsl,mpc8572-fcm-nand",
182 reg = <0x2 0x0 0x40000>;
185 reg = <0x0 0x02000000>;
186 label = "u-boot-nand";
191 reg = <0x02000000 0x10000000>;
192 label = "jffs2-nand";
196 reg = <0x12000000 0x08000000>;
197 label = "ramdisk-nand";
202 reg = <0x1a000000 0x04000000>;
203 label = "kernel-nand";
207 reg = <0x1e000000 0x01000000>;
213 reg = <0x1f000000 0x21000000>;
214 label = "reserved-nand";
219 compatible = "fsl,mpc8572-fcm-nand",
221 reg = <0x4 0x0 0x40000>;
225 compatible = "fsl,mpc8572-fcm-nand",
227 reg = <0x5 0x0 0x40000>;
231 compatible = "fsl,mpc8572-fcm-nand",
233 reg = <0x6 0x0 0x40000>;
238 #address-cells = <1>;
241 compatible = "simple-bus";
242 ranges = <0x0 0 0xffe00000 0x100000>;
243 bus-frequency = <0>; // Filled out by uboot.
246 compatible = "fsl,ecm-law";
252 compatible = "fsl,mpc8572-ecm", "fsl,ecm";
253 reg = <0x1000 0x1000>;
255 interrupt-parent = <&mpic>;
258 memory-controller@2000 {
259 compatible = "fsl,mpc8572-memory-controller";
260 reg = <0x2000 0x1000>;
261 interrupt-parent = <&mpic>;
265 memory-controller@6000 {
266 compatible = "fsl,mpc8572-memory-controller";
267 reg = <0x6000 0x1000>;
268 interrupt-parent = <&mpic>;
272 L2: l2-cache-controller@20000 {
273 compatible = "fsl,mpc8572-l2-cache-controller";
274 reg = <0x20000 0x1000>;
275 cache-line-size = <32>; // 32 bytes
276 cache-size = <0x100000>; // L2, 1M
277 interrupt-parent = <&mpic>;
282 #address-cells = <1>;
285 compatible = "fsl-i2c";
286 reg = <0x3000 0x100>;
288 interrupt-parent = <&mpic>;
293 #address-cells = <1>;
296 compatible = "fsl-i2c";
297 reg = <0x3100 0x100>;
299 interrupt-parent = <&mpic>;
304 #address-cells = <1>;
306 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
308 ranges = <0x0 0xc100 0x200>;
311 compatible = "fsl,mpc8572-dma-channel",
312 "fsl,eloplus-dma-channel";
315 interrupt-parent = <&mpic>;
319 compatible = "fsl,mpc8572-dma-channel",
320 "fsl,eloplus-dma-channel";
323 interrupt-parent = <&mpic>;
327 compatible = "fsl,mpc8572-dma-channel",
328 "fsl,eloplus-dma-channel";
331 interrupt-parent = <&mpic>;
335 compatible = "fsl,mpc8572-dma-channel",
336 "fsl,eloplus-dma-channel";
339 interrupt-parent = <&mpic>;
345 #address-cells = <1>;
347 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
349 ranges = <0x0 0x21100 0x200>;
352 compatible = "fsl,mpc8572-dma-channel",
353 "fsl,eloplus-dma-channel";
356 interrupt-parent = <&mpic>;
360 compatible = "fsl,mpc8572-dma-channel",
361 "fsl,eloplus-dma-channel";
364 interrupt-parent = <&mpic>;
368 compatible = "fsl,mpc8572-dma-channel",
369 "fsl,eloplus-dma-channel";
372 interrupt-parent = <&mpic>;
376 compatible = "fsl,mpc8572-dma-channel",
377 "fsl,eloplus-dma-channel";
380 interrupt-parent = <&mpic>;
385 ptp_timer: ptimer@24e00 {
386 compatible = "fsl,gianfar-ptp-timer";
387 reg = <0x24e00 0xb0>;
390 enet0: ethernet@24000 {
391 #address-cells = <1>;
394 device_type = "network";
396 compatible = "gianfar";
397 reg = <0x24000 0x1000>;
398 ranges = <0x0 0x24000 0x1000>;
399 local-mac-address = [ 00 00 00 00 00 00 ];
400 interrupts = <29 2 30 2 34 2>;
401 interrupt-parent = <&mpic>;
402 tbi-handle = <&tbi0>;
403 phy-handle = <&phy0>;
404 ptimer-handle = < &ptp_timer >;
405 phy-connection-type = "rgmii-id";
408 #address-cells = <1>;
410 compatible = "fsl,gianfar-mdio";
413 phy0: ethernet-phy@0 {
414 interrupt-parent = <&mpic>;
418 phy1: ethernet-phy@1 {
419 interrupt-parent = <&mpic>;
423 phy2: ethernet-phy@2 {
424 interrupt-parent = <&mpic>;
428 phy3: ethernet-phy@3 {
429 interrupt-parent = <&mpic>;
436 device_type = "tbi-phy";
441 enet1: ethernet@25000 {
442 #address-cells = <1>;
445 device_type = "network";
447 compatible = "gianfar";
448 reg = <0x25000 0x1000>;
449 ranges = <0x0 0x25000 0x1000>;
450 local-mac-address = [ 00 00 00 00 00 00 ];
451 interrupts = <35 2 36 2 40 2>;
452 interrupt-parent = <&mpic>;
453 tbi-handle = <&tbi1>;
454 phy-handle = <&phy1>;
455 ptimer-handle = < &ptp_timer >;
456 phy-connection-type = "rgmii-id";
459 #address-cells = <1>;
461 compatible = "fsl,gianfar-tbi";
466 device_type = "tbi-phy";
471 enet2: ethernet@26000 {
472 #address-cells = <1>;
475 device_type = "network";
477 compatible = "gianfar";
478 reg = <0x26000 0x1000>;
479 ranges = <0x0 0x26000 0x1000>;
480 local-mac-address = [ 00 00 00 00 00 00 ];
481 interrupts = <31 2 32 2 33 2>;
482 interrupt-parent = <&mpic>;
483 tbi-handle = <&tbi2>;
484 phy-handle = <&phy2>;
485 ptimer-handle = < &ptp_timer >;
486 phy-connection-type = "rgmii-id";
489 #address-cells = <1>;
491 compatible = "fsl,gianfar-tbi";
496 device_type = "tbi-phy";
501 enet3: ethernet@27000 {
502 #address-cells = <1>;
505 device_type = "network";
507 compatible = "gianfar";
508 reg = <0x27000 0x1000>;
509 ranges = <0x0 0x27000 0x1000>;
510 local-mac-address = [ 00 00 00 00 00 00 ];
511 interrupts = <37 2 38 2 39 2>;
512 interrupt-parent = <&mpic>;
513 tbi-handle = <&tbi3>;
514 phy-handle = <&phy3>;
515 phy-connection-type = "rgmii-id";
518 #address-cells = <1>;
520 compatible = "fsl,gianfar-tbi";
525 device_type = "tbi-phy";
530 serial0: serial@4500 {
532 device_type = "serial";
533 compatible = "ns16550";
534 reg = <0x4500 0x100>;
535 clock-frequency = <0>;
537 interrupt-parent = <&mpic>;
540 serial1: serial@4600 {
542 device_type = "serial";
543 compatible = "ns16550";
544 reg = <0x4600 0x100>;
545 clock-frequency = <0>;
547 interrupt-parent = <&mpic>;
550 global-utilities@e0000 { //global utilities block
551 compatible = "fsl,mpc8572-guts";
552 reg = <0xe0000 0x1000>;
557 compatible = "fsl,mpc8548-pmc";
558 reg = <0xe0070 0x14>;
562 compatible = "fsl,mpic-global-timer";
563 reg = <0x41100 0x204>;
564 interrupts = <0xf7 0x2>;
565 interrupt-parent = <&mpic>;
569 compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
570 reg = <0x41600 0x80>;
571 msi-available-ranges = <0 0x100>;
581 interrupt-parent = <&mpic>;
585 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
586 "fsl,sec2.1", "fsl,sec2.0";
587 reg = <0x30000 0x10000>;
588 interrupts = <45 2 58 2>;
589 interrupt-parent = <&mpic>;
590 fsl,num-channels = <4>;
591 fsl,channel-fifo-len = <24>;
592 fsl,exec-units-mask = <0x9fe>;
593 fsl,descriptor-types-mask = <0x3ab0ebf>;
596 /* PME (pattern-matcher) */
599 compatible = "pme8572";
600 reg = <0x10000 0x5000>;
601 interrupts = <0x39 0x2 0x40 0x2 0x41 0x2 0x42 0x2 0x43 0x2>;
602 interrupt-parent = <&mpic>;
606 interrupt-controller;
607 #address-cells = <0>;
608 #interrupt-cells = <2>;
609 reg = <0x40000 0x40000>;
610 compatible = "chrp,open-pic";
611 device_type = "open-pic";
615 pci0: pcie@ffe08000 {
616 compatible = "fsl,mpc8548-pcie";
618 #interrupt-cells = <1>;
620 #address-cells = <3>;
621 reg = <0 0xffe08000 0 0x1000>;
623 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x10000000
624 0x1000000 0x0 0x00000000 0 0xfee20000 0x0 0x00010000>;
625 clock-frequency = <33333333>;
626 interrupt-parent = <&mpic>;
628 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
630 /* IDSEL 0x11 func 0 - PCI slot 1 */
631 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
632 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
633 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
634 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
636 /* IDSEL 0x11 func 1 - PCI slot 1 */
637 0x8900 0x0 0x0 0x1 &mpic 0x2 0x1
638 0x8900 0x0 0x0 0x2 &mpic 0x3 0x1
639 0x8900 0x0 0x0 0x3 &mpic 0x4 0x1
640 0x8900 0x0 0x0 0x4 &mpic 0x1 0x1
642 /* IDSEL 0x11 func 2 - PCI slot 1 */
643 0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1
644 0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1
645 0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1
646 0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1
648 /* IDSEL 0x11 func 3 - PCI slot 1 */
649 0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1
650 0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1
651 0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1
652 0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1
654 /* IDSEL 0x11 func 4 - PCI slot 1 */
655 0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1
656 0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1
657 0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1
658 0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1
660 /* IDSEL 0x11 func 5 - PCI slot 1 */
661 0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1
662 0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1
663 0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1
664 0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1
666 /* IDSEL 0x11 func 6 - PCI slot 1 */
667 0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1
668 0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1
669 0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1
670 0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1
672 /* IDSEL 0x11 func 7 - PCI slot 1 */
673 0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1
674 0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1
675 0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1
676 0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1
678 /* IDSEL 0x12 func 0 - PCI slot 2 */
679 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
680 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
681 0x9000 0x0 0x0 0x3 &mpic 0x1 0x1
682 0x9000 0x0 0x0 0x4 &mpic 0x2 0x1
684 /* IDSEL 0x12 func 1 - PCI slot 2 */
685 0x9100 0x0 0x0 0x1 &mpic 0x3 0x1
686 0x9100 0x0 0x0 0x2 &mpic 0x4 0x1
687 0x9100 0x0 0x0 0x3 &mpic 0x1 0x1
688 0x9100 0x0 0x0 0x4 &mpic 0x2 0x1
690 /* IDSEL 0x12 func 2 - PCI slot 2 */
691 0x9200 0x0 0x0 0x1 &mpic 0x3 0x1
692 0x9200 0x0 0x0 0x2 &mpic 0x4 0x1
693 0x9200 0x0 0x0 0x3 &mpic 0x1 0x1
694 0x9200 0x0 0x0 0x4 &mpic 0x2 0x1
696 /* IDSEL 0x12 func 3 - PCI slot 2 */
697 0x9300 0x0 0x0 0x1 &mpic 0x3 0x1
698 0x9300 0x0 0x0 0x2 &mpic 0x4 0x1
699 0x9300 0x0 0x0 0x3 &mpic 0x1 0x1
700 0x9300 0x0 0x0 0x4 &mpic 0x2 0x1
702 /* IDSEL 0x12 func 4 - PCI slot 2 */
703 0x9400 0x0 0x0 0x1 &mpic 0x3 0x1
704 0x9400 0x0 0x0 0x2 &mpic 0x4 0x1
705 0x9400 0x0 0x0 0x3 &mpic 0x1 0x1
706 0x9400 0x0 0x0 0x4 &mpic 0x2 0x1
708 /* IDSEL 0x12 func 5 - PCI slot 2 */
709 0x9500 0x0 0x0 0x1 &mpic 0x3 0x1
710 0x9500 0x0 0x0 0x2 &mpic 0x4 0x1
711 0x9500 0x0 0x0 0x3 &mpic 0x1 0x1
712 0x9500 0x0 0x0 0x4 &mpic 0x2 0x1
714 /* IDSEL 0x12 func 6 - PCI slot 2 */
715 0x9600 0x0 0x0 0x1 &mpic 0x3 0x1
716 0x9600 0x0 0x0 0x2 &mpic 0x4 0x1
717 0x9600 0x0 0x0 0x3 &mpic 0x1 0x1
718 0x9600 0x0 0x0 0x4 &mpic 0x2 0x1
720 /* IDSEL 0x12 func 7 - PCI slot 2 */
721 0x9700 0x0 0x0 0x1 &mpic 0x3 0x1
722 0x9700 0x0 0x0 0x2 &mpic 0x4 0x1
723 0x9700 0x0 0x0 0x3 &mpic 0x1 0x1
724 0x9700 0x0 0x0 0x4 &mpic 0x2 0x1
727 0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
728 0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
729 0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
730 0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
733 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
736 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
737 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
739 // IDSEL 0x1f IDE/SATA
740 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
741 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
746 reg = <0x0 0x0 0x0 0x0 0x0>;
748 #address-cells = <3>;
750 ranges = <0x2000000 0x0 0xa0000000
751 0x2000000 0x0 0xa0000000
758 reg = <0x0 0x0 0x0 0x0 0x0>;
760 #address-cells = <3>;
761 ranges = <0x2000000 0x0 0xa0000000
762 0x2000000 0x0 0xa0000000
770 #interrupt-cells = <2>;
772 #address-cells = <2>;
773 reg = <0xf000 0x0 0x0 0x0 0x0>;
774 ranges = <0x1 0x0 0x1000000 0x0 0x0
776 interrupt-parent = <&i8259>;
778 i8259: interrupt-controller@20 {
782 interrupt-controller;
783 device_type = "interrupt-controller";
784 #address-cells = <0>;
785 #interrupt-cells = <2>;
786 compatible = "chrp,iic";
788 interrupt-parent = <&mpic>;
793 #address-cells = <1>;
794 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
795 interrupts = <1 3 12 3>;
801 compatible = "pnpPNP,303";
806 compatible = "pnpPNP,f03";
811 compatible = "pnpPNP,b00";
812 reg = <0x1 0x70 0x2>;
816 reg = <0x1 0x400 0x80>;
824 pci1: pcie@ffe09000 {
825 compatible = "fsl,mpc8548-pcie";
827 #interrupt-cells = <1>;
829 #address-cells = <3>;
830 reg = <0 0xffe09000 0 0x1000>;
832 ranges = <0x2000000 0x0 0x90000000 0 0x90000000 0x0 0x10000000
833 0x1000000 0x0 0x00000000 0 0xfee10000 0x0 0x00010000>;
834 clock-frequency = <33333333>;
835 interrupt-parent = <&mpic>;
837 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
840 0000 0x0 0x0 0x1 &mpic 0x4 0x1
841 0000 0x0 0x0 0x2 &mpic 0x5 0x1
842 0000 0x0 0x0 0x3 &mpic 0x6 0x1
843 0000 0x0 0x0 0x4 &mpic 0x7 0x1
846 reg = <0x0 0x0 0x0 0x0 0x0>;
848 #address-cells = <3>;
850 ranges = <0x2000000 0x0 0x90000000
851 0x2000000 0x0 0x90000000
860 pci2: pcie@ffe0a000 {
861 compatible = "fsl,mpc8548-pcie";
863 #interrupt-cells = <1>;
865 #address-cells = <3>;
866 reg = <0 0xffe0a000 0 0x1000>;
868 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x10000000
869 0x1000000 0x0 0x00000000 0 0xfee00000 0x0 0x00010000>;
870 clock-frequency = <33333333>;
871 interrupt-parent = <&mpic>;
873 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
876 0000 0x0 0x0 0x1 &mpic 0x0 0x1
877 0000 0x0 0x0 0x2 &mpic 0x1 0x1
878 0000 0x0 0x0 0x3 &mpic 0x2 0x1
879 0000 0x0 0x0 0x4 &mpic 0x3 0x1
882 reg = <0x0 0x0 0x0 0x0 0x0>;
884 #address-cells = <3>;
886 ranges = <0x2000000 0x0 0x80000000
887 0x2000000 0x0 0x80000000