2 * P1020 RDB Device Tree Source
4 * Copyright 2009 Freescale Semiconductor Inc.
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40 compatible = "fsl,P1020RDB";
61 next-level-cache = <&L2>;
67 next-level-cache = <&L2>;
72 device_type = "memory";
78 compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
79 reg = <0 0xffe05000 0 0x1000>;
81 interrupt-parent = <&mpic>;
83 /* NOR, NAND Flashes and Vitesse 5 port L2 switch */
84 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
85 0x1 0x0 0x0 0xffa00000 0x00040000
86 0x2 0x0 0x0 0xffb00000 0x00020000>;
91 compatible = "cfi-flash";
92 reg = <0x0 0x0 0x1000000>;
97 /* This location must not be altered */
98 /* 256KB for Vitesse 7385 Switch firmware */
99 reg = <0x0 0x00040000>;
100 label = "NOR (RO) Vitesse-7385 Firmware";
105 /* 256KB for DTB Image */
106 reg = <0x00040000 0x00040000>;
107 label = "NOR (RO) DTB Image";
112 /* 3.5 MB for Linux Kernel Image */
113 reg = <0x00080000 0x00380000>;
114 label = "NOR (RO) Linux Kernel Image";
119 /* 11MB for JFFS2 based Root file System */
120 reg = <0x00400000 0x00b00000>;
121 label = "NOR (RW) JFFS2 Root File System";
125 /* This location must not be altered */
126 /* 512KB for u-boot Bootloader Image */
127 /* 512KB for u-boot Environment Variables */
128 reg = <0x00f00000 0x00100000>;
129 label = "NOR (RO) U-Boot Image";
135 #address-cells = <1>;
137 compatible = "fsl,p1020-fcm-nand",
139 reg = <0x1 0x0 0x40000>;
142 /* This location must not be altered */
143 /* 1MB for u-boot Bootloader Image */
144 reg = <0x0 0x00100000>;
145 label = "NAND (RO) U-Boot Image";
150 /* 1MB for DTB Image */
151 reg = <0x00100000 0x00100000>;
152 label = "NAND (RO) DTB Image";
157 /* 4MB for Linux Kernel Image */
158 reg = <0x00200000 0x00400000>;
159 label = "NAND (RO) Linux Kernel Image";
164 /* 4MB for Compressed Root file System Image */
165 reg = <0x00600000 0x00400000>;
166 label = "NAND (RO) Compressed RFS Image";
171 /* 7MB for JFFS2 based Root file System */
172 reg = <0x00a00000 0x00700000>;
173 label = "NAND (RW) JFFS2 Root File System";
177 /* 15MB for JFFS2 based Root file System */
178 reg = <0x01100000 0x00f00000>;
179 label = "NAND (RW) Writable User area";
184 #address-cells = <1>;
186 compatible = "vitesse-7385";
187 reg = <0x2 0x0 0x20000>;
193 #address-cells = <1>;
196 compatible = "fsl,p1020-immr", "simple-bus";
197 ranges = <0x0 0x0 0xffe00000 0x100000>;
198 bus-frequency = <0>; // Filled out by uboot.
201 compatible = "fsl,ecm-law";
207 compatible = "fsl,p1020-ecm", "fsl,ecm";
208 reg = <0x1000 0x1000>;
210 interrupt-parent = <&mpic>;
213 memory-controller@2000 {
214 compatible = "fsl,p1020-memory-controller";
215 reg = <0x2000 0x1000>;
216 interrupt-parent = <&mpic>;
221 #address-cells = <1>;
224 compatible = "fsl-i2c";
225 reg = <0x3000 0x100>;
227 interrupt-parent = <&mpic>;
230 compatible = "dallas,ds1339";
236 #address-cells = <1>;
239 compatible = "fsl-i2c";
240 reg = <0x3100 0x100>;
242 interrupt-parent = <&mpic>;
246 serial0: serial@4500 {
248 device_type = "serial";
249 compatible = "ns16550";
250 reg = <0x4500 0x100>;
251 clock-frequency = <0>;
253 interrupt-parent = <&mpic>;
256 serial1: serial@4600 {
258 device_type = "serial";
259 compatible = "ns16550";
260 reg = <0x4600 0x100>;
261 clock-frequency = <0>;
263 interrupt-parent = <&mpic>;
268 #address-cells = <1>;
270 compatible = "fsl,espi";
271 reg = <0x7000 0x1000>;
272 interrupts = <59 0x2>;
273 interrupt-parent = <&mpic>;
277 #address-cells = <1>;
279 compatible = "fsl,espi-flash";
281 linux,modalias = "fsl_m25p80";
283 spi-max-frequency = <50000000>;
287 /* 512KB for u-boot Bootloader Image */
288 reg = <0x0 0x00080000>;
289 label = "SPI (RO) U-Boot Image";
294 /* 512KB for DTB Image */
295 reg = <0x00080000 0x00080000>;
296 label = "SPI (RO) DTB Image";
301 /* 4MB for Linux Kernel Image */
302 reg = <0x00100000 0x00400000>;
303 label = "SPI (RO) Linux Kernel Image";
308 /* 4MB for Compressed RFS Image */
309 reg = <0x00500000 0x00400000>;
310 label = "SPI (RO) Compressed RFS Image";
315 /* 7MB for JFFS2 based RFS */
316 reg = <0x00900000 0x00700000>;
317 label = "SPI (RW) JFFS2 RFS";
322 gpio: gpio-controller@f000 {
324 compatible = "fsl,mpc8572-gpio";
325 reg = <0xf000 0x100>;
326 interrupts = <47 0x2>;
327 interrupt-parent = <&mpic>;
331 L2: l2-cache-controller@20000 {
332 compatible = "fsl,p1020-l2-cache-controller";
333 reg = <0x20000 0x1000>;
334 cache-line-size = <32>; // 32 bytes
335 cache-size = <0x40000>; // L2,256K
336 interrupt-parent = <&mpic>;
341 #address-cells = <1>;
343 compatible = "fsl,eloplus-dma";
345 ranges = <0x0 0x21100 0x200>;
348 compatible = "fsl,eloplus-dma-channel";
351 interrupt-parent = <&mpic>;
355 compatible = "fsl,eloplus-dma-channel";
358 interrupt-parent = <&mpic>;
362 compatible = "fsl,eloplus-dma-channel";
365 interrupt-parent = <&mpic>;
369 compatible = "fsl,eloplus-dma-channel";
372 interrupt-parent = <&mpic>;
378 #address-cells = <1>;
380 compatible = "fsl,etsec2-mdio";
381 reg = <0x24000 0x1000 0xb0030 0x4>;
383 phy0: ethernet-phy@0 {
384 interrupt-parent = <&mpic>;
389 phy1: ethernet-phy@1 {
390 interrupt-parent = <&mpic>;
397 #address-cells = <1>;
399 compatible = "fsl,etsec2-tbi";
400 reg = <0x25000 0x1000 0xb1030 0x4>;
404 device_type = "tbi-phy";
408 enet0: ethernet@b0000 {
409 #address-cells = <1>;
411 device_type = "network";
413 compatible = "fsl,etsec2";
414 fsl,num_rx_queues = <0x8>;
415 fsl,num_tx_queues = <0x8>;
416 local-mac-address = [ 00 00 00 00 00 00 ];
417 interrupt-parent = <&mpic>;
418 fixed-link = <1 1 1000 0 0>;
419 phy-connection-type = "rgmii-id";
422 #address-cells = <1>;
424 reg = <0xb0000 0x1000>;
425 interrupts = <29 2 30 2 34 2>;
429 #address-cells = <1>;
431 reg = <0xb4000 0x1000>;
432 interrupts = <17 2 18 2 24 2>;
436 enet1: ethernet@b1000 {
437 #address-cells = <1>;
439 device_type = "network";
441 compatible = "fsl,etsec2";
442 fsl,num_rx_queues = <0x8>;
443 fsl,num_tx_queues = <0x8>;
444 local-mac-address = [ 00 00 00 00 00 00 ];
445 interrupt-parent = <&mpic>;
446 phy-handle = <&phy0>;
447 tbi-handle = <&tbi0>;
448 phy-connection-type = "sgmii";
451 #address-cells = <1>;
453 reg = <0xb1000 0x1000>;
454 interrupts = <35 2 36 2 40 2>;
458 #address-cells = <1>;
460 reg = <0xb5000 0x1000>;
461 interrupts = <51 2 52 2 67 2>;
465 enet2: ethernet@b2000 {
466 #address-cells = <1>;
468 device_type = "network";
470 compatible = "fsl,etsec2";
471 fsl,num_rx_queues = <0x8>;
472 fsl,num_tx_queues = <0x8>;
473 local-mac-address = [ 00 00 00 00 00 00 ];
474 interrupt-parent = <&mpic>;
475 phy-handle = <&phy1>;
476 phy-connection-type = "rgmii-id";
479 #address-cells = <1>;
481 reg = <0xb2000 0x1000>;
482 interrupts = <31 2 32 2 33 2>;
486 #address-cells = <1>;
488 reg = <0xb6000 0x1000>;
489 interrupts = <25 2 26 2 27 2>;
494 #address-cells = <1>;
496 compatible = "fsl-usb2-dr";
497 reg = <0x22000 0x1000>;
498 interrupt-parent = <&mpic>;
499 interrupts = <28 0x2>;
503 /* USB2 is shared with localbus, so it must be disabled
504 by default. We can't put 'status = "disabled";' here
505 since U-Boot doesn't clear the status property when
506 it enables USB2. OTOH, U-Boot does create a new node
507 when there isn't any. So, just comment it out.
509 #address-cells = <1>;
511 compatible = "fsl-usb2-dr";
512 reg = <0x23000 0x1000>;
513 interrupt-parent = <&mpic>;
514 interrupts = <46 0x2>;
520 compatible = "fsl,p1020-esdhc", "fsl,esdhc";
521 reg = <0x2e000 0x1000>;
522 interrupts = <72 0x2>;
523 interrupt-parent = <&mpic>;
524 /* Filled in by U-Boot */
525 clock-frequency = <0>;
529 compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
530 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
531 reg = <0x30000 0x10000>;
532 interrupts = <45 2 58 2>;
533 interrupt-parent = <&mpic>;
534 fsl,num-channels = <4>;
535 fsl,channel-fifo-len = <24>;
536 fsl,exec-units-mask = <0xbfe>;
537 fsl,descriptor-types-mask = <0x3ab0ebf>;
541 interrupt-controller;
542 #address-cells = <0>;
543 #interrupt-cells = <2>;
544 reg = <0x40000 0x40000>;
545 compatible = "chrp,open-pic";
546 device_type = "open-pic";
550 compatible = "fsl,p1020-msi", "fsl,mpic-msi";
551 reg = <0x41600 0x80>;
552 msi-available-ranges = <0 0x100>;
562 interrupt-parent = <&mpic>;
565 global-utilities@e0000 { //global utilities block
566 compatible = "fsl,p1020-guts";
567 reg = <0xe0000 0x1000>;
572 pci0: pcie@ffe09000 {
573 compatible = "fsl,mpc8548-pcie";
575 #interrupt-cells = <1>;
577 #address-cells = <3>;
578 reg = <0 0xffe09000 0 0x1000>;
580 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
581 0x1000000 0x0 0x00000000 0 0xffc30000 0x0 0x10000>;
582 clock-frequency = <33333333>;
583 interrupt-parent = <&mpic>;
586 reg = <0x0 0x0 0x0 0x0 0x0>;
588 #address-cells = <3>;
590 ranges = <0x2000000 0x0 0xa0000000
591 0x2000000 0x0 0xa0000000
600 pci1: pcie@ffe0a000 {
601 compatible = "fsl,mpc8548-pcie";
603 #interrupt-cells = <1>;
605 #address-cells = <3>;
606 reg = <0 0xffe0a000 0 0x1000>;
608 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
609 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
610 clock-frequency = <33333333>;
611 interrupt-parent = <&mpic>;
614 reg = <0x0 0x0 0x0 0x0 0x0>;
616 #address-cells = <3>;
618 ranges = <0x2000000 0x0 0xc0000000
619 0x2000000 0x0 0xc0000000