2 * P2020 DS Device Tree Source
4 * Copyright 2009 Freescale Semiconductor Inc.
6 * Neither the name of Freescale Semiconductor, Inc nor the names of
7 * its contributors may be used to endorse or promote products derived
8 * from this software without specific prior written permission.
10 * Freescale hereby publishes it under the following licenses:
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15 * without modification, are permitted provided that the following
18 * Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
21 * Redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in
23 * the documentation and/or other materials provided with the
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
27 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
29 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
30 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
32 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
33 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
35 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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40 * GNU General Public License, version 2
42 * This program is free software; you can redistribute it and/or
43 * modify it under the terms of the GNU General Public License
44 * as published by the Free Software Foundation; either version 2
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47 * This program is distributed in the hope that it will be useful,
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57 * You may select the license of your choice.
58 *------------------------------------------------------------------
65 compatible = "fsl,P2020DS";
87 next-level-cache = <&L2>;
93 next-level-cache = <&L2>;
98 device_type = "memory";
102 #address-cells = <2>;
104 compatible = "fsl,elbc", "simple-bus";
105 reg = <0 0xffe05000 0 0x1000>;
107 interrupt-parent = <&mpic>;
109 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
110 0x1 0x0 0x0 0xe0000000 0x08000000
111 0x2 0x0 0x0 0xffa00000 0x00040000
112 0x3 0x0 0x0 0xffdf0000 0x00008000
113 0x4 0x0 0x0 0xffa40000 0x00040000
114 0x5 0x0 0x0 0xffa80000 0x00040000
115 0x6 0x0 0x0 0xffac0000 0x00040000>;
118 #address-cells = <1>;
120 compatible = "cfi-flash";
121 reg = <0x0 0x0 0x8000000>;
126 reg = <0x0 0x03000000>;
131 reg = <0x03000000 0x00e00000>;
136 reg = <0x03e00000 0x00200000>;
141 reg = <0x04000000 0x00400000>;
146 reg = <0x04400000 0x03b00000>;
150 reg = <0x07f00000 0x00080000>;
155 reg = <0x07f80000 0x00080000>;
161 #address-cells = <1>;
163 compatible = "fsl,elbc-fcm-nand";
164 reg = <0x2 0x0 0x40000>;
167 reg = <0x0 0x02000000>;
172 reg = <0x02000000 0x10000000>;
176 reg = <0x12000000 0x08000000>;
181 reg = <0x1a000000 0x04000000>;
185 reg = <0x1e000000 0x01000000>;
190 reg = <0x1f000000 0x21000000>;
195 compatible = "fsl,elbc-fcm-nand";
196 reg = <0x4 0x0 0x40000>;
200 compatible = "fsl,elbc-fcm-nand";
201 reg = <0x5 0x0 0x40000>;
205 compatible = "fsl,elbc-fcm-nand";
206 reg = <0x6 0x0 0x40000>;
211 #address-cells = <1>;
214 compatible = "fsl,p2020-immr", "simple-bus";
215 ranges = <0x0 0 0xffe00000 0x100000>;
216 bus-frequency = <0>; // Filled out by uboot.
219 compatible = "fsl,ecm-law";
225 compatible = "fsl,p2020-ecm", "fsl,ecm";
226 reg = <0x1000 0x1000>;
228 interrupt-parent = <&mpic>;
231 memory-controller@2000 {
232 compatible = "fsl,p2020-memory-controller";
233 reg = <0x2000 0x1000>;
234 interrupt-parent = <&mpic>;
239 #address-cells = <1>;
242 compatible = "fsl-i2c";
243 reg = <0x3000 0x100>;
245 interrupt-parent = <&mpic>;
250 #address-cells = <1>;
253 compatible = "fsl-i2c";
254 reg = <0x3100 0x100>;
256 interrupt-parent = <&mpic>;
260 serial0: serial@4500 {
262 device_type = "serial";
263 compatible = "ns16550";
264 reg = <0x4500 0x100>;
265 clock-frequency = <0>;
267 interrupt-parent = <&mpic>;
270 serial1: serial@4600 {
272 device_type = "serial";
273 compatible = "ns16550";
274 reg = <0x4600 0x100>;
275 clock-frequency = <0>;
277 interrupt-parent = <&mpic>;
281 compatible = "fsl,espi";
282 reg = <0x7000 0x1000>;
283 interrupts = <59 0x2>;
284 interrupt-parent = <&mpic>;
288 #address-cells = <1>;
290 compatible = "fsl,eloplus-dma";
292 ranges = <0x0 0xc100 0x200>;
295 compatible = "fsl,eloplus-dma-channel";
298 interrupt-parent = <&mpic>;
302 compatible = "fsl,eloplus-dma-channel";
305 interrupt-parent = <&mpic>;
309 compatible = "fsl,eloplus-dma-channel";
312 interrupt-parent = <&mpic>;
316 compatible = "fsl,eloplus-dma-channel";
319 interrupt-parent = <&mpic>;
324 gpio: gpio-controller@f000 {
326 compatible = "fsl,mpc8572-gpio";
327 reg = <0xf000 0x100>;
328 interrupts = <47 0x2>;
329 interrupt-parent = <&mpic>;
333 L2: l2-cache-controller@20000 {
334 compatible = "fsl,p2020-l2-cache-controller";
335 reg = <0x20000 0x1000>;
336 cache-line-size = <32>; // 32 bytes
337 cache-size = <0x80000>; // L2, 512k
338 interrupt-parent = <&mpic>;
343 #address-cells = <1>;
345 compatible = "fsl,eloplus-dma";
347 ranges = <0x0 0x21100 0x200>;
350 compatible = "fsl,eloplus-dma-channel";
353 interrupt-parent = <&mpic>;
357 compatible = "fsl,eloplus-dma-channel";
360 interrupt-parent = <&mpic>;
364 compatible = "fsl,eloplus-dma-channel";
367 interrupt-parent = <&mpic>;
371 compatible = "fsl,eloplus-dma-channel";
374 interrupt-parent = <&mpic>;
380 #address-cells = <1>;
382 compatible = "fsl-usb2-dr";
383 reg = <0x22000 0x1000>;
384 interrupt-parent = <&mpic>;
385 interrupts = <28 0x2>;
389 enet0: ethernet@24000 {
390 #address-cells = <1>;
393 device_type = "network";
395 compatible = "gianfar";
396 reg = <0x24000 0x1000>;
397 ranges = <0x0 0x24000 0x1000>;
398 local-mac-address = [ 00 00 00 00 00 00 ];
399 interrupts = <29 2 30 2 34 2>;
400 interrupt-parent = <&mpic>;
401 tbi-handle = <&tbi0>;
402 phy-handle = <&phy0>;
403 phy-connection-type = "rgmii-id";
406 #address-cells = <1>;
408 compatible = "fsl,gianfar-mdio";
411 phy0: ethernet-phy@0 {
412 interrupt-parent = <&mpic>;
416 phy1: ethernet-phy@1 {
417 interrupt-parent = <&mpic>;
421 phy2: ethernet-phy@2 {
422 interrupt-parent = <&mpic>;
428 device_type = "tbi-phy";
433 enet1: ethernet@25000 {
434 #address-cells = <1>;
437 device_type = "network";
439 compatible = "gianfar";
440 reg = <0x25000 0x1000>;
441 ranges = <0x0 0x25000 0x1000>;
442 local-mac-address = [ 00 00 00 00 00 00 ];
443 interrupts = <35 2 36 2 40 2>;
444 interrupt-parent = <&mpic>;
445 tbi-handle = <&tbi1>;
446 phy-handle = <&phy1>;
447 phy-connection-type = "rgmii-id";
450 #address-cells = <1>;
452 compatible = "fsl,gianfar-tbi";
457 device_type = "tbi-phy";
462 enet2: ethernet@26000 {
463 #address-cells = <1>;
466 device_type = "network";
468 compatible = "gianfar";
469 reg = <0x26000 0x1000>;
470 ranges = <0x0 0x26000 0x1000>;
471 local-mac-address = [ 00 00 00 00 00 00 ];
472 interrupts = <31 2 32 2 33 2>;
473 interrupt-parent = <&mpic>;
474 tbi-handle = <&tbi2>;
475 phy-handle = <&phy2>;
476 phy-connection-type = "rgmii-id";
479 #address-cells = <1>;
481 compatible = "fsl,gianfar-tbi";
486 device_type = "tbi-phy";
492 compatible = "fsl,p2020-esdhc", "fsl,esdhc";
493 reg = <0x2e000 0x1000>;
494 interrupts = <72 0x2>;
495 interrupt-parent = <&mpic>;
496 /* Filled in by U-Boot */
497 clock-frequency = <0>;
501 compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
502 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
503 reg = <0x30000 0x10000>;
504 interrupts = <45 2 58 2>;
505 interrupt-parent = <&mpic>;
506 fsl,num-channels = <4>;
507 fsl,channel-fifo-len = <24>;
508 fsl,exec-units-mask = <0xbfe>;
509 fsl,descriptor-types-mask = <0x3ab0ebf>;
513 interrupt-controller;
514 #address-cells = <0>;
515 #interrupt-cells = <2>;
516 reg = <0x40000 0x40000>;
517 compatible = "chrp,open-pic";
518 device_type = "open-pic";
522 compatible = "fsl,mpic-msi";
523 reg = <0x41600 0x80>;
524 msi-available-ranges = <0 0x100>;
534 interrupt-parent = <&mpic>;
537 global-utilities@e0000 { //global utilities block
538 compatible = "fsl,p2020-guts";
539 reg = <0xe0000 0x1000>;
544 pci0: pcie@ffe08000 {
545 compatible = "fsl,mpc8548-pcie";
547 #interrupt-cells = <1>;
549 #address-cells = <3>;
550 reg = <0 0xffe08000 0 0x1000>;
552 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
553 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
554 clock-frequency = <33333333>;
555 interrupt-parent = <&mpic>;
557 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
560 0000 0x0 0x0 0x1 &mpic 0x8 0x1
561 0000 0x0 0x0 0x2 &mpic 0x9 0x1
562 0000 0x0 0x0 0x3 &mpic 0xa 0x1
563 0000 0x0 0x0 0x4 &mpic 0xb 0x1
566 reg = <0x0 0x0 0x0 0x0 0x0>;
568 #address-cells = <3>;
570 ranges = <0x2000000 0x0 0x80000000
571 0x2000000 0x0 0x80000000
580 pci1: pcie@ffe09000 {
581 compatible = "fsl,mpc8548-pcie";
583 #interrupt-cells = <1>;
585 #address-cells = <3>;
586 reg = <0 0xffe09000 0 0x1000>;
588 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
589 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
590 clock-frequency = <33333333>;
591 interrupt-parent = <&mpic>;
593 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
596 // IDSEL 0x11 func 0 - PCI slot 1
597 0x8800 0x0 0x0 0x1 &i8259 0x9 0x2
598 0x8800 0x0 0x0 0x2 &i8259 0xa 0x2
600 // IDSEL 0x11 func 1 - PCI slot 1
601 0x8900 0x0 0x0 0x1 &i8259 0x9 0x2
602 0x8900 0x0 0x0 0x2 &i8259 0xa 0x2
604 // IDSEL 0x11 func 2 - PCI slot 1
605 0x8a00 0x0 0x0 0x1 &i8259 0x9 0x2
606 0x8a00 0x0 0x0 0x2 &i8259 0xa 0x2
608 // IDSEL 0x11 func 3 - PCI slot 1
609 0x8b00 0x0 0x0 0x1 &i8259 0x9 0x2
610 0x8b00 0x0 0x0 0x2 &i8259 0xa 0x2
612 // IDSEL 0x11 func 4 - PCI slot 1
613 0x8c00 0x0 0x0 0x1 &i8259 0x9 0x2
614 0x8c00 0x0 0x0 0x2 &i8259 0xa 0x2
616 // IDSEL 0x11 func 5 - PCI slot 1
617 0x8d00 0x0 0x0 0x1 &i8259 0x9 0x2
618 0x8d00 0x0 0x0 0x2 &i8259 0xa 0x2
620 // IDSEL 0x11 func 6 - PCI slot 1
621 0x8e00 0x0 0x0 0x1 &i8259 0x9 0x2
622 0x8e00 0x0 0x0 0x2 &i8259 0xa 0x2
624 // IDSEL 0x11 func 7 - PCI slot 1
625 0x8f00 0x0 0x0 0x1 &i8259 0x9 0x2
626 0x8f00 0x0 0x0 0x2 &i8259 0xa 0x2
629 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
632 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
633 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
635 // IDSEL 0x1f IDE/SATA
636 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
637 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
641 reg = <0x0 0x0 0x0 0x0 0x0>;
643 #address-cells = <3>;
645 ranges = <0x2000000 0x0 0xa0000000
646 0x2000000 0x0 0xa0000000
653 reg = <0x0 0x0 0x0 0x0 0x0>;
655 #address-cells = <3>;
656 ranges = <0x2000000 0x0 0xa0000000
657 0x2000000 0x0 0xa0000000
665 #interrupt-cells = <2>;
667 #address-cells = <2>;
668 reg = <0xf000 0x0 0x0 0x0 0x0>;
669 ranges = <0x1 0x0 0x1000000 0x0 0x0
671 interrupt-parent = <&i8259>;
673 i8259: interrupt-controller@20 {
677 interrupt-controller;
678 device_type = "interrupt-controller";
679 #address-cells = <0>;
680 #interrupt-cells = <2>;
681 compatible = "chrp,iic";
683 interrupt-parent = <&mpic>;
688 #address-cells = <1>;
689 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
690 interrupts = <1 3 12 3>;
696 compatible = "pnpPNP,303";
701 compatible = "pnpPNP,f03";
706 compatible = "pnpPNP,b00";
707 reg = <0x1 0x70 0x2>;
711 reg = <0x1 0x400 0x80>;
719 pci2: pcie@ffe0a000 {
720 compatible = "fsl,mpc8548-pcie";
722 #interrupt-cells = <1>;
724 #address-cells = <3>;
725 reg = <0 0xffe0a000 0 0x1000>;
727 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
728 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
729 clock-frequency = <33333333>;
730 interrupt-parent = <&mpic>;
732 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
735 0000 0x0 0x0 0x1 &mpic 0x0 0x1
736 0000 0x0 0x0 0x2 &mpic 0x1 0x1
737 0000 0x0 0x0 0x3 &mpic 0x2 0x1
738 0000 0x0 0x0 0x4 &mpic 0x3 0x1
741 reg = <0x0 0x0 0x0 0x0 0x0>;
743 #address-cells = <3>;
745 ranges = <0x2000000 0x0 0xc0000000
746 0x2000000 0x0 0xc0000000