2 * P2041RDB Device Tree Source
4 * Copyright 2011 Freescale Semiconductor Inc.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
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15 * derived from this software without specific prior written permission.
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
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36 /include/ "p2041si.dtsi"
39 model = "fsl,P2041RDB";
40 compatible = "fsl,P2041RDB";
43 interrupt-parent = <&mpic>;
46 phy_rgmii_0 = &phy_rgmii_0;
47 phy_rgmii_1 = &phy_rgmii_1;
48 phy_sgmii_2 = &phy_sgmii_2;
49 phy_sgmii_3 = &phy_sgmii_3;
50 phy_sgmii_4 = &phy_sgmii_4;
51 phy_sgmii_1c = &phy_sgmii_1c;
52 phy_sgmii_1d = &phy_sgmii_1d;
53 phy_sgmii_1e = &phy_sgmii_1e;
54 phy_sgmii_1f = &phy_sgmii_1f;
55 phy_xgmii_2 = &phy_xgmii_2;
59 device_type = "memory";
60 reg = <0x00000000 0x00000000 0x00000000 0x80000000>;
63 dcsr: dcsr@f00000000 {
64 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
67 bman-portals@ff4000000 {
94 compatible = "fsl,p2041-bpool", "fsl,bpool";
96 fsl,bpool-cfg = <0 0x100 0 1 0 0x100>;
100 qman-portals@ff4200000 {
101 qportal0: qman-portal@0 {
102 cpu-handle = <&cpu0>;
103 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
104 &qpool4 &qpool5 &qpool6
105 &qpool7 &qpool8 &qpool9
106 &qpool10 &qpool11 &qpool12
107 &qpool13 &qpool14 &qpool15>;
110 qportal1: qman-portal@4000 {
111 cpu-handle = <&cpu1>;
112 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
113 &qpool4 &qpool5 &qpool6
114 &qpool7 &qpool8 &qpool9
115 &qpool10 &qpool11 &qpool12
116 &qpool13 &qpool14 &qpool15>;
119 qportal2: qman-portal@8000 {
120 cpu-handle = <&cpu2>;
121 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
122 &qpool4 &qpool5 &qpool6
123 &qpool7 &qpool8 &qpool9
124 &qpool10 &qpool11 &qpool12
125 &qpool13 &qpool14 &qpool15>;
128 qportal3: qman-portal@c000 {
129 cpu-handle = <&cpu3>;
130 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
131 &qpool4 &qpool5 &qpool6
132 &qpool7 &qpool8 &qpool9
133 &qpool10 &qpool11 &qpool12
134 &qpool13 &qpool14 &qpool15>;
137 qportal4: qman-portal@10000 {
138 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
139 &qpool4 &qpool5 &qpool6
140 &qpool7 &qpool8 &qpool9
141 &qpool10 &qpool11 &qpool12
142 &qpool13 &qpool14 &qpool15>;
145 qportal5: qman-portal@14000 {
146 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
147 &qpool4 &qpool5 &qpool6
148 &qpool7 &qpool8 &qpool9
149 &qpool10 &qpool11 &qpool12
150 &qpool13 &qpool14 &qpool15>;
153 qportal6: qman-portal@18000 {
154 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
155 &qpool4 &qpool5 &qpool6
156 &qpool7 &qpool8 &qpool9
157 &qpool10 &qpool11 &qpool12
158 &qpool13 &qpool14 &qpool15>;
161 qportal7: qman-portal@1c000 {
162 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
163 &qpool4 &qpool5 &qpool6
164 &qpool7 &qpool8 &qpool9
165 &qpool10 &qpool11 &qpool12
166 &qpool13 &qpool14 &qpool15>;
169 qportal8: qman-portal@20000 {
170 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
171 &qpool4 &qpool5 &qpool6
172 &qpool7 &qpool8 &qpool9
173 &qpool10 &qpool11 &qpool12
174 &qpool13 &qpool14 &qpool15>;
177 qportal9: qman-portal@24000 {
178 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
179 &qpool4 &qpool5 &qpool6
180 &qpool7 &qpool8 &qpool9
181 &qpool10 &qpool11 &qpool12
182 &qpool13 &qpool14 &qpool15>;
189 #address-cells = <1>;
191 compatible = "spansion,s25sl12801";
193 spi-max-frequency = <40000000>; /* input clock */
196 reg = <0x00000000 0x00100000>;
201 reg = <0x00100000 0x00500000>;
206 reg = <0x00600000 0x00100000>;
210 label = "file system";
211 reg = <0x00700000 0x00900000>;
218 compatible = "nxp,lm75a";
222 compatible = "at24,24c256";
226 compatible = "pericom,pt7c4338";
233 compatible = "at24,24c256";
243 /* Commented out, use default allocation */
244 /* fsl,pme-pdsr = <0x0 0x23000000 0x0 0x01000000>; */
245 /* fsl,pme-sre = <0x0 0x24000000 0x0 0x00a00000>; */
249 /* Commented out, use default allocation */
250 /* fsl,qman-fqd = <0x0 0x20000000 0x0 0x01000000>; */
251 /* fsl,qman-pfdr = <0x0 0x21000000 0x0 0x01000000>; */
255 /* Same as fsl,qman-*, use default allocation */
256 /* fsl,bman-fbpr = <0x0 0x22000000 0x0 0x01000000>; */
260 enet0: ethernet@e0000 {
261 tbi-handle = <&tbi0>;
262 phy-handle = <&phy_sgmii_2>;
263 phy-connection-type = "sgmii";
269 device_type = "tbi-phy";
272 phy_rgmii_0: ethernet-phy@0 {
275 phy_rgmii_1: ethernet-phy@1 {
278 phy_sgmii_2: ethernet-phy@2 {
281 phy_sgmii_3: ethernet-phy@3 {
284 phy_sgmii_4: ethernet-phy@4 {
287 phy_sgmii_1c: ethernet-phy@1c {
290 phy_sgmii_1d: ethernet-phy@1d {
293 phy_sgmii_1e: ethernet-phy@1e {
296 phy_sgmii_1f: ethernet-phy@1f {
301 enet1: ethernet@e2000 {
302 tbi-handle = <&tbi1>;
303 phy-handle = <&phy_sgmii_3>;
304 phy-connection-type = "sgmii";
310 device_type = "tbi-phy";
314 enet2: ethernet@e4000 {
315 tbi-handle = <&tbi2>;
316 phy-handle = <&phy_sgmii_4>;
317 phy-connection-type = "sgmii";
323 device_type = "tbi-phy";
327 enet3: ethernet@e6000 {
328 tbi-handle = <&tbi3>;
329 phy-handle = <&phy_rgmii_1>;
330 phy-connection-type = "rgmii";
336 device_type = "tbi-phy";
340 enet4: ethernet@e8000 {
341 tbi-handle = <&tbi4>;
342 phy-handle = <&phy_rgmii_0>;
343 phy-connection-type = "rgmii";
349 device_type = "tbi-phy";
353 enet5: ethernet@f0000 {
355 * phy-handle will be updated by U-Boot to
356 * reflect the actual slot the XAUI card is in.
358 phy-handle = <&phy_xgmii_2>;
359 phy-connection-type = "xgmii";
363 /* XAUI card in slot 2 */
364 phy_xgmii_2: ethernet-phy@0 {
372 reg = <0xf 0xfe0c0000 0 0x11000>;
375 ranges = <0 0 0xc 0x20000000 0 0x10000000>;
378 ranges = <0 0 0xc 0x30000000 0 0x10000000>;
383 reg = <0xf 0xfe124000 0 0x1000>;
384 ranges = <0 0 0xf 0xb8000000 0x04000000>;
387 compatible = "cfi-flash";
389 * Map 64Mb of 128MB NOR flash memory. Since highest
390 * line of address of NOR flash memory are set by
391 * FPGA, memory are divided into two pages equal to
392 * 64MB. One of the pages can be accessed at once.
394 reg = <0 0 0x04000000>;
400 pci0: pcie@ffe200000 {
401 reg = <0xf 0xfe200000 0 0x1000>;
402 ranges = <0x02000000 0 0x80000000 0x0 0x80000000 0x0 0x10000000
403 0x01000000 0 0x00000000 0x0 0xff000000 0x0 0x00010000>;
405 ranges = <0x02000000 0 0x80000000
406 0x02000000 0 0x80000000
409 0x01000000 0 0x00000000
410 0x01000000 0 0xff000000
415 pci1: pcie@ffe201000 {
416 reg = <0xf 0xfe201000 0 0x1000>;
417 ranges = <0x02000000 0x0 0x90000000 0x0 0x90000000 0x0 0x10000000
418 0x01000000 0x0 0x00000000 0x0 0xff010000 0x0 0x00010000>;
420 ranges = <0x02000000 0 0x90000000
421 0x02000000 0 0x90000000
424 0x01000000 0 0x00000000
425 0x01000000 0 0xff010000
430 pci2: pcie@ffe202000 {
431 reg = <0xf 0xfe202000 0 0x1000>;
432 ranges = <0x02000000 0 0xa0000000 0x0 0xa0000000 0 0x10000000
433 0x01000000 0 0x00000000 0x0 0xff020000 0 0x00010000>;
435 ranges = <0x02000000 0 0xa0000000
436 0x02000000 0 0xa0000000
439 0x01000000 0 0x00000000
440 0x01000000 0 0xff020000