2 * P3041DS Device Tree Source
4 * Copyright 2010-2011 Freescale Semiconductor Inc.
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7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
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18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
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36 /include/ "p3041si.dtsi"
39 model = "fsl,P3041DS";
40 compatible = "fsl,P3041DS";
43 interrupt-parent = <&mpic>;
46 phy_rgmii_0 = &phy_rgmii_0;
47 phy_rgmii_1 = &phy_rgmii_1;
48 phy_sgmii_1c = &phy_sgmii_1c;
49 phy_sgmii_1d = &phy_sgmii_1d;
50 phy_sgmii_1e = &phy_sgmii_1e;
51 phy_sgmii_1f = &phy_sgmii_1f;
52 phy_xgmii_1 = &phy_xgmii_1;
53 phy_xgmii_2 = &phy_xgmii_2;
54 emi1_rgmii = &hydra_mdio_rgmii;
55 emi1_sgmii = &hydra_mdio_sgmii;
56 emi2_xgmii = &hydra_mdio_xgmii;
60 device_type = "memory";
61 reg = <0x00000000 0x00000000 0x00000000 0x80000000>;
64 dcsr: dcsr@f00000000 {
65 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
68 bman-portals@ff4000000 {
95 compatible = "fsl,p3041-bpool", "fsl,bpool";
97 fsl,bpool-cfg = <0 0x100 0 1 0 0x100>;
101 qman-portals@ff4200000 {
102 qportal0: qman-portal@0 {
103 cpu-handle = <&cpu0>;
104 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
105 &qpool4 &qpool5 &qpool6
106 &qpool7 &qpool8 &qpool9
107 &qpool10 &qpool11 &qpool12
108 &qpool13 &qpool14 &qpool15>;
111 qportal1: qman-portal@4000 {
112 cpu-handle = <&cpu1>;
113 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
114 &qpool4 &qpool5 &qpool6
115 &qpool7 &qpool8 &qpool9
116 &qpool10 &qpool11 &qpool12
117 &qpool13 &qpool14 &qpool15>;
120 qportal2: qman-portal@8000 {
121 cpu-handle = <&cpu2>;
122 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
123 &qpool4 &qpool5 &qpool6
124 &qpool7 &qpool8 &qpool9
125 &qpool10 &qpool11 &qpool12
126 &qpool13 &qpool14 &qpool15>;
129 qportal3: qman-portal@c000 {
130 cpu-handle = <&cpu3>;
131 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
132 &qpool4 &qpool5 &qpool6
133 &qpool7 &qpool8 &qpool9
134 &qpool10 &qpool11 &qpool12
135 &qpool13 &qpool14 &qpool15>;
138 qportal4: qman-portal@10000 {
139 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
140 &qpool4 &qpool5 &qpool6
141 &qpool7 &qpool8 &qpool9
142 &qpool10 &qpool11 &qpool12
143 &qpool13 &qpool14 &qpool15>;
146 qportal5: qman-portal@14000 {
147 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
148 &qpool4 &qpool5 &qpool6
149 &qpool7 &qpool8 &qpool9
150 &qpool10 &qpool11 &qpool12
151 &qpool13 &qpool14 &qpool15>;
154 qportal6: qman-portal@18000 {
155 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
156 &qpool4 &qpool5 &qpool6
157 &qpool7 &qpool8 &qpool9
158 &qpool10 &qpool11 &qpool12
159 &qpool13 &qpool14 &qpool15>;
162 qportal7: qman-portal@1c000 {
163 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
164 &qpool4 &qpool5 &qpool6
165 &qpool7 &qpool8 &qpool9
166 &qpool10 &qpool11 &qpool12
167 &qpool13 &qpool14 &qpool15>;
170 qportal8: qman-portal@20000 {
171 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
172 &qpool4 &qpool5 &qpool6
173 &qpool7 &qpool8 &qpool9
174 &qpool10 &qpool11 &qpool12
175 &qpool13 &qpool14 &qpool15>;
178 qportal9: qman-portal@24000 {
179 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
180 &qpool4 &qpool5 &qpool6
181 &qpool7 &qpool8 &qpool9
182 &qpool10 &qpool11 &qpool12
183 &qpool13 &qpool14 &qpool15>;
190 #address-cells = <1>;
192 compatible = "spansion,s25sl12801";
194 spi-max-frequency = <35000000>; /* input clock */
197 reg = <0x00000000 0x00100000>;
202 reg = <0x00100000 0x00500000>;
207 reg = <0x00600000 0x00100000>;
211 label = "file system";
212 reg = <0x00700000 0x00900000>;
219 compatible = "at24,24c256";
223 compatible = "at24,24c256";
230 compatible = "dallas,ds3232";
232 interrupts = <0x1 0x1 0 0>;
237 /* Commented out, use default allocation */
238 /* fsl,pme-pdsr = <0x0 0x23000000 0x0 0x01000000>; */
239 /* fsl,pme-sre = <0x0 0x24000000 0x0 0x00a00000>; */
243 /* Commented out, use default allocation */
244 /* fsl,qman-fqd = <0x0 0x20000000 0x0 0x01000000>; */
245 /* fsl,qman-pfdr = <0x0 0x21000000 0x0 0x01000000>; */
249 /* Same as fsl,qman-*, use default allocation */
250 /* fsl,bman-fbpr = <0x0 0x22000000 0x0 0x01000000>; */
254 enet0: ethernet@e0000 {
255 tbi-handle = <&tbi0>;
256 phy-handle = <&phy_rgmii_0>;
257 phy-connection-type = "rgmii";
263 device_type = "tbi-phy";
267 * Virtual MDIO for the two on-board RGMII
268 * ports. The fsl,hydra-mdio-muxval property
269 * is already correct.
271 hydra_mdio_rgmii: hydra-mdio-rgmii {
272 #address-cells = <1>;
274 compatible = "fsl,hydra-mdio";
275 fsl,mdio-handle = <&mdio0>;
276 fsl,hydra-mdio-muxval = <0x00>;
279 phy_rgmii_0: ethernet-phy@0 {
282 phy_rgmii_1: ethernet-phy@1 {
288 * Virtual MDIO for the four-port SGMII card.
289 * The fsl,hydra-mdio-muxval property will be
290 * fixed-up by U-Boot based on the slot that
291 * the SGMII card is in.
293 * Note: we do not support DTSEC5 connected to
294 * SGMII, so this is the only SGMII node.
296 hydra_mdio_sgmii: hydra-mdio-sgmii {
297 #address-cells = <1>;
299 compatible = "fsl,hydra-mdio";
300 fsl,mdio-handle = <&mdio0>;
301 fsl,hydra-mdio-muxval = <0x00>;
304 phy_sgmii_1c: ethernet-phy@1c {
307 phy_sgmii_1d: ethernet-phy@1d {
310 phy_sgmii_1e: ethernet-phy@1e {
313 phy_sgmii_1f: ethernet-phy@1f {
319 enet1: ethernet@e2000 {
320 tbi-handle = <&tbi1>;
321 phy-handle = <&phy_sgmii_1d>;
322 phy-connection-type = "sgmii";
328 device_type = "tbi-phy";
332 enet2: ethernet@e4000 {
333 tbi-handle = <&tbi2>;
334 phy-handle = <&phy_sgmii_1e>;
335 phy-connection-type = "sgmii";
341 device_type = "tbi-phy";
345 enet3: ethernet@e6000 {
346 tbi-handle = <&tbi3>;
347 phy-handle = <&phy_sgmii_1f>;
348 phy-connection-type = "sgmii";
352 #address-cells = <1>;
354 compatible = "fsl,fman-tbi";
355 reg = <0xe7120 0xee0>;
356 interrupts = <100 1 0 0>;
360 device_type = "tbi-phy";
364 enet4: ethernet@e8000 {
365 tbi-handle = <&tbi4>;
366 phy-handle = <&phy_rgmii_1>;
367 phy-connection-type = "rgmii";
373 device_type = "tbi-phy";
377 enet5: ethernet@f0000 {
379 * phy-handle will be updated by U-Boot to
380 * reflect the actual slot the XAUI card is in.
382 phy-handle = <&phy_xgmii_1>;
383 phy-connection-type = "xgmii";
387 * We only support one XAUI card, so the MDIO muxing
388 * is set by U-Boot, and Linux never touches it.
389 * Therefore, we don't need a virtual MDIO node.
390 * However, the phy address depends on the slot, so
391 * only one of the ethernet-phy nodes below will be
394 hydra_mdio_xgmii: mdio@f1000 {
397 /* XAUI card in slot 1 */
398 phy_xgmii_1: ethernet-phy@4 {
402 /* XAUI card in slot 2 */
403 phy_xgmii_2: ethernet-phy@0 {
411 reg = <0xf 0xfe0c0000 0 0x11000>;
414 ranges = <0 0 0xc 0x20000000 0 0x10000000>;
417 ranges = <0 0 0xc 0x30000000 0 0x10000000>;
422 reg = <0xf 0xfe124000 0 0x1000>;
423 ranges = <0 0 0xf 0xb8000000 0x04000000>;
426 compatible = "cfi-flash";
428 * Map 64Mb of 128MB NOR flash memory. Since highest
429 * line of address of NOR flash memory are set by
430 * FPGA, memory are divided into two pages equal to
431 * 64MB. One of the pages can be accessed at once.
433 reg = <0 0 0x04000000>;
439 #address-cells = <1>;
441 compatible = "fsl,elbc-fcm-nand";
442 reg = <0x2 0x0 0x40000>;
445 label = "NAND U-Boot Image";
446 reg = <0x0 0x02000000>;
451 label = "NAND Root File System";
452 reg = <0x02000000 0x10000000>;
456 label = "NAND Compressed RFS Image";
457 reg = <0x12000000 0x08000000>;
461 label = "NAND Linux Kernel Image";
462 reg = <0x1a000000 0x04000000>;
466 label = "NAND DTB Image";
467 reg = <0x1e000000 0x01000000>;
471 label = "NAND Writable User area";
472 reg = <0x1f000000 0x21000000>;
477 compatible = "fsl,p3041ds-fpga", "fsl,fpga-ngpixis";
482 pci0: pcie@ffe200000 {
483 reg = <0xf 0xfe200000 0 0x1000>;
484 ranges = <0x02000000 0 0x80000000 0x0 0x80000000 0x0 0x10000000
485 0x01000000 0 0x00000000 0x0 0xff000000 0x0 0x00010000>;
487 ranges = <0x02000000 0 0x80000000
488 0x02000000 0 0x80000000
491 0x01000000 0 0x00000000
492 0x01000000 0 0xff000000
497 pci1: pcie@ffe201000 {
498 reg = <0xf 0xfe201000 0 0x1000>;
499 ranges = <0x02000000 0x0 0x90000000 0x0 0x90000000 0x0 0x10000000
500 0x01000000 0x0 0x00000000 0x0 0xff010000 0x0 0x00010000>;
502 ranges = <0x02000000 0 0x90000000
503 0x02000000 0 0x90000000
506 0x01000000 0 0x00000000
507 0x01000000 0 0xff010000
512 pci2: pcie@ffe202000 {
513 reg = <0xf 0xfe202000 0 0x1000>;
514 ranges = <0x02000000 0 0xa0000000 0x0 0xa0000000 0 0x10000000
515 0x01000000 0 0x00000000 0x0 0xff020000 0 0x00010000>;
517 ranges = <0x02000000 0 0xa0000000
518 0x02000000 0 0xa0000000
521 0x01000000 0 0x00000000
522 0x01000000 0 0xff020000
527 pci3: pcie@ffe203000 {
528 reg = <0xf 0xfe203000 0 0x1000>;
529 ranges = <0x02000000 0 0xb0000000 0x0 0xb0000000 0 0x08000000
530 0x01000000 0 0x00000000 0x0 0xff030000 0 0x00010000>;
532 ranges = <0x02000000 0 0xb0000000
533 0x02000000 0 0xb0000000
536 0x01000000 0 0x00000000
537 0x01000000 0 0xff030000