2 * P5020DS Device Tree Source
4 * Copyright 2010-2011 Freescale Semiconductor Inc.
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7 * modification, are permitted provided that the following conditions are met:
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36 /include/ "p5020si.dtsi"
39 model = "fsl,P5020DS";
40 compatible = "fsl,P5020DS";
43 interrupt-parent = <&mpic>;
46 phy_rgmii_0 = &phy_rgmii_0;
47 phy_rgmii_1 = &phy_rgmii_1;
48 phy_sgmii_1c = &phy_sgmii_1c;
49 phy_sgmii_1d = &phy_sgmii_1d;
50 phy_sgmii_1e = &phy_sgmii_1e;
51 phy_sgmii_1f = &phy_sgmii_1f;
52 phy_xgmii_1 = &phy_xgmii_1;
53 phy_xgmii_2 = &phy_xgmii_2;
54 emi1_rgmii = &hydra_mdio_rgmii;
55 emi1_sgmii = &hydra_mdio_sgmii;
56 emi2_xgmii = &hydra_mdio_xgmii;
60 device_type = "memory";
61 reg = <0x00000000 0x00000000 0x00000000 0x80000000>;
64 dcsr: dcsr@f00000000 {
65 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
68 bman-portals@ff4000000 {
93 compatible = "fsl,p5020-bpool", "fsl,bpool";
95 fsl,bpool-cfg = <0 0x100 0 1 0 0x100>;
99 qman-portals@ff4200000 {
100 qportal0: qman-portal@0 {
101 cpu-handle = <&cpu0>;
102 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
103 &qpool4 &qpool5 &qpool6
104 &qpool7 &qpool8 &qpool9
105 &qpool10 &qpool11 &qpool12
106 &qpool13 &qpool14 &qpool15>;
109 qportal1: qman-portal@4000 {
110 cpu-handle = <&cpu1>;
111 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
112 &qpool4 &qpool5 &qpool6
113 &qpool7 &qpool8 &qpool9
114 &qpool10 &qpool11 &qpool12
115 &qpool13 &qpool14 &qpool15>;
118 qportal2: qman-portal@8000 {
119 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
120 &qpool4 &qpool5 &qpool6
121 &qpool7 &qpool8 &qpool9
122 &qpool10 &qpool11 &qpool12
123 &qpool13 &qpool14 &qpool15>;
126 qportal3: qman-portal@c000 {
127 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
128 &qpool4 &qpool5 &qpool6
129 &qpool7 &qpool8 &qpool9
130 &qpool10 &qpool11 &qpool12
131 &qpool13 &qpool14 &qpool15>;
134 qportal4: qman-portal@10000 {
135 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
136 &qpool4 &qpool5 &qpool6
137 &qpool7 &qpool8 &qpool9
138 &qpool10 &qpool11 &qpool12
139 &qpool13 &qpool14 &qpool15>;
142 qportal5: qman-portal@14000 {
143 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
144 &qpool4 &qpool5 &qpool6
145 &qpool7 &qpool8 &qpool9
146 &qpool10 &qpool11 &qpool12
147 &qpool13 &qpool14 &qpool15>;
150 qportal6: qman-portal@18000 {
151 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
152 &qpool4 &qpool5 &qpool6
153 &qpool7 &qpool8 &qpool9
154 &qpool10 &qpool11 &qpool12
155 &qpool13 &qpool14 &qpool15>;
158 qportal7: qman-portal@1c000 {
159 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
160 &qpool4 &qpool5 &qpool6
161 &qpool7 &qpool8 &qpool9
162 &qpool10 &qpool11 &qpool12
163 &qpool13 &qpool14 &qpool15>;
166 qportal8: qman-portal@20000 {
167 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
168 &qpool4 &qpool5 &qpool6
169 &qpool7 &qpool8 &qpool9
170 &qpool10 &qpool11 &qpool12
171 &qpool13 &qpool14 &qpool15>;
174 qportal9: qman-portal@24000 {
175 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
176 &qpool4 &qpool5 &qpool6
177 &qpool7 &qpool8 &qpool9
178 &qpool10 &qpool11 &qpool12
179 &qpool13 &qpool14 &qpool15>;
186 #address-cells = <1>;
188 compatible = "spansion,s25sl12801";
190 spi-max-frequency = <40000000>; /* input clock */
193 reg = <0x00000000 0x00100000>;
198 reg = <0x00100000 0x00500000>;
203 reg = <0x00600000 0x00100000>;
207 label = "file system";
208 reg = <0x00700000 0x00900000>;
215 compatible = "at24,24c256";
219 compatible = "at24,24c256";
226 compatible = "dallas,ds3232";
228 interrupts = <0x1 0x1 0 0>;
233 /* Commented out, use default allocation */
234 /* fsl,pme-pdsr = <0x0 0x23000000 0x0 0x01000000>; */
235 /* fsl,pme-sre = <0x0 0x24000000 0x0 0x00a00000>; */
239 /* Commented out, use default allocation */
240 /* fsl,qman-fqd = <0x0 0x20000000 0x0 0x01000000>; */
241 /* fsl,qman-pfdr = <0x0 0x21000000 0x0 0x01000000>; */
245 /* Same as fsl,qman-*, use default allocation */
246 /* fsl,bman-fbpr = <0x0 0x22000000 0x0 0x01000000>; */
250 enet0: ethernet@e0000 {
251 tbi-handle = <&tbi0>;
252 phy-handle = <&phy_rgmii_0>;
253 phy-connection-type = "rgmii";
259 device_type = "tbi-phy";
263 * Virtual MDIO for the two on-board RGMII
264 * ports. The fsl,hydra-mdio-muxval property
265 * is already correct.
267 hydra_mdio_rgmii: hydra-mdio-rgmii {
268 #address-cells = <1>;
270 compatible = "fsl,hydra-mdio";
271 fsl,mdio-handle = <&mdio0>;
272 fsl,hydra-mdio-muxval = <0x00>;
275 phy_rgmii_0: ethernet-phy@0 {
278 phy_rgmii_1: ethernet-phy@1 {
284 * Virtual MDIO for the four-port SGMII card.
285 * The fsl,hydra-mdio-muxval property will be
286 * fixed-up by U-Boot based on the slot that
287 * the SGMII card is in.
289 * Note: we do not support DTSEC5 connected to
290 * SGMII, so this is the only SGMII node.
292 hydra_mdio_sgmii: hydra-mdio-sgmii {
293 #address-cells = <1>;
295 compatible = "fsl,hydra-mdio";
296 fsl,mdio-handle = <&mdio0>;
297 fsl,hydra-mdio-muxval = <0x00>;
300 phy_sgmii_1c: ethernet-phy@1c {
303 phy_sgmii_1d: ethernet-phy@1d {
306 phy_sgmii_1e: ethernet-phy@1e {
309 phy_sgmii_1f: ethernet-phy@1f {
315 enet1: ethernet@e2000 {
316 tbi-handle = <&tbi1>;
317 phy-handle = <&phy_sgmii_1d>;
318 phy-connection-type = "sgmii";
324 device_type = "tbi-phy";
328 enet2: ethernet@e4000 {
329 tbi-handle = <&tbi2>;
330 phy-handle = <&phy_sgmii_1e>;
331 phy-connection-type = "sgmii";
337 device_type = "tbi-phy";
341 enet3: ethernet@e6000 {
342 tbi-handle = <&tbi3>;
343 phy-handle = <&phy_sgmii_1f>;
344 phy-connection-type = "sgmii";
348 #address-cells = <1>;
350 compatible = "fsl,fman-tbi";
351 reg = <0xe7120 0xee0>;
352 interrupts = <100 1 0 0>;
356 device_type = "tbi-phy";
360 enet4: ethernet@e8000 {
361 tbi-handle = <&tbi4>;
362 phy-handle = <&phy_rgmii_1>;
363 phy-connection-type = "rgmii";
369 device_type = "tbi-phy";
373 enet5: ethernet@f0000 {
375 * phy-handle will be updated by U-Boot to
376 * reflect the actual slot the XAUI card is in.
378 phy-handle = <&phy_xgmii_1>;
379 phy-connection-type = "xgmii";
383 * We only support one XAUI card, so the MDIO muxing
384 * is set by U-Boot, and Linux never touches it.
385 * Therefore, we don't need a virtual MDIO node.
386 * However, the phy address depends on the slot, so
387 * only one of the ethernet-phy nodes below will be
390 hydra_mdio_xgmii: mdio@f1000 {
393 /* XAUI card in slot 1 */
394 phy_xgmii_1: ethernet-phy@4 {
398 /* XAUI card in slot 2 */
399 phy_xgmii_2: ethernet-phy@0 {
407 reg = <0xf 0xfe0c0000 0 0x11000>;
410 ranges = <0 0 0xc 0x20000000 0 0x10000000>;
413 ranges = <0 0 0xc 0x30000000 0 0x10000000>;
418 reg = <0xf 0xfe124000 0 0x1000>;
419 ranges = <0 0 0xf 0xb8000000 0x04000000>;
422 compatible = "cfi-flash";
424 * Map 64Mb of 128MB NOR flash memory. Since highest
425 * line of address of NOR flash memory are set by
426 * FPGA, memory are divided into two pages equal to
427 * 64MB. One of the pages can be accessed at once.
429 reg = <0 0 0x04000000>;
435 #address-cells = <1>;
437 compatible = "fsl,elbc-fcm-nand";
438 reg = <0x2 0x0 0x40000>;
441 label = "NAND U-Boot Image";
442 reg = <0x0 0x02000000>;
447 label = "NAND Root File System";
448 reg = <0x02000000 0x10000000>;
452 label = "NAND Compressed RFS Image";
453 reg = <0x12000000 0x08000000>;
457 label = "NAND Linux Kernel Image";
458 reg = <0x1a000000 0x04000000>;
462 label = "NAND DTB Image";
463 reg = <0x1e000000 0x01000000>;
467 label = "NAND Writable User area";
468 reg = <0x1f000000 0x21000000>;
473 compatible = "fsl,p5020ds-fpga", "fsl,fpga-ngpixis";
478 pci0: pcie@ffe200000 {
479 reg = <0xf 0xfe200000 0 0x1000>;
480 ranges = <0x02000000 0 0x80000000 0x0 0x80000000 0x0 0x10000000
481 0x01000000 0 0x00000000 0x0 0xff000000 0x0 0x00010000>;
483 ranges = <0x02000000 0 0x80000000
484 0x02000000 0 0x80000000
487 0x01000000 0 0x00000000
488 0x01000000 0 0xff000000
493 pci1: pcie@ffe201000 {
494 reg = <0xf 0xfe201000 0 0x1000>;
495 ranges = <0x02000000 0x0 0x90000000 0x0 0x90000000 0x0 0x10000000
496 0x01000000 0x0 0x00000000 0x0 0xff010000 0x0 0x00010000>;
498 ranges = <0x02000000 0 0x90000000
499 0x02000000 0 0x90000000
502 0x01000000 0 0x00000000
503 0x01000000 0 0xff010000
508 pci2: pcie@ffe202000 {
509 reg = <0xf 0xfe202000 0 0x1000>;
510 ranges = <0x02000000 0 0xa0000000 0x0 0xa0000000 0 0x10000000
511 0x01000000 0 0x00000000 0x0 0xff020000 0 0x00010000>;
513 ranges = <0x02000000 0 0xa0000000
514 0x02000000 0 0xa0000000
517 0x01000000 0 0x00000000
518 0x01000000 0 0xff020000
523 pci3: pcie@ffe203000 {
524 reg = <0xf 0xfe203000 0 0x1000>;
525 ranges = <0x02000000 0 0xb0000000 0x0 0xb0000000 0 0x08000000
526 0x01000000 0 0x00000000 0x0 0xff030000 0 0x00010000>;
528 ranges = <0x02000000 0 0xb0000000
529 0x02000000 0 0xb0000000
532 0x01000000 0 0x00000000
533 0x01000000 0 0xff030000