2 * Copyright 2016 Linaro Ltd
4 * Permission is hereby granted, free of charge, to any person obtaining a copy
5 * of this software and associated documentation files (the "Software"), to deal
6 * in the Software without restriction, including without limitation the rights
7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8 * copies of the Software, and to permit persons to whom the Software is
9 * furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 #include <dt-bindings/interrupt-controller/irq.h>
24 #include <dt-bindings/gpio/gpio.h>
29 compatible = "arm,realview-pbx";
43 device_type = "memory";
44 /* 128 MiB memory @ 0x0 */
45 reg = <0x00000000 0x08000000>;
48 /* The voltage to the MMC card is hardwired at 3.3V */
49 vmmc: regulator-vmmc {
50 compatible = "regulator-fixed";
51 regulator-name = "vmmc";
52 regulator-min-microvolt = <3300000>;
53 regulator-max-microvolt = <3300000>;
57 veth: regulator-veth {
58 compatible = "regulator-fixed";
59 regulator-name = "veth";
60 regulator-min-microvolt = <3300000>;
61 regulator-max-microvolt = <3300000>;
65 xtal24mhz: xtal24mhz@24M {
67 compatible = "fixed-clock";
68 clock-frequency = <24000000>;
71 refclk32khz: refclk32khz {
73 compatible = "fixed-clock";
74 clock-frequency = <32768>;
79 compatible = "fixed-factor-clock";
82 clocks = <&xtal24mhz>;
87 compatible = "fixed-factor-clock";
90 clocks = <&xtal24mhz>;
95 compatible = "fixed-factor-clock";
98 clocks = <&xtal24mhz>;
103 compatible = "fixed-factor-clock";
106 clocks = <&xtal24mhz>;
109 uartclk: uartclk@24M {
111 compatible = "fixed-factor-clock";
114 clocks = <&xtal24mhz>;
117 wdogclk: wdogclk@24M {
119 compatible = "fixed-factor-clock";
122 clocks = <&xtal24mhz>;
125 /* FIXME: this actually hangs off the PLL clocks */
128 compatible = "fixed-clock";
129 clock-frequency = <0>;
133 /* 2 * 32MiB NOR Flash memory */
134 compatible = "arm,versatile-flash", "cfi-flash";
135 reg = <0x40000000 0x04000000>;
140 /* 2 * 32MiB NOR Flash memory */
141 compatible = "arm,versatile-flash", "cfi-flash";
142 reg = <0x44000000 0x04000000>;
146 /* SMSC 9118 ethernet with PHY and EEPROM */
147 ethernet: ethernet@4e000000 {
148 compatible = "smsc,lan9118", "smsc,lan9115";
149 reg = <0x4e000000 0x10000>;
152 smsc,irq-active-high;
154 vdd33a-supply = <&veth>;
155 vddvario-supply = <&veth>;
159 compatible = "nxp,usb-isp1761";
160 reg = <0x4f000000 0x20000>;
165 compatible = "ti,ths8134a", "ti,ths8134";
166 #address-cells = <1>;
170 #address-cells = <1>;
176 vga_bridge_in: endpoint {
177 remote-endpoint = <&clcd_pads>;
184 vga_bridge_out: endpoint {
185 remote-endpoint = <&vga_con_in>;
193 * This DDC I2C is connected directly to the DVI portions
194 * of the connector, so it's not really working when the
195 * monitor is connected to the VGA connector.
197 compatible = "vga-connector";
198 ddc-i2c-bus = <&i2c1>;
201 vga_con_in: endpoint {
202 remote-endpoint = <&vga_bridge_out>;
208 compatible = "arm,realview-pbx-soc", "simple-bus";
209 #address-cells = <1>;
214 syscon: syscon@10000000 {
215 compatible = "arm,realview-pbx-syscon", "syscon", "simple-mfd";
216 reg = <0x10000000 0x1000>;
219 compatible = "register-bit-led";
222 label = "versatile:0";
223 linux,default-trigger = "heartbeat";
224 default-state = "on";
227 compatible = "register-bit-led";
230 label = "versatile:1";
231 linux,default-trigger = "mmc0";
232 default-state = "off";
235 compatible = "register-bit-led";
238 label = "versatile:2";
239 linux,default-trigger = "cpu0";
240 default-state = "off";
243 compatible = "register-bit-led";
246 label = "versatile:3";
247 default-state = "off";
250 compatible = "register-bit-led";
253 label = "versatile:4";
254 default-state = "off";
257 compatible = "register-bit-led";
260 label = "versatile:5";
261 default-state = "off";
264 compatible = "register-bit-led";
267 label = "versatile:6";
268 default-state = "off";
271 compatible = "register-bit-led";
274 label = "versatile:7";
275 default-state = "off";
278 compatible = "arm,syscon-icst307";
280 lock-offset = <0x20>;
282 clocks = <&xtal24mhz>;
285 compatible = "arm,syscon-icst307";
287 lock-offset = <0x20>;
289 clocks = <&xtal24mhz>;
292 compatible = "arm,syscon-icst307";
294 lock-offset = <0x20>;
296 clocks = <&xtal24mhz>;
299 compatible = "arm,syscon-icst307";
301 lock-offset = <0x20>;
303 clocks = <&xtal24mhz>;
306 compatible = "arm,syscon-icst307";
308 lock-offset = <0x20>;
310 clocks = <&xtal24mhz>;
314 sp810_syscon0: sysctl@10001000 {
315 compatible = "arm,sp810", "arm,primecell";
316 reg = <0x10001000 0x1000>;
317 clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>;
318 clock-names = "refclk", "timclk", "apb_pclk";
320 clock-output-names = "timerclk0",
324 assigned-clocks = <&sp810_syscon0 0>,
328 assigned-clock-parents = <&timclk>,
335 #address-cells = <1>;
337 compatible = "arm,versatile-i2c";
338 reg = <0x10002000 0x1000>;
341 compatible = "dallas,ds1338";
346 serial0: serial@10009000 {
347 compatible = "arm,pl011", "arm,primecell";
348 reg = <0x10009000 0x1000>;
349 clocks = <&uartclk>, <&pclk>;
350 clock-names = "uartclk", "apb_pclk";
353 serial1: serial@1000a000 {
354 compatible = "arm,pl011", "arm,primecell";
355 reg = <0x1000a000 0x1000>;
356 clocks = <&uartclk>, <&pclk>;
357 clock-names = "uartclk", "apb_pclk";
360 serial2: serial@1000b000 {
361 compatible = "arm,pl011", "arm,primecell";
362 reg = <0x1000b000 0x1000>;
363 clocks = <&uartclk>, <&pclk>;
364 clock-names = "uartclk", "apb_pclk";
368 compatible = "arm,pl022", "arm,primecell";
369 reg = <0x1000d000 0x1000>;
370 clocks = <&sspclk>, <&pclk>;
371 clock-names = "SSPCLK", "apb_pclk";
374 wdog0: watchdog@1000f000 {
375 compatible = "arm,sp805", "arm,primecell";
376 reg = <0x1000f000 0x1000>;
377 clocks = <&wdogclk>, <&pclk>;
378 clock-names = "wdogclk", "apb_pclk";
382 wdog1: watchdog@10010000 {
383 compatible = "arm,sp805", "arm,primecell";
384 reg = <0x10010000 0x1000>;
385 clocks = <&wdogclk>, <&pclk>;
386 clock-names = "wdogclk", "apb_pclk";
390 timer01: timer@10011000 {
391 compatible = "arm,sp804", "arm,primecell";
392 reg = <0x10011000 0x1000>;
393 clocks = <&sp810_syscon0 0>,
396 clock-names = "timerclk0",
401 timer23: timer@10012000 {
402 compatible = "arm,sp804", "arm,primecell";
403 reg = <0x10012000 0x1000>;
404 clocks = <&sp810_syscon0 2>,
407 clock-names = "timerclk2",
412 gpio0: gpio@10013000 {
413 compatible = "arm,pl061", "arm,primecell";
414 reg = <0x10013000 0x1000>;
417 interrupt-controller;
418 #interrupt-cells = <2>;
420 clock-names = "apb_pclk";
423 gpio1: gpio@10014000 {
424 compatible = "arm,pl061", "arm,primecell";
425 reg = <0x10014000 0x1000>;
428 interrupt-controller;
429 #interrupt-cells = <2>;
431 clock-names = "apb_pclk";
434 gpio2: gpio@10015000 {
435 compatible = "arm,pl061", "arm,primecell";
436 reg = <0x10015000 0x1000>;
439 interrupt-controller;
440 #interrupt-cells = <2>;
442 clock-names = "apb_pclk";
446 #address-cells = <1>;
448 compatible = "arm,versatile-i2c";
449 reg = <0x10016000 0x1000>;
453 compatible = "arm,pl031", "arm,primecell";
454 reg = <0x10017000 0x1000>;
456 clock-names = "apb_pclk";
459 timer45: timer@10018000 {
460 compatible = "arm,sp804", "arm,primecell";
461 reg = <0x10018000 0x1000>;
462 clocks = <&timclk>, <&timclk>, <&pclk>;
463 clock-names = "timerclk4", "timerclk5", "apb_pclk";
466 timer67: timer@10019000 {
467 compatible = "arm,sp804", "arm,primecell";
468 reg = <0x10019000 0x1000>;
469 clocks = <&timclk>, <&timclk>, <&pclk>;
470 clock-names = "timerclk6", "timerclk7", "apb_pclk";
473 sp810_syscon1: sysctl@1001a000 {
474 compatible = "arm,sp810", "arm,primecell";
475 reg = <0x1001a000 0x1000>;
476 clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>;
477 clock-names = "refclk", "timclk", "apb_pclk";
479 clock-output-names = "timerclk4",
483 assigned-clocks = <&sp810_syscon1 0>,
487 assigned-clock-parents = <&timclk>,
495 /* These peripherals are inside the FPGA */
497 #address-cells = <1>;
499 compatible = "simple-bus";
502 aaci: aaci@10004000 {
503 compatible = "arm,pl041", "arm,primecell";
504 reg = <0x10004000 0x1000>;
506 clock-names = "apb_pclk";
509 mmc: mmcsd@10005000 {
510 compatible = "arm,pl18x", "arm,primecell";
511 reg = <0x10005000 0x1000>;
513 /* Due to frequent FIFO overruns, use just 500 kHz */
514 max-frequency = <500000>;
518 clocks = <&mclk>, <&pclk>;
519 clock-names = "mclk", "apb_pclk";
520 vmmc-supply = <&vmmc>;
521 cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
522 wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
526 compatible = "arm,pl050", "arm,primecell";
527 reg = <0x10006000 0x1000>;
528 clocks = <&kmiclk>, <&pclk>;
529 clock-names = "KMIREFCLK", "apb_pclk";
533 compatible = "arm,pl050", "arm,primecell";
534 reg = <0x10007000 0x1000>;
535 clocks = <&kmiclk>, <&pclk>;
536 clock-names = "KMIREFCLK", "apb_pclk";
539 serial3: serial@1000c000 {
540 compatible = "arm,pl011", "arm,primecell";
541 reg = <0x1000c000 0x1000>;
542 clocks = <&uartclk>, <&pclk>;
543 clock-names = "uartclk", "apb_pclk";
547 /* These peripherals are inside the NEC ISSP */
549 #address-cells = <1>;
551 compatible = "simple-bus";
554 clcd: clcd@10020000 {
555 compatible = "arm,pl111", "arm,primecell";
556 reg = <0x10020000 0x1000>;
557 interrupt-names = "combined";
558 clocks = <&oscclk4>, <&pclk>;
559 clock-names = "clcdclk", "apb_pclk";
560 /* 1024x768 16bpp @65MHz works fine */
561 max-memory-bandwidth = <95000000>;
564 clcd_pads: endpoint {
565 remote-endpoint = <&vga_bridge_in>;
566 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;