1 // SPDX-License-Identifier: GPL-2.0+
2 #include <dt-bindings/clock/aspeed-clock.h>
6 compatible = "aspeed,ast2400";
9 interrupt-parent = <&vic>;
39 compatible = "arm,arm926ej-s";
46 device_type = "memory";
51 compatible = "simple-bus";
56 fmc: flash-controller@1e620000 {
57 reg = < 0x1e620000 0x94
58 0x20000000 0x10000000 >;
61 compatible = "aspeed,ast2400-fmc";
62 clocks = <&syscon ASPEED_CLK_AHB>;
67 compatible = "jedec,spi-nor";
72 spi: flash-controller@1e630000 {
73 reg = < 0x1e630000 0x18
74 0x30000000 0x10000000 >;
77 compatible = "aspeed,ast2400-spi";
78 clocks = <&syscon ASPEED_CLK_AHB>;
82 compatible = "jedec,spi-nor";
87 vic: interrupt-controller@1e6c0080 {
88 compatible = "aspeed,ast2400-vic";
90 #interrupt-cells = <1>;
91 valid-sources = <0xffffffff 0x0007ffff>;
92 reg = <0x1e6c0080 0x80>;
95 cvic: copro-interrupt-controller@1e6c2000 {
96 compatible = "aspeed,ast2400-cvic", "aspeed-cvic";
97 valid-sources = <0x7fffffff>;
98 reg = <0x1e6c2000 0x80>;
101 mac0: ethernet@1e660000 {
102 compatible = "aspeed,ast2400-mac", "faraday,ftgmac100";
103 reg = <0x1e660000 0x180>;
105 clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
109 mac1: ethernet@1e680000 {
110 compatible = "aspeed,ast2400-mac", "faraday,ftgmac100";
111 reg = <0x1e680000 0x180>;
113 clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
117 ehci0: usb@1e6a1000 {
118 compatible = "aspeed,ast2400-ehci", "generic-ehci";
119 reg = <0x1e6a1000 0x100>;
121 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
122 pinctrl-names = "default";
123 pinctrl-0 = <&pinctrl_usb2h_default>;
128 compatible = "aspeed,ast2400-uhci", "generic-uhci";
129 reg = <0x1e6b0000 0x100>;
132 clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>;
135 * No default pinmux, it will follow EHCI, use an explicit pinmux
136 * override if you don't enable EHCI
140 vhub: usb-vhub@1e6a0000 {
141 compatible = "aspeed,ast2400-usb-vhub";
142 reg = <0x1e6a0000 0x300>;
144 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
145 pinctrl-names = "default";
146 pinctrl-0 = <&pinctrl_usb2d_default>;
151 compatible = "simple-bus";
152 #address-cells = <1>;
156 syscon: syscon@1e6e2000 {
157 compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd";
158 reg = <0x1e6e2000 0x1a8>;
159 #address-cells = <1>;
165 compatible = "aspeed,g4-pinctrl";
170 rng: hwrng@1e6e2078 {
171 compatible = "timeriomem_rng";
172 reg = <0x1e6e2078 0x4>;
178 compatible = "aspeed,ast2400-adc";
179 reg = <0x1e6e9000 0xb0>;
180 clocks = <&syscon ASPEED_CLK_APB>;
181 resets = <&syscon ASPEED_RESET_ADC>;
182 #io-channel-cells = <1>;
186 sram: sram@1e720000 {
187 compatible = "mmio-sram";
188 reg = <0x1e720000 0x8000>; // 32K
191 gpio: gpio@1e780000 {
194 compatible = "aspeed,ast2400-gpio";
195 reg = <0x1e780000 0x1000>;
197 gpio-ranges = <&pinctrl 0 0 220>;
198 clocks = <&syscon ASPEED_CLK_APB>;
199 interrupt-controller;
202 timer: timer@1e782000 {
203 /* This timer is a Faraday FTTMR010 derivative */
204 compatible = "aspeed,ast2400-timer";
205 reg = <0x1e782000 0x90>;
206 interrupts = <16 17 18 35 36 37 38 39>;
207 clocks = <&syscon ASPEED_CLK_APB>;
208 clock-names = "PCLK";
211 uart1: serial@1e783000 {
212 compatible = "ns16550a";
213 reg = <0x1e783000 0x20>;
216 clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
217 resets = <&lpc_reset 4>;
222 uart5: serial@1e784000 {
223 compatible = "ns16550a";
224 reg = <0x1e784000 0x20>;
227 clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
232 wdt1: watchdog@1e785000 {
233 compatible = "aspeed,ast2400-wdt";
234 reg = <0x1e785000 0x1c>;
235 clocks = <&syscon ASPEED_CLK_APB>;
238 wdt2: watchdog@1e785020 {
239 compatible = "aspeed,ast2400-wdt";
240 reg = <0x1e785020 0x1c>;
241 clocks = <&syscon ASPEED_CLK_APB>;
244 pwm_tacho: pwm-tacho-controller@1e786000 {
245 compatible = "aspeed,ast2400-pwm-tacho";
246 #address-cells = <1>;
248 reg = <0x1e786000 0x1000>;
249 clocks = <&syscon ASPEED_CLK_24M>;
250 resets = <&syscon ASPEED_RESET_PWM>;
254 vuart: serial@1e787000 {
255 compatible = "aspeed,ast2400-vuart";
256 reg = <0x1e787000 0x40>;
259 clocks = <&syscon ASPEED_CLK_APB>;
265 compatible = "aspeed,ast2400-lpc", "simple-mfd";
266 reg = <0x1e789000 0x1000>;
268 #address-cells = <1>;
270 ranges = <0x0 0x1e789000 0x1000>;
273 compatible = "aspeed,ast2400-lpc-bmc";
277 lpc_host: lpc-host@80 {
278 compatible = "aspeed,ast2400-lpc-host", "simple-mfd", "syscon";
282 #address-cells = <1>;
284 ranges = <0x0 0x80 0x1e0>;
286 lpc_ctrl: lpc-ctrl@0 {
287 compatible = "aspeed,ast2400-lpc-ctrl";
289 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
293 lpc_snoop: lpc-snoop@0 {
294 compatible = "aspeed,ast2400-lpc-snoop";
301 compatible = "aspeed,ast2400-lhc";
302 reg = <0x20 0x24 0x48 0x8>;
305 lpc_reset: reset-controller@18 {
306 compatible = "aspeed,ast2400-lpc-reset";
312 compatible = "aspeed,ast2400-ibt-bmc";
320 uart2: serial@1e78d000 {
321 compatible = "ns16550a";
322 reg = <0x1e78d000 0x20>;
325 clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
326 resets = <&lpc_reset 5>;
331 uart3: serial@1e78e000 {
332 compatible = "ns16550a";
333 reg = <0x1e78e000 0x20>;
336 clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
337 resets = <&lpc_reset 6>;
342 uart4: serial@1e78f000 {
343 compatible = "ns16550a";
344 reg = <0x1e78f000 0x20>;
347 clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
348 resets = <&lpc_reset 7>;
354 compatible = "simple-bus";
355 #address-cells = <1>;
357 ranges = <0 0x1e78a000 0x1000>;
364 i2c_ic: interrupt-controller@0 {
365 #interrupt-cells = <1>;
366 compatible = "aspeed,ast2400-i2c-ic";
369 interrupt-controller;
373 #address-cells = <1>;
375 #interrupt-cells = <1>;
378 compatible = "aspeed,ast2400-i2c-bus";
379 clocks = <&syscon ASPEED_CLK_APB>;
380 resets = <&syscon ASPEED_RESET_I2C>;
381 bus-frequency = <100000>;
383 interrupt-parent = <&i2c_ic>;
385 /* Does not need pinctrl properties */
389 #address-cells = <1>;
391 #interrupt-cells = <1>;
394 compatible = "aspeed,ast2400-i2c-bus";
395 clocks = <&syscon ASPEED_CLK_APB>;
396 resets = <&syscon ASPEED_RESET_I2C>;
397 bus-frequency = <100000>;
399 interrupt-parent = <&i2c_ic>;
401 /* Does not need pinctrl properties */
405 #address-cells = <1>;
407 #interrupt-cells = <1>;
410 compatible = "aspeed,ast2400-i2c-bus";
411 clocks = <&syscon ASPEED_CLK_APB>;
412 resets = <&syscon ASPEED_RESET_I2C>;
413 bus-frequency = <100000>;
415 interrupt-parent = <&i2c_ic>;
416 pinctrl-names = "default";
417 pinctrl-0 = <&pinctrl_i2c3_default>;
422 #address-cells = <1>;
424 #interrupt-cells = <1>;
427 compatible = "aspeed,ast2400-i2c-bus";
428 clocks = <&syscon ASPEED_CLK_APB>;
429 resets = <&syscon ASPEED_RESET_I2C>;
430 bus-frequency = <100000>;
432 interrupt-parent = <&i2c_ic>;
433 pinctrl-names = "default";
434 pinctrl-0 = <&pinctrl_i2c4_default>;
439 #address-cells = <1>;
441 #interrupt-cells = <1>;
444 compatible = "aspeed,ast2400-i2c-bus";
445 clocks = <&syscon ASPEED_CLK_APB>;
446 resets = <&syscon ASPEED_RESET_I2C>;
447 bus-frequency = <100000>;
449 interrupt-parent = <&i2c_ic>;
450 pinctrl-names = "default";
451 pinctrl-0 = <&pinctrl_i2c5_default>;
456 #address-cells = <1>;
458 #interrupt-cells = <1>;
461 compatible = "aspeed,ast2400-i2c-bus";
462 clocks = <&syscon ASPEED_CLK_APB>;
463 resets = <&syscon ASPEED_RESET_I2C>;
464 bus-frequency = <100000>;
466 interrupt-parent = <&i2c_ic>;
467 pinctrl-names = "default";
468 pinctrl-0 = <&pinctrl_i2c6_default>;
473 #address-cells = <1>;
475 #interrupt-cells = <1>;
478 compatible = "aspeed,ast2400-i2c-bus";
479 clocks = <&syscon ASPEED_CLK_APB>;
480 resets = <&syscon ASPEED_RESET_I2C>;
481 bus-frequency = <100000>;
483 interrupt-parent = <&i2c_ic>;
484 pinctrl-names = "default";
485 pinctrl-0 = <&pinctrl_i2c7_default>;
490 #address-cells = <1>;
492 #interrupt-cells = <1>;
495 compatible = "aspeed,ast2400-i2c-bus";
496 clocks = <&syscon ASPEED_CLK_APB>;
497 resets = <&syscon ASPEED_RESET_I2C>;
498 bus-frequency = <100000>;
500 interrupt-parent = <&i2c_ic>;
501 pinctrl-names = "default";
502 pinctrl-0 = <&pinctrl_i2c8_default>;
507 #address-cells = <1>;
509 #interrupt-cells = <1>;
512 compatible = "aspeed,ast2400-i2c-bus";
513 clocks = <&syscon ASPEED_CLK_APB>;
514 resets = <&syscon ASPEED_RESET_I2C>;
515 bus-frequency = <100000>;
517 interrupt-parent = <&i2c_ic>;
518 pinctrl-names = "default";
519 pinctrl-0 = <&pinctrl_i2c9_default>;
524 #address-cells = <1>;
526 #interrupt-cells = <1>;
529 compatible = "aspeed,ast2400-i2c-bus";
530 clocks = <&syscon ASPEED_CLK_APB>;
531 resets = <&syscon ASPEED_RESET_I2C>;
532 bus-frequency = <100000>;
534 interrupt-parent = <&i2c_ic>;
535 pinctrl-names = "default";
536 pinctrl-0 = <&pinctrl_i2c10_default>;
541 #address-cells = <1>;
543 #interrupt-cells = <1>;
546 compatible = "aspeed,ast2400-i2c-bus";
547 clocks = <&syscon ASPEED_CLK_APB>;
548 resets = <&syscon ASPEED_RESET_I2C>;
549 bus-frequency = <100000>;
551 interrupt-parent = <&i2c_ic>;
552 pinctrl-names = "default";
553 pinctrl-0 = <&pinctrl_i2c11_default>;
558 #address-cells = <1>;
560 #interrupt-cells = <1>;
563 compatible = "aspeed,ast2400-i2c-bus";
564 clocks = <&syscon ASPEED_CLK_APB>;
565 resets = <&syscon ASPEED_RESET_I2C>;
566 bus-frequency = <100000>;
568 interrupt-parent = <&i2c_ic>;
569 pinctrl-names = "default";
570 pinctrl-0 = <&pinctrl_i2c12_default>;
575 #address-cells = <1>;
577 #interrupt-cells = <1>;
580 compatible = "aspeed,ast2400-i2c-bus";
581 clocks = <&syscon ASPEED_CLK_APB>;
582 resets = <&syscon ASPEED_RESET_I2C>;
583 bus-frequency = <100000>;
585 interrupt-parent = <&i2c_ic>;
586 pinctrl-names = "default";
587 pinctrl-0 = <&pinctrl_i2c13_default>;
592 #address-cells = <1>;
594 #interrupt-cells = <1>;
597 compatible = "aspeed,ast2400-i2c-bus";
598 clocks = <&syscon ASPEED_CLK_APB>;
599 resets = <&syscon ASPEED_RESET_I2C>;
600 bus-frequency = <100000>;
602 interrupt-parent = <&i2c_ic>;
603 pinctrl-names = "default";
604 pinctrl-0 = <&pinctrl_i2c14_default>;
610 pinctrl_acpi_default: acpi_default {
615 pinctrl_adc0_default: adc0_default {
620 pinctrl_adc1_default: adc1_default {
625 pinctrl_adc10_default: adc10_default {
630 pinctrl_adc11_default: adc11_default {
635 pinctrl_adc12_default: adc12_default {
640 pinctrl_adc13_default: adc13_default {
645 pinctrl_adc14_default: adc14_default {
650 pinctrl_adc15_default: adc15_default {
655 pinctrl_adc2_default: adc2_default {
660 pinctrl_adc3_default: adc3_default {
665 pinctrl_adc4_default: adc4_default {
670 pinctrl_adc5_default: adc5_default {
675 pinctrl_adc6_default: adc6_default {
680 pinctrl_adc7_default: adc7_default {
685 pinctrl_adc8_default: adc8_default {
690 pinctrl_adc9_default: adc9_default {
695 pinctrl_bmcint_default: bmcint_default {
700 pinctrl_ddcclk_default: ddcclk_default {
705 pinctrl_ddcdat_default: ddcdat_default {
710 pinctrl_extrst_default: extrst_default {
715 pinctrl_flack_default: flack_default {
720 pinctrl_flbusy_default: flbusy_default {
725 pinctrl_flwp_default: flwp_default {
730 pinctrl_gpid_default: gpid_default {
735 pinctrl_gpid0_default: gpid0_default {
740 pinctrl_gpid2_default: gpid2_default {
745 pinctrl_gpid4_default: gpid4_default {
750 pinctrl_gpid6_default: gpid6_default {
755 pinctrl_gpie0_default: gpie0_default {
760 pinctrl_gpie2_default: gpie2_default {
765 pinctrl_gpie4_default: gpie4_default {
770 pinctrl_gpie6_default: gpie6_default {
775 pinctrl_i2c10_default: i2c10_default {
780 pinctrl_i2c11_default: i2c11_default {
785 pinctrl_i2c12_default: i2c12_default {
790 pinctrl_i2c13_default: i2c13_default {
795 pinctrl_i2c14_default: i2c14_default {
800 pinctrl_i2c3_default: i2c3_default {
805 pinctrl_i2c4_default: i2c4_default {
810 pinctrl_i2c5_default: i2c5_default {
815 pinctrl_i2c6_default: i2c6_default {
820 pinctrl_i2c7_default: i2c7_default {
825 pinctrl_i2c8_default: i2c8_default {
830 pinctrl_i2c9_default: i2c9_default {
835 pinctrl_lpcpd_default: lpcpd_default {
840 pinctrl_lpcpme_default: lpcpme_default {
845 pinctrl_lpcrst_default: lpcrst_default {
850 pinctrl_lpcsmi_default: lpcsmi_default {
855 pinctrl_mac1link_default: mac1link_default {
856 function = "MAC1LINK";
860 pinctrl_mac2link_default: mac2link_default {
861 function = "MAC2LINK";
865 pinctrl_mdio1_default: mdio1_default {
870 pinctrl_mdio2_default: mdio2_default {
875 pinctrl_ncts1_default: ncts1_default {
880 pinctrl_ncts2_default: ncts2_default {
885 pinctrl_ncts3_default: ncts3_default {
890 pinctrl_ncts4_default: ncts4_default {
895 pinctrl_ndcd1_default: ndcd1_default {
900 pinctrl_ndcd2_default: ndcd2_default {
905 pinctrl_ndcd3_default: ndcd3_default {
910 pinctrl_ndcd4_default: ndcd4_default {
915 pinctrl_ndsr1_default: ndsr1_default {
920 pinctrl_ndsr2_default: ndsr2_default {
925 pinctrl_ndsr3_default: ndsr3_default {
930 pinctrl_ndsr4_default: ndsr4_default {
935 pinctrl_ndtr1_default: ndtr1_default {
940 pinctrl_ndtr2_default: ndtr2_default {
945 pinctrl_ndtr3_default: ndtr3_default {
950 pinctrl_ndtr4_default: ndtr4_default {
955 pinctrl_ndts4_default: ndts4_default {
960 pinctrl_nri1_default: nri1_default {
965 pinctrl_nri2_default: nri2_default {
970 pinctrl_nri3_default: nri3_default {
975 pinctrl_nri4_default: nri4_default {
980 pinctrl_nrts1_default: nrts1_default {
985 pinctrl_nrts2_default: nrts2_default {
990 pinctrl_nrts3_default: nrts3_default {
995 pinctrl_oscclk_default: oscclk_default {
1000 pinctrl_pwm0_default: pwm0_default {
1005 pinctrl_pwm1_default: pwm1_default {
1010 pinctrl_pwm2_default: pwm2_default {
1015 pinctrl_pwm3_default: pwm3_default {
1020 pinctrl_pwm4_default: pwm4_default {
1025 pinctrl_pwm5_default: pwm5_default {
1030 pinctrl_pwm6_default: pwm6_default {
1035 pinctrl_pwm7_default: pwm7_default {
1040 pinctrl_rgmii1_default: rgmii1_default {
1041 function = "RGMII1";
1045 pinctrl_rgmii2_default: rgmii2_default {
1046 function = "RGMII2";
1050 pinctrl_rmii1_default: rmii1_default {
1055 pinctrl_rmii2_default: rmii2_default {
1060 pinctrl_rom16_default: rom16_default {
1065 pinctrl_rom8_default: rom8_default {
1070 pinctrl_romcs1_default: romcs1_default {
1071 function = "ROMCS1";
1075 pinctrl_romcs2_default: romcs2_default {
1076 function = "ROMCS2";
1080 pinctrl_romcs3_default: romcs3_default {
1081 function = "ROMCS3";
1085 pinctrl_romcs4_default: romcs4_default {
1086 function = "ROMCS4";
1090 pinctrl_rxd1_default: rxd1_default {
1095 pinctrl_rxd2_default: rxd2_default {
1100 pinctrl_rxd3_default: rxd3_default {
1105 pinctrl_rxd4_default: rxd4_default {
1110 pinctrl_salt1_default: salt1_default {
1115 pinctrl_salt2_default: salt2_default {
1120 pinctrl_salt3_default: salt3_default {
1125 pinctrl_salt4_default: salt4_default {
1130 pinctrl_sd1_default: sd1_default {
1135 pinctrl_sd2_default: sd2_default {
1140 pinctrl_sgpmck_default: sgpmck_default {
1141 function = "SGPMCK";
1145 pinctrl_sgpmi_default: sgpmi_default {
1150 pinctrl_sgpmld_default: sgpmld_default {
1151 function = "SGPMLD";
1155 pinctrl_sgpmo_default: sgpmo_default {
1160 pinctrl_sgpsck_default: sgpsck_default {
1161 function = "SGPSCK";
1165 pinctrl_sgpsi0_default: sgpsi0_default {
1166 function = "SGPSI0";
1170 pinctrl_sgpsi1_default: sgpsi1_default {
1171 function = "SGPSI1";
1175 pinctrl_sgpsld_default: sgpsld_default {
1176 function = "SGPSLD";
1180 pinctrl_sioonctrl_default: sioonctrl_default {
1181 function = "SIOONCTRL";
1182 groups = "SIOONCTRL";
1185 pinctrl_siopbi_default: siopbi_default {
1186 function = "SIOPBI";
1190 pinctrl_siopbo_default: siopbo_default {
1191 function = "SIOPBO";
1195 pinctrl_siopwreq_default: siopwreq_default {
1196 function = "SIOPWREQ";
1197 groups = "SIOPWREQ";
1200 pinctrl_siopwrgd_default: siopwrgd_default {
1201 function = "SIOPWRGD";
1202 groups = "SIOPWRGD";
1205 pinctrl_sios3_default: sios3_default {
1210 pinctrl_sios5_default: sios5_default {
1215 pinctrl_siosci_default: siosci_default {
1216 function = "SIOSCI";
1220 pinctrl_spi1_default: spi1_default {
1225 pinctrl_spi1debug_default: spi1debug_default {
1226 function = "SPI1DEBUG";
1227 groups = "SPI1DEBUG";
1230 pinctrl_spi1passthru_default: spi1passthru_default {
1231 function = "SPI1PASSTHRU";
1232 groups = "SPI1PASSTHRU";
1235 pinctrl_spics1_default: spics1_default {
1236 function = "SPICS1";
1240 pinctrl_timer3_default: timer3_default {
1241 function = "TIMER3";
1245 pinctrl_timer4_default: timer4_default {
1246 function = "TIMER4";
1250 pinctrl_timer5_default: timer5_default {
1251 function = "TIMER5";
1255 pinctrl_timer6_default: timer6_default {
1256 function = "TIMER6";
1260 pinctrl_timer7_default: timer7_default {
1261 function = "TIMER7";
1265 pinctrl_timer8_default: timer8_default {
1266 function = "TIMER8";
1270 pinctrl_txd1_default: txd1_default {
1275 pinctrl_txd2_default: txd2_default {
1280 pinctrl_txd3_default: txd3_default {
1285 pinctrl_txd4_default: txd4_default {
1290 pinctrl_uart6_default: uart6_default {
1295 pinctrl_usbcki_default: usbcki_default {
1296 function = "USBCKI";
1300 pinctrl_usb2h_default: usb2h_default {
1301 function = "USB2H1";
1305 pinctrl_usb2d_default: usb2d_default {
1306 function = "USB2D1";
1310 pinctrl_vgabios_rom_default: vgabios_rom_default {
1311 function = "VGABIOS_ROM";
1312 groups = "VGABIOS_ROM";
1315 pinctrl_vgahs_default: vgahs_default {
1320 pinctrl_vgavs_default: vgavs_default {
1325 pinctrl_vpi18_default: vpi18_default {
1330 pinctrl_vpi24_default: vpi24_default {
1335 pinctrl_vpi30_default: vpi30_default {
1340 pinctrl_vpo12_default: vpo12_default {
1345 pinctrl_vpo24_default: vpo24_default {
1350 pinctrl_wdtrst1_default: wdtrst1_default {
1351 function = "WDTRST1";
1355 pinctrl_wdtrst2_default: wdtrst2_default {
1356 function = "WDTRST2";