1 #include <dt-bindings/pinctrl/bcm2835.h>
2 #include <dt-bindings/clock/bcm2835.h>
3 #include <dt-bindings/clock/bcm2835-aux.h>
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/interrupt-controller/irq.h>
7 /* firmware-provided startup stubs live here, where the secondary CPUs are
10 /memreserve/ 0x00000000 0x00001000;
12 /* This include file covers the common peripherals and configuration between
13 * bcm2835 and bcm2836 implementations, leaving the CPU configuration to
14 * bcm2835.dtsi and bcm2836.dtsi.
18 compatible = "brcm,bcm2835";
20 interrupt-parent = <&intc>;
30 stdout-path = "serial0:115200n8";
34 cpu_thermal: cpu-thermal {
35 polling-delay-passive = <0>;
36 polling-delay = <1000>;
38 thermal-sensors = <&thermal>;
42 temperature = <80000>;
54 compatible = "simple-bus";
59 compatible = "brcm,bcm2835-system-timer";
60 reg = <0x7e003000 0x1000>;
61 interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
62 /* This could be a reference to BCM2835_CLOCK_TIMER,
63 * but we don't have the driver using the common clock
66 clock-frequency = <1000000>;
70 compatible = "brcm,bcm2835-dma";
71 reg = <0x7e007000 0xf00>;
83 /* dma channel 11-14 share one irq */
88 /* unused shared irq for all channels */
90 interrupt-names = "dma0",
107 brcm,dma-channel-mask = <0x7f35>;
110 intc: interrupt-controller@7e00b200 {
111 compatible = "brcm,bcm2835-armctrl-ic";
112 reg = <0x7e00b200 0x200>;
113 interrupt-controller;
114 #interrupt-cells = <2>;
118 compatible = "brcm,bcm2835-pm-wdt";
119 reg = <0x7e100000 0x28>;
122 clocks: cprman@7e101000 {
123 compatible = "brcm,bcm2835-cprman";
125 reg = <0x7e101000 0x2000>;
127 /* CPRMAN derives almost everything from the
128 * platform's oscillator. However, the DSI
129 * pixel clocks come from the DSI analog PHY.
132 <&dsi0 0>, <&dsi0 1>, <&dsi0 2>,
133 <&dsi1 0>, <&dsi1 1>, <&dsi1 2>;
137 compatible = "brcm,bcm2835-rng";
138 reg = <0x7e104000 0x10>;
141 mailbox: mailbox@7e00b880 {
142 compatible = "brcm,bcm2835-mbox";
143 reg = <0x7e00b880 0x40>;
148 gpio: gpio@7e200000 {
149 compatible = "brcm,bcm2835-gpio";
150 reg = <0x7e200000 0xb4>;
152 * The GPIO IP block is designed for 3 banks of GPIOs.
153 * Each bank has a GPIO interrupt for itself.
154 * There is an overall "any bank" interrupt.
155 * In order, these are GIC interrupts 17, 18, 19, 20.
156 * Since the BCM2835 only has 2 banks, the 2nd bank
157 * interrupt output appears to be mirrored onto the
158 * 3rd bank's interrupt signal.
159 * So, a bank0 interrupt shows up on 17, 20, and
160 * a bank1 interrupt shows up on 18, 19, 20!
162 interrupts = <2 17>, <2 18>, <2 19>, <2 20>;
167 interrupt-controller;
168 #interrupt-cells = <2>;
170 /* Defines pin muxing groups according to
171 * BCM2835-ARM-Peripherals.pdf page 102.
173 * While each pin can have its mux selected
174 * for various functions individually, some
175 * groups only make sense to switch to a
176 * particular function together.
178 dpi_gpio0: dpi_gpio0 {
179 brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11
180 12 13 14 15 16 17 18 19
181 20 21 22 23 24 25 26 27>;
182 brcm,function = <BCM2835_FSEL_ALT2>;
184 emmc_gpio22: emmc_gpio22 {
185 brcm,pins = <22 23 24 25 26 27>;
186 brcm,function = <BCM2835_FSEL_ALT3>;
188 emmc_gpio34: emmc_gpio34 {
189 brcm,pins = <34 35 36 37 38 39>;
190 brcm,function = <BCM2835_FSEL_ALT3>;
191 brcm,pull = <BCM2835_PUD_OFF
198 emmc_gpio48: emmc_gpio48 {
199 brcm,pins = <48 49 50 51 52 53>;
200 brcm,function = <BCM2835_FSEL_ALT3>;
203 gpclk0_gpio4: gpclk0_gpio4 {
205 brcm,function = <BCM2835_FSEL_ALT0>;
207 gpclk1_gpio5: gpclk1_gpio5 {
209 brcm,function = <BCM2835_FSEL_ALT0>;
211 gpclk1_gpio42: gpclk1_gpio42 {
213 brcm,function = <BCM2835_FSEL_ALT0>;
215 gpclk1_gpio44: gpclk1_gpio44 {
217 brcm,function = <BCM2835_FSEL_ALT0>;
219 gpclk2_gpio6: gpclk2_gpio6 {
221 brcm,function = <BCM2835_FSEL_ALT0>;
223 gpclk2_gpio43: gpclk2_gpio43 {
225 brcm,function = <BCM2835_FSEL_ALT0>;
226 brcm,pull = <BCM2835_PUD_OFF>;
229 i2c0_gpio0: i2c0_gpio0 {
231 brcm,function = <BCM2835_FSEL_ALT0>;
233 i2c0_gpio28: i2c0_gpio28 {
235 brcm,function = <BCM2835_FSEL_ALT0>;
237 i2c0_gpio44: i2c0_gpio44 {
239 brcm,function = <BCM2835_FSEL_ALT1>;
241 i2c1_gpio2: i2c1_gpio2 {
243 brcm,function = <BCM2835_FSEL_ALT0>;
245 i2c1_gpio44: i2c1_gpio44 {
247 brcm,function = <BCM2835_FSEL_ALT2>;
249 i2c_slave_gpio18: i2c_slave_gpio18 {
250 brcm,pins = <18 19 20 21>;
251 brcm,function = <BCM2835_FSEL_ALT3>;
254 jtag_gpio4: jtag_gpio4 {
255 brcm,pins = <4 5 6 12 13>;
256 brcm,function = <BCM2835_FSEL_ALT5>;
258 jtag_gpio22: jtag_gpio22 {
259 brcm,pins = <22 23 24 25 26 27>;
260 brcm,function = <BCM2835_FSEL_ALT4>;
263 pcm_gpio18: pcm_gpio18 {
264 brcm,pins = <18 19 20 21>;
265 brcm,function = <BCM2835_FSEL_ALT0>;
267 pcm_gpio28: pcm_gpio28 {
268 brcm,pins = <28 29 30 31>;
269 brcm,function = <BCM2835_FSEL_ALT2>;
272 pwm0_gpio12: pwm0_gpio12 {
274 brcm,function = <BCM2835_FSEL_ALT0>;
276 pwm0_gpio18: pwm0_gpio18 {
278 brcm,function = <BCM2835_FSEL_ALT5>;
280 pwm0_gpio40: pwm0_gpio40 {
282 brcm,function = <BCM2835_FSEL_ALT0>;
284 pwm1_gpio13: pwm1_gpio13 {
286 brcm,function = <BCM2835_FSEL_ALT0>;
288 pwm1_gpio19: pwm1_gpio19 {
290 brcm,function = <BCM2835_FSEL_ALT5>;
292 pwm1_gpio41: pwm1_gpio41 {
294 brcm,function = <BCM2835_FSEL_ALT0>;
296 pwm1_gpio45: pwm1_gpio45 {
298 brcm,function = <BCM2835_FSEL_ALT0>;
301 sdhost_gpio48: sdhost_gpio48 {
302 brcm,pins = <48 49 50 51 52 53>;
303 brcm,function = <BCM2835_FSEL_ALT0>;
306 spi0_gpio7: spi0_gpio7 {
307 brcm,pins = <7 8 9 10 11>;
308 brcm,function = <BCM2835_FSEL_ALT0>;
310 spi0_gpio35: spi0_gpio35 {
311 brcm,pins = <35 36 37 38 39>;
312 brcm,function = <BCM2835_FSEL_ALT0>;
314 spi1_gpio16: spi1_gpio16 {
315 brcm,pins = <16 17 18 19 20 21>;
316 brcm,function = <BCM2835_FSEL_ALT4>;
318 spi2_gpio40: spi2_gpio40 {
319 brcm,pins = <40 41 42 43 44 45>;
320 brcm,function = <BCM2835_FSEL_ALT4>;
323 uart0_gpio14: uart0_gpio14 {
325 brcm,function = <BCM2835_FSEL_ALT0>;
327 /* Separate from the uart0_gpio14 group
328 * because it conflicts with spi1_gpio16, and
329 * people often run uart0 on the two pins
330 * without flow control.
332 uart0_ctsrts_gpio16: uart0_ctsrts_gpio16 {
334 brcm,function = <BCM2835_FSEL_ALT3>;
336 uart0_ctsrts_gpio30: uart0_ctsrts_gpio30 {
338 brcm,function = <BCM2835_FSEL_ALT3>;
339 brcm,pull = <BCM2835_PUD_UP BCM2835_PUD_OFF>;
341 uart0_gpio32: uart0_gpio32 {
343 brcm,function = <BCM2835_FSEL_ALT3>;
344 brcm,pull = <BCM2835_PUD_OFF BCM2835_PUD_UP>;
346 uart0_gpio36: uart0_gpio36 {
348 brcm,function = <BCM2835_FSEL_ALT2>;
350 uart0_ctsrts_gpio38: uart0_ctsrts_gpio38 {
352 brcm,function = <BCM2835_FSEL_ALT2>;
355 uart1_gpio14: uart1_gpio14 {
357 brcm,function = <BCM2835_FSEL_ALT5>;
359 uart1_ctsrts_gpio16: uart1_ctsrts_gpio16 {
361 brcm,function = <BCM2835_FSEL_ALT5>;
363 uart1_gpio32: uart1_gpio32 {
365 brcm,function = <BCM2835_FSEL_ALT5>;
367 uart1_ctsrts_gpio30: uart1_ctsrts_gpio30 {
369 brcm,function = <BCM2835_FSEL_ALT5>;
371 uart1_gpio40: uart1_gpio40 {
373 brcm,function = <BCM2835_FSEL_ALT5>;
375 uart1_ctsrts_gpio42: uart1_ctsrts_gpio42 {
377 brcm,function = <BCM2835_FSEL_ALT5>;
381 uart0: serial@7e201000 {
382 compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
383 reg = <0x7e201000 0x1000>;
385 clocks = <&clocks BCM2835_CLOCK_UART>,
386 <&clocks BCM2835_CLOCK_VPU>;
387 clock-names = "uartclk", "apb_pclk";
388 arm,primecell-periphid = <0x00241011>;
391 sdhost: mmc@7e202000 {
392 compatible = "brcm,bcm2835-sdhost";
393 reg = <0x7e202000 0x100>;
395 clocks = <&clocks BCM2835_CLOCK_VPU>;
402 compatible = "brcm,bcm2835-i2s";
403 reg = <0x7e203000 0x24>;
404 clocks = <&clocks BCM2835_CLOCK_PCM>;
408 dma-names = "tx", "rx";
413 compatible = "brcm,bcm2835-spi";
414 reg = <0x7e204000 0x1000>;
416 clocks = <&clocks BCM2835_CLOCK_VPU>;
417 #address-cells = <1>;
423 compatible = "brcm,bcm2835-i2c";
424 reg = <0x7e205000 0x1000>;
426 clocks = <&clocks BCM2835_CLOCK_VPU>;
427 #address-cells = <1>;
432 pixelvalve@7e206000 {
433 compatible = "brcm,bcm2835-pixelvalve0";
434 reg = <0x7e206000 0x100>;
435 interrupts = <2 13>; /* pwa0 */
438 pixelvalve@7e207000 {
439 compatible = "brcm,bcm2835-pixelvalve1";
440 reg = <0x7e207000 0x100>;
441 interrupts = <2 14>; /* pwa1 */
445 compatible = "brcm,bcm2835-dpi";
446 reg = <0x7e208000 0x8c>;
447 clocks = <&clocks BCM2835_CLOCK_VPU>,
448 <&clocks BCM2835_CLOCK_DPI>;
449 clock-names = "core", "pixel";
450 #address-cells = <1>;
456 compatible = "brcm,bcm2835-dsi0";
457 reg = <0x7e209000 0x78>;
459 #address-cells = <1>;
463 clocks = <&clocks BCM2835_PLLA_DSI0>,
464 <&clocks BCM2835_CLOCK_DSI0E>,
465 <&clocks BCM2835_CLOCK_DSI0P>;
466 clock-names = "phy", "escape", "pixel";
468 clock-output-names = "dsi0_byte",
474 thermal: thermal@7e212000 {
475 compatible = "brcm,bcm2835-thermal";
476 reg = <0x7e212000 0x8>;
477 clocks = <&clocks BCM2835_CLOCK_TSENS>;
478 #thermal-sensor-cells = <0>;
483 compatible = "brcm,bcm2835-aux";
485 reg = <0x7e215000 0x8>;
486 clocks = <&clocks BCM2835_CLOCK_VPU>;
489 uart1: serial@7e215040 {
490 compatible = "brcm,bcm2835-aux-uart";
491 reg = <0x7e215040 0x40>;
493 clocks = <&aux BCM2835_AUX_CLOCK_UART>;
498 compatible = "brcm,bcm2835-aux-spi";
499 reg = <0x7e215080 0x40>;
501 clocks = <&aux BCM2835_AUX_CLOCK_SPI1>;
502 #address-cells = <1>;
508 compatible = "brcm,bcm2835-aux-spi";
509 reg = <0x7e2150c0 0x40>;
511 clocks = <&aux BCM2835_AUX_CLOCK_SPI2>;
512 #address-cells = <1>;
518 compatible = "brcm,bcm2835-pwm";
519 reg = <0x7e20c000 0x28>;
520 clocks = <&clocks BCM2835_CLOCK_PWM>;
521 assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
522 assigned-clock-rates = <10000000>;
527 sdhci: sdhci@7e300000 {
528 compatible = "brcm,bcm2835-sdhci";
529 reg = <0x7e300000 0x100>;
531 clocks = <&clocks BCM2835_CLOCK_EMMC>;
536 compatible = "brcm,bcm2835-hvs";
537 reg = <0x7e400000 0x6000>;
542 compatible = "brcm,bcm2835-dsi1";
543 reg = <0x7e700000 0x8c>;
545 #address-cells = <1>;
549 clocks = <&clocks BCM2835_PLLD_DSI1>,
550 <&clocks BCM2835_CLOCK_DSI1E>,
551 <&clocks BCM2835_CLOCK_DSI1P>;
552 clock-names = "phy", "escape", "pixel";
554 clock-output-names = "dsi1_byte",
562 compatible = "brcm,bcm2835-i2c";
563 reg = <0x7e804000 0x1000>;
565 clocks = <&clocks BCM2835_CLOCK_VPU>;
566 #address-cells = <1>;
572 compatible = "brcm,bcm2835-i2c";
573 reg = <0x7e805000 0x1000>;
575 clocks = <&clocks BCM2835_CLOCK_VPU>;
576 #address-cells = <1>;
582 compatible = "brcm,bcm2835-vec";
583 reg = <0x7e806000 0x1000>;
584 clocks = <&clocks BCM2835_CLOCK_VEC>;
589 pixelvalve@7e807000 {
590 compatible = "brcm,bcm2835-pixelvalve2";
591 reg = <0x7e807000 0x100>;
592 interrupts = <2 10>; /* pixelvalve */
595 hdmi: hdmi@7e902000 {
596 compatible = "brcm,bcm2835-hdmi";
597 reg = <0x7e902000 0x600>,
599 interrupts = <2 8>, <2 9>;
601 clocks = <&clocks BCM2835_PLLH_PIX>,
602 <&clocks BCM2835_CLOCK_HSM>;
603 clock-names = "pixel", "hdmi";
605 dma-names = "audio-rx";
610 compatible = "brcm,bcm2835-usb";
611 reg = <0x7e980000 0x10000>;
613 #address-cells = <1>;
618 phy-names = "usb2-phy";
622 compatible = "brcm,bcm2835-v3d";
623 reg = <0x7ec00000 0x1000>;
628 compatible = "brcm,bcm2835-vc4";
633 compatible = "simple-bus";
634 #address-cells = <1>;
637 /* The oscillator is the root of the clock tree. */
639 compatible = "fixed-clock";
642 clock-output-names = "osc";
643 clock-frequency = <19200000>;
647 compatible = "fixed-clock";
650 clock-output-names = "otg";
651 clock-frequency = <480000000>;
656 compatible = "usb-nop-xceiv";