sys/gnu/dts/arm/dra72-evm-common.dtsi

   1 /*
   2  * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8 /dts-v1/;
   9
  10 #include "dra72x.dtsi"
  11 #include <dt-bindings/gpio/gpio.h>
  12 #include <dt-bindings/clk/ti-dra7-atl.h>
  13
  14 / {
  15         compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
  16
  17         aliases {
  18                 display0 = &hdmi0;
  19         };
  20
  21         evm_12v0: fixedregulator-evm12v0 {
  22                 /* main supply */
  23                 compatible = "regulator-fixed";
  24                 regulator-name = "evm_12v0";
  25                 regulator-min-microvolt = <12000000>;
  26                 regulator-max-microvolt = <12000000>;
  27                 regulator-always-on;
  28                 regulator-boot-on;
  29         };
  30
  31         evm_5v0: fixedregulator-evm5v0 {
  32                 /* Output 1 of TPS43351QDAPRQ1 on dra72-evm */
  33                 /* Output 1 of LM5140QRWGTQ1 on dra71-evm */
  34                 compatible = "regulator-fixed";
  35                 regulator-name = "evm_5v0";
  36                 regulator-min-microvolt = <5000000>;
  37                 regulator-max-microvolt = <5000000>;
  38                 vin-supply = <&evm_12v0>;
  39                 regulator-always-on;
  40                 regulator-boot-on;
  41         };
  42
  43         vsys_3v3: fixedregulator-vsys3v3 {
  44                 /* Output 2 of TPS43351QDAPRQ1 on dra72-evm */
  45                 /* Output 2 of LM5140QRWGTQ1 on dra71-evm */
  46                 compatible = "regulator-fixed";
  47                 regulator-name = "vsys_3v3";
  48                 regulator-min-microvolt = <3300000>;
  49                 regulator-max-microvolt = <3300000>;
  50                 vin-supply = <&evm_12v0>;
  51                 regulator-always-on;
  52                 regulator-boot-on;
  53         };
  54
  55         evm_3v3_sw: fixedregulator-evm_3v3 {
  56                 /* TPS22965DSG */
  57                 compatible = "regulator-fixed";
  58                 regulator-name = "evm_3v3";
  59                 regulator-min-microvolt = <3300000>;
  60                 regulator-max-microvolt = <3300000>;
  61                 vin-supply = <&vsys_3v3>;
  62                 regulator-always-on;
  63                 regulator-boot-on;
  64         };
  65
  66         aic_dvdd: fixedregulator-aic_dvdd {
  67                 /* TPS77018DBVT */
  68                 compatible = "regulator-fixed";
  69                 regulator-name = "aic_dvdd";
  70                 vin-supply = <&evm_3v3_sw>;
  71                 regulator-min-microvolt = <1800000>;
  72                 regulator-max-microvolt = <1800000>;
  73         };
  74
  75         evm_3v3_sd: fixedregulator-sd {
  76                 compatible = "regulator-fixed";
  77                 regulator-name = "evm_3v3_sd";
  78                 regulator-min-microvolt = <3300000>;
  79                 regulator-max-microvolt = <3300000>;
  80                 vin-supply = <&evm_3v3_sw>;
  81                 enable-active-high;
  82                 gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
  83         };
  84
  85         extcon_usb1: extcon_usb1 {
  86                 compatible = "linux,extcon-usb-gpio";
  87                 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
  88         };
  89
  90         extcon_usb2: extcon_usb2 {
  91                 compatible = "linux,extcon-usb-gpio";
  92                 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
  93         };
  94
  95         hdmi0: connector {
  96                 compatible = "hdmi-connector";
  97                 label = "hdmi";
  98
  99                 type = "a";
 100
 101                 port {
 102                         hdmi_connector_in: endpoint {
 103                                 remote-endpoint = <&tpd12s015_out>;
 104                         };
 105                 };
 106         };
 107
 108         tpd12s015: encoder {
 109                 compatible = "ti,tpd12s015";
 110
 111                 gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */
 112                         <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */
 113                         <&gpio7 12 GPIO_ACTIVE_HIGH>;   /* gpio7_12/sp1_cs2, HPD */
 114
 115                 ports {
 116                         #address-cells = <1>;
 117                         #size-cells = <0>;
 118
 119                         port@0 {
 120                                 reg = <0>;
 121
 122                                 tpd12s015_in: endpoint {
 123                                         remote-endpoint = <&hdmi_out>;
 124                                 };
 125                         };
 126
 127                         port@1 {
 128                                 reg = <1>;
 129
 130                                 tpd12s015_out: endpoint {
 131                                         remote-endpoint = <&hdmi_connector_in>;
 132                                 };
 133                         };
 134                 };
 135         };
 136
 137         sound0: sound0 {
 138                 compatible = "simple-audio-card";
 139                 simple-audio-card,name = "DRA7xx-EVM";
 140                 simple-audio-card,widgets =
 141                         "Headphone", "Headphone Jack",
 142                         "Line", "Line Out",
 143                         "Microphone", "Mic Jack",
 144                         "Line", "Line In";
 145                 simple-audio-card,routing =
 146                         "Headphone Jack",       "HPLOUT",
 147                         "Headphone Jack",       "HPROUT",
 148                         "Line Out",             "LLOUT",
 149                         "Line Out",             "RLOUT",
 150                         "MIC3L",                "Mic Jack",
 151                         "MIC3R",                "Mic Jack",
 152                         "Mic Jack",             "Mic Bias",
 153                         "LINE1L",               "Line In",
 154                         "LINE1R",               "Line In";
 155                 simple-audio-card,format = "dsp_b";
 156                 simple-audio-card,bitclock-master = <&sound0_master>;
 157                 simple-audio-card,frame-master = <&sound0_master>;
 158                 simple-audio-card,bitclock-inversion;
 159
 160                 sound0_master: simple-audio-card,cpu {
 161                         sound-dai = <&mcasp3>;
 162                         system-clock-frequency = <5644800>;
 163                 };
 164
 165                 simple-audio-card,codec {
 166                         sound-dai = <&tlv320aic3106>;
 167                         clocks = <&atl_clkin2_ck>;
 168                 };
 169         };
 170 };
 171
 172 &dra7_pmx_core {
 173         mmc1_pins_default: mmc1_pins_default {
 174                 pinctrl-single,pins = <
 175                         DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14)       /* mmc1sdcd.gpio219 */
 176                         DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
 177                         DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
 178                         DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
 179                         DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
 180                         DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
 181                         DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
 182                 >;
 183         };
 184
 185         mmc2_pins_default: mmc2_pins_default {
 186                 pinctrl-single,pins = <
 187                         DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
 188                         DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
 189                         DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
 190                         DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
 191                         DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
 192                         DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
 193                         DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
 194                         DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
 195                         DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
 196                         DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
 197                 >;
 198         };
 199
 200         dcan1_pins_default: dcan1_pins_default {
 201                 pinctrl-single,pins = <
 202                         DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
 203                         DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1)  /* wakeup0.dcan1_rx */
 204                 >;
 205         };
 206
 207         dcan1_pins_sleep: dcan1_pins_sleep {
 208                 pinctrl-single,pins = <
 209                         DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
 210                         DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */
 211                 >;
 212         };
 213 };
 214
 215 &i2c1 {
 216         status = "okay";
 217         clock-frequency = <400000>;
 218
 219         pcf_gpio_21: gpio@21 {
 220                 compatible = "ti,pcf8575", "nxp,pcf8575";
 221                 reg = <0x21>;
 222                 lines-initial-states = <0x1408>;
 223                 gpio-controller;
 224                 #gpio-cells = <2>;
 225                 interrupt-controller;
 226                 #interrupt-cells = <2>;
 227         };
 228
 229         tlv320aic3106: tlv320aic3106@19 {
 230                 #sound-dai-cells = <0>;
 231                 compatible = "ti,tlv320aic3106";
 232                 reg = <0x19>;
 233                 adc-settle-ms = <40>;
 234                 ai3x-micbias-vg = <1>;          /* 2.0V */
 235                 status = "okay";
 236
 237                 /* Regulators */
 238                 AVDD-supply = <&evm_3v3_sw>;
 239                 IOVDD-supply = <&evm_3v3_sw>;
 240                 DRVDD-supply = <&evm_3v3_sw>;
 241                 DVDD-supply = <&aic_dvdd>;
 242         };
 243 };
 244
 245 &i2c5 {
 246         status = "okay";
 247         clock-frequency = <400000>;
 248
 249         pcf_hdmi: pcf8575@26 {
 250                 compatible = "ti,pcf8575", "nxp,pcf8575";
 251                 reg = <0x26>;
 252                 gpio-controller;
 253                 #gpio-cells = <2>;
 254                 /*
 255                  * initial state is used here to keep the mdio interface
 256                  * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and
 257                  * VIN2_S0 driven high otherwise Ethernet stops working
 258                  * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6
 259                  */
 260                 lines-initial-states = <0x0f2b>;
 261
 262                 p1 {
 263                         /* vin6_sel_s0: high: VIN6, low: audio */
 264                         gpio-hog;
 265                         gpios = <1 GPIO_ACTIVE_HIGH>;
 266                         output-low;
 267                         line-name = "vin6_sel_s0";
 268                 };
 269         };
 270 };
 271
 272 &uart1 {
 273         status = "okay";
 274         interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
 275                               <&dra7_pmx_core 0x3e0>;
 276 };
 277
 278 &elm {
 279         status = "okay";
 280 };
 281
 282 &gpmc {
 283         status = "okay";
 284         ranges = <0 0 0x08000000 0x01000000>;   /* minimum GPMC partition = 16MB */
 285         nand@0,0 {
 286                 /* To use NAND, DIP switch SW5 must be set like so:
 287                  * SW5.1 (NAND_SELn) = ON (LOW)
 288                  * SW5.9 (GPMC_WPN) = OFF (HIGH)
 289                  */
 290                 compatible = "ti,omap2-nand";
 291                 reg = <0 0 4>;          /* device IO registers */
 292                 interrupt-parent = <&gpmc>;
 293                 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
 294                              <1 IRQ_TYPE_NONE>; /* termcount */
 295                 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
 296                 ti,nand-ecc-opt = "bch8";
 297                 ti,elm-id = <&elm>;
 298                 nand-bus-width = <16>;
 299                 gpmc,device-width = <2>;
 300                 gpmc,sync-clk-ps = <0>;
 301                 gpmc,cs-on-ns = <0>;
 302                 gpmc,cs-rd-off-ns = <80>;
 303                 gpmc,cs-wr-off-ns = <80>;
 304                 gpmc,adv-on-ns = <0>;
 305                 gpmc,adv-rd-off-ns = <60>;
 306                 gpmc,adv-wr-off-ns = <60>;
 307                 gpmc,we-on-ns = <10>;
 308                 gpmc,we-off-ns = <50>;
 309                 gpmc,oe-on-ns = <4>;
 310                 gpmc,oe-off-ns = <40>;
 311                 gpmc,access-ns = <40>;
 312                 gpmc,wr-access-ns = <80>;
 313                 gpmc,rd-cycle-ns = <80>;
 314                 gpmc,wr-cycle-ns = <80>;
 315                 gpmc,bus-turnaround-ns = <0>;
 316                 gpmc,cycle2cycle-delay-ns = <0>;
 317                 gpmc,clk-activation-ns = <0>;
 318                 gpmc,wr-data-mux-bus-ns = <0>;
 319                 /* MTD partition table */
 320                 /* All SPL-* partitions are sized to minimal length
 321                  * which can be independently programmable. For
 322                  * NAND flash this is equal to size of erase-block */
 323                 #address-cells = <1>;
 324                 #size-cells = <1>;
 325                 partition@0 {
 326                         label = "NAND.SPL";
 327                         reg = <0x00000000 0x000020000>;
 328                 };
 329                 partition@1 {
 330                         label = "NAND.SPL.backup1";
 331                         reg = <0x00020000 0x00020000>;
 332                 };
 333                 partition@2 {
 334                         label = "NAND.SPL.backup2";
 335                         reg = <0x00040000 0x00020000>;
 336                 };
 337                 partition@3 {
 338                         label = "NAND.SPL.backup3";
 339                         reg = <0x00060000 0x00020000>;
 340                 };
 341                 partition@4 {
 342                         label = "NAND.u-boot-spl-os";
 343                         reg = <0x00080000 0x00040000>;
 344                 };
 345                 partition@5 {
 346                         label = "NAND.u-boot";
 347                         reg = <0x000c0000 0x00100000>;
 348                 };
 349                 partition@6 {
 350                         label = "NAND.u-boot-env";
 351                         reg = <0x001c0000 0x00020000>;
 352                 };
 353                 partition@7 {
 354                         label = "NAND.u-boot-env.backup1";
 355                         reg = <0x001e0000 0x00020000>;
 356                 };
 357                 partition@8 {
 358                         label = "NAND.kernel";
 359                         reg = <0x00200000 0x00800000>;
 360                 };
 361                 partition@9 {
 362                         label = "NAND.file-system";
 363                         reg = <0x00a00000 0x0f600000>;
 364                 };
 365         };
 366 };
 367
 368 &omap_dwc3_1 {
 369         extcon = <&extcon_usb1>;
 370 };
 371
 372 &omap_dwc3_2 {
 373         extcon = <&extcon_usb2>;
 374 };
 375
 376 &usb1 {
 377         dr_mode = "peripheral";
 378 };
 379
 380 &usb2 {
 381         dr_mode = "host";
 382 };
 383
 384 &mmc1 {
 385         status = "okay";
 386         pinctrl-names = "default";
 387         pinctrl-0 = <&mmc1_pins_default>;
 388         vmmc-supply = <&evm_3v3_sd>;
 389         bus-width = <4>;
 390         /*
 391          * SDCD signal is not being used here - using the fact that GPIO mode
 392          * is a viable alternative
 393          */
 394         cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
 395         max-frequency = <192000000>;
 396 };
 397
 398 &mmc2 {
 399         /* SW5-3 in ON position */
 400         status = "okay";
 401         pinctrl-names = "default";
 402         pinctrl-0 = <&mmc2_pins_default>;
 403
 404         vmmc-supply = <&evm_3v3_sw>;
 405         bus-width = <8>;
 406         ti,non-removable;
 407         max-frequency = <192000000>;
 408 };
 409
 410 &mac {
 411         status = "okay";
 412 };
 413
 414 &dcan1 {
 415         status = "ok";
 416         pinctrl-names = "default", "sleep", "active";
 417         pinctrl-0 = <&dcan1_pins_sleep>;
 418         pinctrl-1 = <&dcan1_pins_sleep>;
 419         pinctrl-2 = <&dcan1_pins_default>;
 420 };
 421
 422 &qspi {
 423         status = "okay";
 424
 425         spi-max-frequency = <76800000>;
 426         m25p80@0 {
 427                 compatible = "s25fl256s1";
 428                 spi-max-frequency = <76800000>;
 429                 reg = <0>;
 430                 spi-tx-bus-width = <1>;
 431                 spi-rx-bus-width = <4>;
 432                 #address-cells = <1>;
 433                 #size-cells = <1>;
 434
 435                 /* MTD partition table.
 436                  * The ROM checks the first four physical blocks
 437                  * for a valid file to boot and the flash here is
 438                  * 64KiB block size.
 439                  */
 440                 partition@0 {
 441                         label = "QSPI.SPL";
 442                         reg = <0x00000000 0x000010000>;
 443                 };
 444                 partition@1 {
 445                         label = "QSPI.SPL.backup1";
 446                         reg = <0x00010000 0x00010000>;
 447                 };
 448                 partition@2 {
 449                         label = "QSPI.SPL.backup2";
 450                         reg = <0x00020000 0x00010000>;
 451                 };
 452                 partition@3 {
 453                         label = "QSPI.SPL.backup3";
 454                         reg = <0x00030000 0x00010000>;
 455                 };
 456                 partition@4 {
 457                         label = "QSPI.u-boot";
 458                         reg = <0x00040000 0x00100000>;
 459                 };
 460                 partition@5 {
 461                         label = "QSPI.u-boot-spl-os";
 462                         reg = <0x00140000 0x00080000>;
 463                 };
 464                 partition@6 {
 465                         label = "QSPI.u-boot-env";
 466                         reg = <0x001c0000 0x00010000>;
 467                 };
 468                 partition@7 {
 469                         label = "QSPI.u-boot-env.backup1";
 470                         reg = <0x001d0000 0x0010000>;
 471                 };
 472                 partition@8 {
 473                         label = "QSPI.kernel";
 474                         reg = <0x001e0000 0x0800000>;
 475                 };
 476                 partition@9 {
 477                         label = "QSPI.file-system";
 478                         reg = <0x009e0000 0x01620000>;
 479                 };
 480         };
 481 };
 482
 483 &dss {
 484         status = "ok";
 485 };
 486
 487 &hdmi {
 488         status = "ok";
 489
 490         port {
 491                 hdmi_out: endpoint {
 492                         remote-endpoint = <&tpd12s015_in>;
 493                 };
 494         };
 495 };
 496
 497 &atl {
 498         assigned-clocks = <&abe_dpll_sys_clk_mux>,
 499                           <&atl_gfclk_mux>,
 500                           <&dpll_abe_ck>,
 501                           <&dpll_abe_m2x2_ck>,
 502                           <&atl_clkin2_ck>;
 503         assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
 504         assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;
 505
 506         status = "okay";
 507
 508         atl2 {
 509                 bws = <DRA7_ATL_WS_MCASP2_FSX>;
 510                 aws = <DRA7_ATL_WS_MCASP3_FSX>;
 511         };
 512 };
 513
 514 &mcasp3 {
 515         #sound-dai-cells = <0>;
 516
 517         assigned-clocks = <&mcasp3_ahclkx_mux>;
 518         assigned-clock-parents = <&atl_clkin2_ck>;
 519
 520         status = "okay";
 521
 522         op-mode = <0>;          /* MCASP_IIS_MODE */
 523         tdm-slots = <2>;
 524         /* 4 serializer */
 525         serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
 526                 1 2 0 0
 527         >;
 528         tx-num-evt = <32>;
 529         rx-num-evt = <32>;
 530 };
 531
 532 &mailbox5 {
 533         status = "okay";
 534         mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
 535                 status = "okay";
 536         };
 537         mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
 538                 status = "okay";
 539         };
 540 };
 541
 542 &mailbox6 {
 543         status = "okay";
 544         mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
 545                 status = "okay";
 546         };
 547 };