2 * Device Tree Source for DRA7xx clock data
4 * Copyright (C) 2013 Texas Instruments, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 atl_clkin0_ck: atl_clkin0_ck {
13 compatible = "ti,dra7-atl-clock";
14 clocks = <&atl_gfclk_mux>;
17 atl_clkin1_ck: atl_clkin1_ck {
19 compatible = "ti,dra7-atl-clock";
20 clocks = <&atl_gfclk_mux>;
23 atl_clkin2_ck: atl_clkin2_ck {
25 compatible = "ti,dra7-atl-clock";
26 clocks = <&atl_gfclk_mux>;
29 atl_clkin3_ck: atl_clkin3_ck {
31 compatible = "ti,dra7-atl-clock";
32 clocks = <&atl_gfclk_mux>;
35 hdmi_clkin_ck: hdmi_clkin_ck {
37 compatible = "fixed-clock";
38 clock-frequency = <0>;
41 mlb_clkin_ck: mlb_clkin_ck {
43 compatible = "fixed-clock";
44 clock-frequency = <0>;
47 mlbp_clkin_ck: mlbp_clkin_ck {
49 compatible = "fixed-clock";
50 clock-frequency = <0>;
53 pciesref_acs_clk_ck: pciesref_acs_clk_ck {
55 compatible = "fixed-clock";
56 clock-frequency = <100000000>;
59 ref_clkin0_ck: ref_clkin0_ck {
61 compatible = "fixed-clock";
62 clock-frequency = <0>;
65 ref_clkin1_ck: ref_clkin1_ck {
67 compatible = "fixed-clock";
68 clock-frequency = <0>;
71 ref_clkin2_ck: ref_clkin2_ck {
73 compatible = "fixed-clock";
74 clock-frequency = <0>;
77 ref_clkin3_ck: ref_clkin3_ck {
79 compatible = "fixed-clock";
80 clock-frequency = <0>;
83 rmii_clk_ck: rmii_clk_ck {
85 compatible = "fixed-clock";
86 clock-frequency = <0>;
89 sdvenc_clkin_ck: sdvenc_clkin_ck {
91 compatible = "fixed-clock";
92 clock-frequency = <0>;
95 secure_32k_clk_src_ck: secure_32k_clk_src_ck {
97 compatible = "fixed-clock";
98 clock-frequency = <32768>;
101 sys_clk32_crystal_ck: sys_clk32_crystal_ck {
103 compatible = "fixed-clock";
104 clock-frequency = <32768>;
107 sys_clk32_pseudo_ck: sys_clk32_pseudo_ck {
109 compatible = "fixed-factor-clock";
110 clocks = <&sys_clkin1>;
115 virt_12000000_ck: virt_12000000_ck {
117 compatible = "fixed-clock";
118 clock-frequency = <12000000>;
121 virt_13000000_ck: virt_13000000_ck {
123 compatible = "fixed-clock";
124 clock-frequency = <13000000>;
127 virt_16800000_ck: virt_16800000_ck {
129 compatible = "fixed-clock";
130 clock-frequency = <16800000>;
133 virt_19200000_ck: virt_19200000_ck {
135 compatible = "fixed-clock";
136 clock-frequency = <19200000>;
139 virt_20000000_ck: virt_20000000_ck {
141 compatible = "fixed-clock";
142 clock-frequency = <20000000>;
145 virt_26000000_ck: virt_26000000_ck {
147 compatible = "fixed-clock";
148 clock-frequency = <26000000>;
151 virt_27000000_ck: virt_27000000_ck {
153 compatible = "fixed-clock";
154 clock-frequency = <27000000>;
157 virt_38400000_ck: virt_38400000_ck {
159 compatible = "fixed-clock";
160 clock-frequency = <38400000>;
163 sys_clkin2: sys_clkin2 {
165 compatible = "fixed-clock";
166 clock-frequency = <22579200>;
169 usb_otg_clkin_ck: usb_otg_clkin_ck {
171 compatible = "fixed-clock";
172 clock-frequency = <0>;
175 video1_clkin_ck: video1_clkin_ck {
177 compatible = "fixed-clock";
178 clock-frequency = <0>;
181 video1_m2_clkin_ck: video1_m2_clkin_ck {
183 compatible = "fixed-clock";
184 clock-frequency = <0>;
187 video2_clkin_ck: video2_clkin_ck {
189 compatible = "fixed-clock";
190 clock-frequency = <0>;
193 video2_m2_clkin_ck: video2_m2_clkin_ck {
195 compatible = "fixed-clock";
196 clock-frequency = <0>;
199 dpll_abe_ck: dpll_abe_ck@1e0 {
201 compatible = "ti,omap4-dpll-m4xen-clock";
202 clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
203 reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
206 dpll_abe_x2_ck: dpll_abe_x2_ck {
208 compatible = "ti,omap4-dpll-x2-clock";
209 clocks = <&dpll_abe_ck>;
212 dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 {
214 compatible = "ti,divider-clock";
215 clocks = <&dpll_abe_x2_ck>;
217 ti,autoidle-shift = <8>;
219 ti,index-starts-at-one;
220 ti,invert-autoidle-bit;
223 abe_clk: abe_clk@108 {
225 compatible = "ti,divider-clock";
226 clocks = <&dpll_abe_m2x2_ck>;
229 ti,index-power-of-two;
232 dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 {
234 compatible = "ti,divider-clock";
235 clocks = <&dpll_abe_ck>;
237 ti,autoidle-shift = <8>;
239 ti,index-starts-at-one;
240 ti,invert-autoidle-bit;
243 dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
245 compatible = "ti,divider-clock";
246 clocks = <&dpll_abe_x2_ck>;
248 ti,autoidle-shift = <8>;
250 ti,index-starts-at-one;
251 ti,invert-autoidle-bit;
254 dpll_core_byp_mux: dpll_core_byp_mux@12c {
256 compatible = "ti,mux-clock";
257 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
262 dpll_core_ck: dpll_core_ck@120 {
264 compatible = "ti,omap4-dpll-core-clock";
265 clocks = <&sys_clkin1>, <&dpll_core_byp_mux>;
266 reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
269 dpll_core_x2_ck: dpll_core_x2_ck {
271 compatible = "ti,omap4-dpll-x2-clock";
272 clocks = <&dpll_core_ck>;
275 dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c {
277 compatible = "ti,divider-clock";
278 clocks = <&dpll_core_x2_ck>;
280 ti,autoidle-shift = <8>;
282 ti,index-starts-at-one;
283 ti,invert-autoidle-bit;
286 mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
288 compatible = "fixed-factor-clock";
289 clocks = <&dpll_core_h12x2_ck>;
294 dpll_mpu_ck: dpll_mpu_ck@160 {
296 compatible = "ti,omap5-mpu-dpll-clock";
297 clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>;
298 reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
301 dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 {
303 compatible = "ti,divider-clock";
304 clocks = <&dpll_mpu_ck>;
306 ti,autoidle-shift = <8>;
308 ti,index-starts-at-one;
309 ti,invert-autoidle-bit;
312 mpu_dclk_div: mpu_dclk_div {
314 compatible = "fixed-factor-clock";
315 clocks = <&dpll_mpu_m2_ck>;
320 dsp_dpll_hs_clk_div: dsp_dpll_hs_clk_div {
322 compatible = "fixed-factor-clock";
323 clocks = <&dpll_core_h12x2_ck>;
328 dpll_dsp_byp_mux: dpll_dsp_byp_mux@240 {
330 compatible = "ti,mux-clock";
331 clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
336 dpll_dsp_ck: dpll_dsp_ck@234 {
338 compatible = "ti,omap4-dpll-clock";
339 clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>;
340 reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>;
341 assigned-clocks = <&dpll_dsp_ck>;
342 assigned-clock-rates = <600000000>;
345 dpll_dsp_m2_ck: dpll_dsp_m2_ck@244 {
347 compatible = "ti,divider-clock";
348 clocks = <&dpll_dsp_ck>;
350 ti,autoidle-shift = <8>;
352 ti,index-starts-at-one;
353 ti,invert-autoidle-bit;
354 assigned-clocks = <&dpll_dsp_m2_ck>;
355 assigned-clock-rates = <600000000>;
358 iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
360 compatible = "fixed-factor-clock";
361 clocks = <&dpll_core_h12x2_ck>;
366 dpll_iva_byp_mux: dpll_iva_byp_mux@1ac {
368 compatible = "ti,mux-clock";
369 clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
374 dpll_iva_ck: dpll_iva_ck@1a0 {
376 compatible = "ti,omap4-dpll-clock";
377 clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>;
378 reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
379 assigned-clocks = <&dpll_iva_ck>;
380 assigned-clock-rates = <1165000000>;
383 dpll_iva_m2_ck: dpll_iva_m2_ck@1b0 {
385 compatible = "ti,divider-clock";
386 clocks = <&dpll_iva_ck>;
388 ti,autoidle-shift = <8>;
390 ti,index-starts-at-one;
391 ti,invert-autoidle-bit;
392 assigned-clocks = <&dpll_iva_m2_ck>;
393 assigned-clock-rates = <388333334>;
398 compatible = "fixed-factor-clock";
399 clocks = <&dpll_iva_m2_ck>;
404 dpll_gpu_byp_mux: dpll_gpu_byp_mux@2e4 {
406 compatible = "ti,mux-clock";
407 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
412 dpll_gpu_ck: dpll_gpu_ck@2d8 {
414 compatible = "ti,omap4-dpll-clock";
415 clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>;
416 reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>;
417 assigned-clocks = <&dpll_gpu_ck>;
418 assigned-clock-rates = <1277000000>;
421 dpll_gpu_m2_ck: dpll_gpu_m2_ck@2e8 {
423 compatible = "ti,divider-clock";
424 clocks = <&dpll_gpu_ck>;
426 ti,autoidle-shift = <8>;
428 ti,index-starts-at-one;
429 ti,invert-autoidle-bit;
430 assigned-clocks = <&dpll_gpu_m2_ck>;
431 assigned-clock-rates = <425666667>;
434 dpll_core_m2_ck: dpll_core_m2_ck@130 {
436 compatible = "ti,divider-clock";
437 clocks = <&dpll_core_ck>;
439 ti,autoidle-shift = <8>;
441 ti,index-starts-at-one;
442 ti,invert-autoidle-bit;
445 core_dpll_out_dclk_div: core_dpll_out_dclk_div {
447 compatible = "fixed-factor-clock";
448 clocks = <&dpll_core_m2_ck>;
453 dpll_ddr_byp_mux: dpll_ddr_byp_mux@21c {
455 compatible = "ti,mux-clock";
456 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
461 dpll_ddr_ck: dpll_ddr_ck@210 {
463 compatible = "ti,omap4-dpll-clock";
464 clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>;
465 reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>;
468 dpll_ddr_m2_ck: dpll_ddr_m2_ck@220 {
470 compatible = "ti,divider-clock";
471 clocks = <&dpll_ddr_ck>;
473 ti,autoidle-shift = <8>;
475 ti,index-starts-at-one;
476 ti,invert-autoidle-bit;
479 dpll_gmac_byp_mux: dpll_gmac_byp_mux@2b4 {
481 compatible = "ti,mux-clock";
482 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
487 dpll_gmac_ck: dpll_gmac_ck@2a8 {
489 compatible = "ti,omap4-dpll-clock";
490 clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>;
491 reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>;
494 dpll_gmac_m2_ck: dpll_gmac_m2_ck@2b8 {
496 compatible = "ti,divider-clock";
497 clocks = <&dpll_gmac_ck>;
499 ti,autoidle-shift = <8>;
501 ti,index-starts-at-one;
502 ti,invert-autoidle-bit;
505 video2_dclk_div: video2_dclk_div {
507 compatible = "fixed-factor-clock";
508 clocks = <&video2_m2_clkin_ck>;
513 video1_dclk_div: video1_dclk_div {
515 compatible = "fixed-factor-clock";
516 clocks = <&video1_m2_clkin_ck>;
521 hdmi_dclk_div: hdmi_dclk_div {
523 compatible = "fixed-factor-clock";
524 clocks = <&hdmi_clkin_ck>;
529 per_dpll_hs_clk_div: per_dpll_hs_clk_div {
531 compatible = "fixed-factor-clock";
532 clocks = <&dpll_abe_m3x2_ck>;
537 usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
539 compatible = "fixed-factor-clock";
540 clocks = <&dpll_abe_m3x2_ck>;
545 eve_dpll_hs_clk_div: eve_dpll_hs_clk_div {
547 compatible = "fixed-factor-clock";
548 clocks = <&dpll_core_h12x2_ck>;
553 dpll_eve_byp_mux: dpll_eve_byp_mux@290 {
555 compatible = "ti,mux-clock";
556 clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
561 dpll_eve_ck: dpll_eve_ck@284 {
563 compatible = "ti,omap4-dpll-clock";
564 clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>;
565 reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>;
568 dpll_eve_m2_ck: dpll_eve_m2_ck@294 {
570 compatible = "ti,divider-clock";
571 clocks = <&dpll_eve_ck>;
573 ti,autoidle-shift = <8>;
575 ti,index-starts-at-one;
576 ti,invert-autoidle-bit;
579 eve_dclk_div: eve_dclk_div {
581 compatible = "fixed-factor-clock";
582 clocks = <&dpll_eve_m2_ck>;
587 dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 {
589 compatible = "ti,divider-clock";
590 clocks = <&dpll_core_x2_ck>;
592 ti,autoidle-shift = <8>;
594 ti,index-starts-at-one;
595 ti,invert-autoidle-bit;
598 dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 {
600 compatible = "ti,divider-clock";
601 clocks = <&dpll_core_x2_ck>;
603 ti,autoidle-shift = <8>;
605 ti,index-starts-at-one;
606 ti,invert-autoidle-bit;
609 dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 {
611 compatible = "ti,divider-clock";
612 clocks = <&dpll_core_x2_ck>;
614 ti,autoidle-shift = <8>;
616 ti,index-starts-at-one;
617 ti,invert-autoidle-bit;
620 dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 {
622 compatible = "ti,divider-clock";
623 clocks = <&dpll_core_x2_ck>;
625 ti,autoidle-shift = <8>;
627 ti,index-starts-at-one;
628 ti,invert-autoidle-bit;
631 dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c {
633 compatible = "ti,divider-clock";
634 clocks = <&dpll_core_x2_ck>;
636 ti,autoidle-shift = <8>;
638 ti,index-starts-at-one;
639 ti,invert-autoidle-bit;
642 dpll_ddr_x2_ck: dpll_ddr_x2_ck {
644 compatible = "ti,omap4-dpll-x2-clock";
645 clocks = <&dpll_ddr_ck>;
648 dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck@228 {
650 compatible = "ti,divider-clock";
651 clocks = <&dpll_ddr_x2_ck>;
653 ti,autoidle-shift = <8>;
655 ti,index-starts-at-one;
656 ti,invert-autoidle-bit;
659 dpll_dsp_x2_ck: dpll_dsp_x2_ck {
661 compatible = "ti,omap4-dpll-x2-clock";
662 clocks = <&dpll_dsp_ck>;
665 dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck@248 {
667 compatible = "ti,divider-clock";
668 clocks = <&dpll_dsp_x2_ck>;
670 ti,autoidle-shift = <8>;
672 ti,index-starts-at-one;
673 ti,invert-autoidle-bit;
674 assigned-clocks = <&dpll_dsp_m3x2_ck>;
675 assigned-clock-rates = <400000000>;
678 dpll_gmac_x2_ck: dpll_gmac_x2_ck {
680 compatible = "ti,omap4-dpll-x2-clock";
681 clocks = <&dpll_gmac_ck>;
684 dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck@2c0 {
686 compatible = "ti,divider-clock";
687 clocks = <&dpll_gmac_x2_ck>;
689 ti,autoidle-shift = <8>;
691 ti,index-starts-at-one;
692 ti,invert-autoidle-bit;
695 dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck@2c4 {
697 compatible = "ti,divider-clock";
698 clocks = <&dpll_gmac_x2_ck>;
700 ti,autoidle-shift = <8>;
702 ti,index-starts-at-one;
703 ti,invert-autoidle-bit;
706 dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck@2c8 {
708 compatible = "ti,divider-clock";
709 clocks = <&dpll_gmac_x2_ck>;
711 ti,autoidle-shift = <8>;
713 ti,index-starts-at-one;
714 ti,invert-autoidle-bit;
717 dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck@2bc {
719 compatible = "ti,divider-clock";
720 clocks = <&dpll_gmac_x2_ck>;
722 ti,autoidle-shift = <8>;
724 ti,index-starts-at-one;
725 ti,invert-autoidle-bit;
728 gmii_m_clk_div: gmii_m_clk_div {
730 compatible = "fixed-factor-clock";
731 clocks = <&dpll_gmac_h11x2_ck>;
736 hdmi_clk2_div: hdmi_clk2_div {
738 compatible = "fixed-factor-clock";
739 clocks = <&hdmi_clkin_ck>;
744 hdmi_div_clk: hdmi_div_clk {
746 compatible = "fixed-factor-clock";
747 clocks = <&hdmi_clkin_ck>;
752 l3_iclk_div: l3_iclk_div@100 {
754 compatible = "ti,divider-clock";
758 clocks = <&dpll_core_h12x2_ck>;
759 ti,index-power-of-two;
762 l4_root_clk_div: l4_root_clk_div {
764 compatible = "fixed-factor-clock";
765 clocks = <&l3_iclk_div>;
770 video1_clk2_div: video1_clk2_div {
772 compatible = "fixed-factor-clock";
773 clocks = <&video1_clkin_ck>;
778 video1_div_clk: video1_div_clk {
780 compatible = "fixed-factor-clock";
781 clocks = <&video1_clkin_ck>;
786 video2_clk2_div: video2_clk2_div {
788 compatible = "fixed-factor-clock";
789 clocks = <&video2_clkin_ck>;
794 video2_div_clk: video2_div_clk {
796 compatible = "fixed-factor-clock";
797 clocks = <&video2_clkin_ck>;
802 ipu1_gfclk_mux: ipu1_gfclk_mux@520 {
804 compatible = "ti,mux-clock";
805 clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>;
808 assigned-clocks = <&ipu1_gfclk_mux>;
809 assigned-clock-parents = <&dpll_core_h22x2_ck>;
812 mcasp1_ahclkr_mux: mcasp1_ahclkr_mux@550 {
814 compatible = "ti,mux-clock";
815 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
820 mcasp1_ahclkx_mux: mcasp1_ahclkx_mux@550 {
822 compatible = "ti,mux-clock";
823 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
828 mcasp1_aux_gfclk_mux: mcasp1_aux_gfclk_mux@550 {
830 compatible = "ti,mux-clock";
831 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
836 timer5_gfclk_mux: timer5_gfclk_mux@558 {
838 compatible = "ti,mux-clock";
839 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
844 timer6_gfclk_mux: timer6_gfclk_mux@560 {
846 compatible = "ti,mux-clock";
847 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
852 timer7_gfclk_mux: timer7_gfclk_mux@568 {
854 compatible = "ti,mux-clock";
855 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
860 timer8_gfclk_mux: timer8_gfclk_mux@570 {
862 compatible = "ti,mux-clock";
863 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
868 uart6_gfclk_mux: uart6_gfclk_mux@580 {
870 compatible = "ti,mux-clock";
871 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
878 compatible = "fixed-clock";
879 clock-frequency = <0>;
883 sys_clkin1: sys_clkin1@110 {
885 compatible = "ti,mux-clock";
886 clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
888 ti,index-starts-at-one;
891 abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux@118 {
893 compatible = "ti,mux-clock";
894 clocks = <&sys_clkin1>, <&sys_clkin2>;
898 abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@114 {
900 compatible = "ti,mux-clock";
901 clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
905 abe_dpll_clk_mux: abe_dpll_clk_mux@10c {
907 compatible = "ti,mux-clock";
908 clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
912 abe_24m_fclk: abe_24m_fclk@11c {
914 compatible = "ti,divider-clock";
915 clocks = <&dpll_abe_m2x2_ck>;
917 ti,dividers = <8>, <16>;
920 aess_fclk: aess_fclk@178 {
922 compatible = "ti,divider-clock";
928 abe_giclk_div: abe_giclk_div@174 {
930 compatible = "ti,divider-clock";
931 clocks = <&aess_fclk>;
936 abe_lp_clk_div: abe_lp_clk_div@1d8 {
938 compatible = "ti,divider-clock";
939 clocks = <&dpll_abe_m2x2_ck>;
941 ti,dividers = <16>, <32>;
944 abe_sys_clk_div: abe_sys_clk_div@120 {
946 compatible = "ti,divider-clock";
947 clocks = <&sys_clkin1>;
952 adc_gfclk_mux: adc_gfclk_mux@1dc {
954 compatible = "ti,mux-clock";
955 clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>;
959 sys_clk1_dclk_div: sys_clk1_dclk_div@1c8 {
961 compatible = "ti,divider-clock";
962 clocks = <&sys_clkin1>;
965 ti,index-power-of-two;
968 sys_clk2_dclk_div: sys_clk2_dclk_div@1cc {
970 compatible = "ti,divider-clock";
971 clocks = <&sys_clkin2>;
974 ti,index-power-of-two;
977 per_abe_x1_dclk_div: per_abe_x1_dclk_div@1bc {
979 compatible = "ti,divider-clock";
980 clocks = <&dpll_abe_m2_ck>;
983 ti,index-power-of-two;
986 dsp_gclk_div: dsp_gclk_div@18c {
988 compatible = "ti,divider-clock";
989 clocks = <&dpll_dsp_m2_ck>;
992 ti,index-power-of-two;
995 gpu_dclk: gpu_dclk@1a0 {
997 compatible = "ti,divider-clock";
998 clocks = <&dpll_gpu_m2_ck>;
1001 ti,index-power-of-two;
1004 emif_phy_dclk_div: emif_phy_dclk_div@190 {
1006 compatible = "ti,divider-clock";
1007 clocks = <&dpll_ddr_m2_ck>;
1010 ti,index-power-of-two;
1013 gmac_250m_dclk_div: gmac_250m_dclk_div@19c {
1015 compatible = "ti,divider-clock";
1016 clocks = <&dpll_gmac_m2_ck>;
1019 ti,index-power-of-two;
1022 gmac_main_clk: gmac_main_clk {
1024 compatible = "fixed-factor-clock";
1025 clocks = <&gmac_250m_dclk_div>;
1030 l3init_480m_dclk_div: l3init_480m_dclk_div@1ac {
1032 compatible = "ti,divider-clock";
1033 clocks = <&dpll_usb_m2_ck>;
1036 ti,index-power-of-two;
1039 usb_otg_dclk_div: usb_otg_dclk_div@184 {
1041 compatible = "ti,divider-clock";
1042 clocks = <&usb_otg_clkin_ck>;
1045 ti,index-power-of-two;
1048 sata_dclk_div: sata_dclk_div@1c0 {
1050 compatible = "ti,divider-clock";
1051 clocks = <&sys_clkin1>;
1054 ti,index-power-of-two;
1057 pcie2_dclk_div: pcie2_dclk_div@1b8 {
1059 compatible = "ti,divider-clock";
1060 clocks = <&dpll_pcie_ref_m2_ck>;
1063 ti,index-power-of-two;
1066 pcie_dclk_div: pcie_dclk_div@1b4 {
1068 compatible = "ti,divider-clock";
1069 clocks = <&apll_pcie_m2_ck>;
1072 ti,index-power-of-two;
1075 emu_dclk_div: emu_dclk_div@194 {
1077 compatible = "ti,divider-clock";
1078 clocks = <&sys_clkin1>;
1081 ti,index-power-of-two;
1084 secure_32k_dclk_div: secure_32k_dclk_div@1c4 {
1086 compatible = "ti,divider-clock";
1087 clocks = <&secure_32k_clk_src_ck>;
1090 ti,index-power-of-two;
1093 clkoutmux0_clk_mux: clkoutmux0_clk_mux@158 {
1095 compatible = "ti,mux-clock";
1096 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1100 clkoutmux1_clk_mux: clkoutmux1_clk_mux@15c {
1102 compatible = "ti,mux-clock";
1103 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1107 clkoutmux2_clk_mux: clkoutmux2_clk_mux@160 {
1109 compatible = "ti,mux-clock";
1110 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1114 custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
1116 compatible = "fixed-factor-clock";
1117 clocks = <&sys_clkin1>;
1122 eve_clk: eve_clk@180 {
1124 compatible = "ti,mux-clock";
1125 clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>;
1129 hdmi_dpll_clk_mux: hdmi_dpll_clk_mux@164 {
1131 compatible = "ti,mux-clock";
1132 clocks = <&sys_clkin1>, <&sys_clkin2>;
1136 mlb_clk: mlb_clk@134 {
1138 compatible = "ti,divider-clock";
1139 clocks = <&mlb_clkin_ck>;
1142 ti,index-power-of-two;
1145 mlbp_clk: mlbp_clk@130 {
1147 compatible = "ti,divider-clock";
1148 clocks = <&mlbp_clkin_ck>;
1151 ti,index-power-of-two;
1154 per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div@138 {
1156 compatible = "ti,divider-clock";
1157 clocks = <&dpll_abe_m2_ck>;
1160 ti,index-power-of-two;
1163 timer_sys_clk_div: timer_sys_clk_div@144 {
1165 compatible = "ti,divider-clock";
1166 clocks = <&sys_clkin1>;
1171 video1_dpll_clk_mux: video1_dpll_clk_mux@168 {
1173 compatible = "ti,mux-clock";
1174 clocks = <&sys_clkin1>, <&sys_clkin2>;
1178 video2_dpll_clk_mux: video2_dpll_clk_mux@16c {
1180 compatible = "ti,mux-clock";
1181 clocks = <&sys_clkin1>, <&sys_clkin2>;
1185 wkupaon_iclk_mux: wkupaon_iclk_mux@108 {
1187 compatible = "ti,mux-clock";
1188 clocks = <&sys_clkin1>, <&abe_lp_clk_div>;
1192 gpio1_dbclk: gpio1_dbclk@1838 {
1194 compatible = "ti,gate-clock";
1195 clocks = <&sys_32k_ck>;
1200 dcan1_sys_clk_mux: dcan1_sys_clk_mux@1888 {
1202 compatible = "ti,mux-clock";
1203 clocks = <&sys_clkin1>, <&sys_clkin2>;
1204 ti,bit-shift = <24>;
1208 timer1_gfclk_mux: timer1_gfclk_mux@1840 {
1210 compatible = "ti,mux-clock";
1211 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1212 ti,bit-shift = <24>;
1216 uart10_gfclk_mux: uart10_gfclk_mux@1880 {
1218 compatible = "ti,mux-clock";
1219 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1220 ti,bit-shift = <24>;
1225 dpll_pcie_ref_ck: dpll_pcie_ref_ck@200 {
1227 compatible = "ti,omap4-dpll-clock";
1228 clocks = <&sys_clkin1>, <&sys_clkin1>;
1229 reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
1232 dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck@210 {
1234 compatible = "ti,divider-clock";
1235 clocks = <&dpll_pcie_ref_ck>;
1237 ti,autoidle-shift = <8>;
1239 ti,index-starts-at-one;
1240 ti,invert-autoidle-bit;
1243 apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
1244 compatible = "ti,mux-clock";
1245 clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>;
1251 apll_pcie_ck: apll_pcie_ck@21c {
1253 compatible = "ti,dra7-apll-clock";
1254 clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
1255 reg = <0x021c>, <0x0220>;
1258 optfclk_pciephy1_32khz: optfclk_pciephy1_32khz@4a0093b0 {
1259 compatible = "ti,gate-clock";
1260 clocks = <&sys_32k_ck>;
1266 optfclk_pciephy2_32khz: optfclk_pciephy2_32khz@4a0093b8 {
1267 compatible = "ti,gate-clock";
1268 clocks = <&sys_32k_ck>;
1274 optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
1275 compatible = "ti,divider-clock";
1276 clocks = <&apll_pcie_ck>;
1279 ti,dividers = <2>, <1>;
1284 optfclk_pciephy1_clk: optfclk_pciephy1_clk@4a0093b0 {
1285 compatible = "ti,gate-clock";
1286 clocks = <&apll_pcie_ck>;
1292 optfclk_pciephy2_clk: optfclk_pciephy2_clk@4a0093b8 {
1293 compatible = "ti,gate-clock";
1294 clocks = <&apll_pcie_ck>;
1300 optfclk_pciephy1_div_clk: optfclk_pciephy1_div_clk@4a0093b0 {
1301 compatible = "ti,gate-clock";
1302 clocks = <&optfclk_pciephy_div>;
1305 ti,bit-shift = <10>;
1308 optfclk_pciephy2_div_clk: optfclk_pciephy2_div_clk@4a0093b8 {
1309 compatible = "ti,gate-clock";
1310 clocks = <&optfclk_pciephy_div>;
1313 ti,bit-shift = <10>;
1316 apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
1318 compatible = "fixed-factor-clock";
1319 clocks = <&apll_pcie_ck>;
1324 apll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div {
1326 compatible = "fixed-factor-clock";
1327 clocks = <&apll_pcie_ck>;
1332 apll_pcie_m2_ck: apll_pcie_m2_ck {
1334 compatible = "fixed-factor-clock";
1335 clocks = <&apll_pcie_ck>;
1340 dpll_per_byp_mux: dpll_per_byp_mux@14c {
1342 compatible = "ti,mux-clock";
1343 clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
1344 ti,bit-shift = <23>;
1348 dpll_per_ck: dpll_per_ck@140 {
1350 compatible = "ti,omap4-dpll-clock";
1351 clocks = <&sys_clkin1>, <&dpll_per_byp_mux>;
1352 reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
1355 dpll_per_m2_ck: dpll_per_m2_ck@150 {
1357 compatible = "ti,divider-clock";
1358 clocks = <&dpll_per_ck>;
1360 ti,autoidle-shift = <8>;
1362 ti,index-starts-at-one;
1363 ti,invert-autoidle-bit;
1366 func_96m_aon_dclk_div: func_96m_aon_dclk_div {
1368 compatible = "fixed-factor-clock";
1369 clocks = <&dpll_per_m2_ck>;
1374 dpll_usb_byp_mux: dpll_usb_byp_mux@18c {
1376 compatible = "ti,mux-clock";
1377 clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
1378 ti,bit-shift = <23>;
1382 dpll_usb_ck: dpll_usb_ck@180 {
1384 compatible = "ti,omap4-dpll-j-type-clock";
1385 clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>;
1386 reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
1389 dpll_usb_m2_ck: dpll_usb_m2_ck@190 {
1391 compatible = "ti,divider-clock";
1392 clocks = <&dpll_usb_ck>;
1394 ti,autoidle-shift = <8>;
1396 ti,index-starts-at-one;
1397 ti,invert-autoidle-bit;
1400 dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck@210 {
1402 compatible = "ti,divider-clock";
1403 clocks = <&dpll_pcie_ref_ck>;
1405 ti,autoidle-shift = <8>;
1407 ti,index-starts-at-one;
1408 ti,invert-autoidle-bit;
1411 dpll_per_x2_ck: dpll_per_x2_ck {
1413 compatible = "ti,omap4-dpll-x2-clock";
1414 clocks = <&dpll_per_ck>;
1417 dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 {
1419 compatible = "ti,divider-clock";
1420 clocks = <&dpll_per_x2_ck>;
1422 ti,autoidle-shift = <8>;
1424 ti,index-starts-at-one;
1425 ti,invert-autoidle-bit;
1428 dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c {
1430 compatible = "ti,divider-clock";
1431 clocks = <&dpll_per_x2_ck>;
1433 ti,autoidle-shift = <8>;
1435 ti,index-starts-at-one;
1436 ti,invert-autoidle-bit;
1439 dpll_per_h13x2_ck: dpll_per_h13x2_ck@160 {
1441 compatible = "ti,divider-clock";
1442 clocks = <&dpll_per_x2_ck>;
1444 ti,autoidle-shift = <8>;
1446 ti,index-starts-at-one;
1447 ti,invert-autoidle-bit;
1450 dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 {
1452 compatible = "ti,divider-clock";
1453 clocks = <&dpll_per_x2_ck>;
1455 ti,autoidle-shift = <8>;
1457 ti,index-starts-at-one;
1458 ti,invert-autoidle-bit;
1461 dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 {
1463 compatible = "ti,divider-clock";
1464 clocks = <&dpll_per_x2_ck>;
1466 ti,autoidle-shift = <8>;
1468 ti,index-starts-at-one;
1469 ti,invert-autoidle-bit;
1472 dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
1474 compatible = "fixed-factor-clock";
1475 clocks = <&dpll_usb_ck>;
1480 func_128m_clk: func_128m_clk {
1482 compatible = "fixed-factor-clock";
1483 clocks = <&dpll_per_h11x2_ck>;
1488 func_12m_fclk: func_12m_fclk {
1490 compatible = "fixed-factor-clock";
1491 clocks = <&dpll_per_m2x2_ck>;
1496 func_24m_clk: func_24m_clk {
1498 compatible = "fixed-factor-clock";
1499 clocks = <&dpll_per_m2_ck>;
1504 func_48m_fclk: func_48m_fclk {
1506 compatible = "fixed-factor-clock";
1507 clocks = <&dpll_per_m2x2_ck>;
1512 func_96m_fclk: func_96m_fclk {
1514 compatible = "fixed-factor-clock";
1515 clocks = <&dpll_per_m2x2_ck>;
1520 l3init_60m_fclk: l3init_60m_fclk@104 {
1522 compatible = "ti,divider-clock";
1523 clocks = <&dpll_usb_m2_ck>;
1525 ti,dividers = <1>, <8>;
1528 clkout2_clk: clkout2_clk@6b0 {
1530 compatible = "ti,gate-clock";
1531 clocks = <&clkoutmux2_clk_mux>;
1536 l3init_960m_gfclk: l3init_960m_gfclk@6c0 {
1538 compatible = "ti,gate-clock";
1539 clocks = <&dpll_usb_clkdcoldo>;
1544 dss_32khz_clk: dss_32khz_clk@1120 {
1546 compatible = "ti,gate-clock";
1547 clocks = <&sys_32k_ck>;
1548 ti,bit-shift = <11>;
1552 dss_48mhz_clk: dss_48mhz_clk@1120 {
1554 compatible = "ti,gate-clock";
1555 clocks = <&func_48m_fclk>;
1560 dss_dss_clk: dss_dss_clk@1120 {
1562 compatible = "ti,gate-clock";
1563 clocks = <&dpll_per_h12x2_ck>;
1569 dss_hdmi_clk: dss_hdmi_clk@1120 {
1571 compatible = "ti,gate-clock";
1572 clocks = <&hdmi_dpll_clk_mux>;
1573 ti,bit-shift = <10>;
1577 dss_video1_clk: dss_video1_clk@1120 {
1579 compatible = "ti,gate-clock";
1580 clocks = <&video1_dpll_clk_mux>;
1581 ti,bit-shift = <12>;
1585 dss_video2_clk: dss_video2_clk@1120 {
1587 compatible = "ti,gate-clock";
1588 clocks = <&video2_dpll_clk_mux>;
1589 ti,bit-shift = <13>;
1593 gpio2_dbclk: gpio2_dbclk@1760 {
1595 compatible = "ti,gate-clock";
1596 clocks = <&sys_32k_ck>;
1601 gpio3_dbclk: gpio3_dbclk@1768 {
1603 compatible = "ti,gate-clock";
1604 clocks = <&sys_32k_ck>;
1609 gpio4_dbclk: gpio4_dbclk@1770 {
1611 compatible = "ti,gate-clock";
1612 clocks = <&sys_32k_ck>;
1617 gpio5_dbclk: gpio5_dbclk@1778 {
1619 compatible = "ti,gate-clock";
1620 clocks = <&sys_32k_ck>;
1625 gpio6_dbclk: gpio6_dbclk@1780 {
1627 compatible = "ti,gate-clock";
1628 clocks = <&sys_32k_ck>;
1633 gpio7_dbclk: gpio7_dbclk@1810 {
1635 compatible = "ti,gate-clock";
1636 clocks = <&sys_32k_ck>;
1641 gpio8_dbclk: gpio8_dbclk@1818 {
1643 compatible = "ti,gate-clock";
1644 clocks = <&sys_32k_ck>;
1649 mmc1_clk32k: mmc1_clk32k@1328 {
1651 compatible = "ti,gate-clock";
1652 clocks = <&sys_32k_ck>;
1657 mmc2_clk32k: mmc2_clk32k@1330 {
1659 compatible = "ti,gate-clock";
1660 clocks = <&sys_32k_ck>;
1665 mmc3_clk32k: mmc3_clk32k@1820 {
1667 compatible = "ti,gate-clock";
1668 clocks = <&sys_32k_ck>;
1673 mmc4_clk32k: mmc4_clk32k@1828 {
1675 compatible = "ti,gate-clock";
1676 clocks = <&sys_32k_ck>;
1681 sata_ref_clk: sata_ref_clk@1388 {
1683 compatible = "ti,gate-clock";
1684 clocks = <&sys_clkin1>;
1689 usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m@13f0 {
1691 compatible = "ti,gate-clock";
1692 clocks = <&l3init_960m_gfclk>;
1697 usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m@1340 {
1699 compatible = "ti,gate-clock";
1700 clocks = <&l3init_960m_gfclk>;
1705 usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@640 {
1707 compatible = "ti,gate-clock";
1708 clocks = <&sys_32k_ck>;
1713 usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k@688 {
1715 compatible = "ti,gate-clock";
1716 clocks = <&sys_32k_ck>;
1721 usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k@698 {
1723 compatible = "ti,gate-clock";
1724 clocks = <&sys_32k_ck>;
1729 atl_dpll_clk_mux: atl_dpll_clk_mux@c00 {
1731 compatible = "ti,mux-clock";
1732 clocks = <&sys_32k_ck>, <&video1_clkin_ck>, <&video2_clkin_ck>, <&hdmi_clkin_ck>;
1733 ti,bit-shift = <24>;
1737 atl_gfclk_mux: atl_gfclk_mux@c00 {
1739 compatible = "ti,mux-clock";
1740 clocks = <&l3_iclk_div>, <&dpll_abe_m2_ck>, <&atl_dpll_clk_mux>;
1741 ti,bit-shift = <26>;
1745 rmii_50mhz_clk_mux: rmii_50mhz_clk_mux@13d0 {
1747 compatible = "ti,mux-clock";
1748 clocks = <&dpll_gmac_h11x2_ck>, <&rmii_clk_ck>;
1749 ti,bit-shift = <24>;
1753 gmac_rft_clk_mux: gmac_rft_clk_mux@13d0 {
1755 compatible = "ti,mux-clock";
1756 clocks = <&video1_clkin_ck>, <&video2_clkin_ck>, <&dpll_abe_m2_ck>, <&hdmi_clkin_ck>, <&l3_iclk_div>;
1757 ti,bit-shift = <25>;
1761 gpu_core_gclk_mux: gpu_core_gclk_mux@1220 {
1763 compatible = "ti,mux-clock";
1764 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
1765 ti,bit-shift = <24>;
1767 assigned-clocks = <&gpu_core_gclk_mux>;
1768 assigned-clock-parents = <&dpll_gpu_m2_ck>;
1771 gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1220 {
1773 compatible = "ti,mux-clock";
1774 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
1775 ti,bit-shift = <26>;
1777 assigned-clocks = <&gpu_hyd_gclk_mux>;
1778 assigned-clock-parents = <&dpll_gpu_m2_ck>;
1781 l3instr_ts_gclk_div: l3instr_ts_gclk_div@e50 {
1783 compatible = "ti,divider-clock";
1784 clocks = <&wkupaon_iclk_mux>;
1785 ti,bit-shift = <24>;
1787 ti,dividers = <8>, <16>, <32>;
1790 mcasp2_ahclkr_mux: mcasp2_ahclkr_mux@1860 {
1792 compatible = "ti,mux-clock";
1793 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1794 ti,bit-shift = <28>;
1798 mcasp2_ahclkx_mux: mcasp2_ahclkx_mux@1860 {
1800 compatible = "ti,mux-clock";
1801 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1802 ti,bit-shift = <24>;
1806 mcasp2_aux_gfclk_mux: mcasp2_aux_gfclk_mux@1860 {
1808 compatible = "ti,mux-clock";
1809 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1810 ti,bit-shift = <22>;
1814 mcasp3_ahclkx_mux: mcasp3_ahclkx_mux@1868 {
1816 compatible = "ti,mux-clock";
1817 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1818 ti,bit-shift = <24>;
1820 assigned-clocks = <&mcasp3_ahclkx_mux>;
1821 assigned-clock-parents = <&abe_24m_fclk>;
1824 mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux@1868 {
1826 compatible = "ti,mux-clock";
1827 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1828 ti,bit-shift = <22>;
1832 mcasp4_ahclkx_mux: mcasp4_ahclkx_mux@1898 {
1834 compatible = "ti,mux-clock";
1835 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1836 ti,bit-shift = <24>;
1840 mcasp4_aux_gfclk_mux: mcasp4_aux_gfclk_mux@1898 {
1842 compatible = "ti,mux-clock";
1843 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1844 ti,bit-shift = <22>;
1848 mcasp5_ahclkx_mux: mcasp5_ahclkx_mux@1878 {
1850 compatible = "ti,mux-clock";
1851 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1852 ti,bit-shift = <24>;
1856 mcasp5_aux_gfclk_mux: mcasp5_aux_gfclk_mux@1878 {
1858 compatible = "ti,mux-clock";
1859 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1860 ti,bit-shift = <22>;
1864 mcasp6_ahclkx_mux: mcasp6_ahclkx_mux@1904 {
1866 compatible = "ti,mux-clock";
1867 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1868 ti,bit-shift = <24>;
1872 mcasp6_aux_gfclk_mux: mcasp6_aux_gfclk_mux@1904 {
1874 compatible = "ti,mux-clock";
1875 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1876 ti,bit-shift = <22>;
1880 mcasp7_ahclkx_mux: mcasp7_ahclkx_mux@1908 {
1882 compatible = "ti,mux-clock";
1883 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1884 ti,bit-shift = <24>;
1888 mcasp7_aux_gfclk_mux: mcasp7_aux_gfclk_mux@1908 {
1890 compatible = "ti,mux-clock";
1891 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1892 ti,bit-shift = <22>;
1896 mcasp8_ahclkx_mux: mcasp8_ahclkx_mux@1890 {
1898 compatible = "ti,mux-clock";
1899 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1900 ti,bit-shift = <22>;
1904 mcasp8_aux_gfclk_mux: mcasp8_aux_gfclk_mux@1890 {
1906 compatible = "ti,mux-clock";
1907 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1908 ti,bit-shift = <24>;
1912 mmc1_fclk_mux: mmc1_fclk_mux@1328 {
1914 compatible = "ti,mux-clock";
1915 clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
1916 ti,bit-shift = <24>;
1920 mmc1_fclk_div: mmc1_fclk_div@1328 {
1922 compatible = "ti,divider-clock";
1923 clocks = <&mmc1_fclk_mux>;
1924 ti,bit-shift = <25>;
1927 ti,index-power-of-two;
1930 mmc2_fclk_mux: mmc2_fclk_mux@1330 {
1932 compatible = "ti,mux-clock";
1933 clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
1934 ti,bit-shift = <24>;
1938 mmc2_fclk_div: mmc2_fclk_div@1330 {
1940 compatible = "ti,divider-clock";
1941 clocks = <&mmc2_fclk_mux>;
1942 ti,bit-shift = <25>;
1945 ti,index-power-of-two;
1948 mmc3_gfclk_mux: mmc3_gfclk_mux@1820 {
1950 compatible = "ti,mux-clock";
1951 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1952 ti,bit-shift = <24>;
1956 mmc3_gfclk_div: mmc3_gfclk_div@1820 {
1958 compatible = "ti,divider-clock";
1959 clocks = <&mmc3_gfclk_mux>;
1960 ti,bit-shift = <25>;
1963 ti,index-power-of-two;
1966 mmc4_gfclk_mux: mmc4_gfclk_mux@1828 {
1968 compatible = "ti,mux-clock";
1969 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1970 ti,bit-shift = <24>;
1974 mmc4_gfclk_div: mmc4_gfclk_div@1828 {
1976 compatible = "ti,divider-clock";
1977 clocks = <&mmc4_gfclk_mux>;
1978 ti,bit-shift = <25>;
1981 ti,index-power-of-two;
1984 qspi_gfclk_mux: qspi_gfclk_mux@1838 {
1986 compatible = "ti,mux-clock";
1987 clocks = <&func_128m_clk>, <&dpll_per_h13x2_ck>;
1988 ti,bit-shift = <24>;
1992 qspi_gfclk_div: qspi_gfclk_div@1838 {
1994 compatible = "ti,divider-clock";
1995 clocks = <&qspi_gfclk_mux>;
1996 ti,bit-shift = <25>;
1999 ti,index-power-of-two;
2002 timer10_gfclk_mux: timer10_gfclk_mux@1728 {
2004 compatible = "ti,mux-clock";
2005 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
2006 ti,bit-shift = <24>;
2010 timer11_gfclk_mux: timer11_gfclk_mux@1730 {
2012 compatible = "ti,mux-clock";
2013 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
2014 ti,bit-shift = <24>;
2018 timer13_gfclk_mux: timer13_gfclk_mux@17c8 {
2020 compatible = "ti,mux-clock";
2021 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
2022 ti,bit-shift = <24>;
2026 timer14_gfclk_mux: timer14_gfclk_mux@17d0 {
2028 compatible = "ti,mux-clock";
2029 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
2030 ti,bit-shift = <24>;
2034 timer15_gfclk_mux: timer15_gfclk_mux@17d8 {
2036 compatible = "ti,mux-clock";
2037 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
2038 ti,bit-shift = <24>;
2042 timer16_gfclk_mux: timer16_gfclk_mux@1830 {
2044 compatible = "ti,mux-clock";
2045 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
2046 ti,bit-shift = <24>;
2050 timer2_gfclk_mux: timer2_gfclk_mux@1738 {
2052 compatible = "ti,mux-clock";
2053 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
2054 ti,bit-shift = <24>;
2058 timer3_gfclk_mux: timer3_gfclk_mux@1740 {
2060 compatible = "ti,mux-clock";
2061 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
2062 ti,bit-shift = <24>;
2066 timer4_gfclk_mux: timer4_gfclk_mux@1748 {
2068 compatible = "ti,mux-clock";
2069 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
2070 ti,bit-shift = <24>;
2074 timer9_gfclk_mux: timer9_gfclk_mux@1750 {
2076 compatible = "ti,mux-clock";
2077 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
2078 ti,bit-shift = <24>;
2082 uart1_gfclk_mux: uart1_gfclk_mux@1840 {
2084 compatible = "ti,mux-clock";
2085 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2086 ti,bit-shift = <24>;
2090 uart2_gfclk_mux: uart2_gfclk_mux@1848 {
2092 compatible = "ti,mux-clock";
2093 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2094 ti,bit-shift = <24>;
2098 uart3_gfclk_mux: uart3_gfclk_mux@1850 {
2100 compatible = "ti,mux-clock";
2101 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2102 ti,bit-shift = <24>;
2106 uart4_gfclk_mux: uart4_gfclk_mux@1858 {
2108 compatible = "ti,mux-clock";
2109 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2110 ti,bit-shift = <24>;
2114 uart5_gfclk_mux: uart5_gfclk_mux@1870 {
2116 compatible = "ti,mux-clock";
2117 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2118 ti,bit-shift = <24>;
2122 uart7_gfclk_mux: uart7_gfclk_mux@18d0 {
2124 compatible = "ti,mux-clock";
2125 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2126 ti,bit-shift = <24>;
2130 uart8_gfclk_mux: uart8_gfclk_mux@18e0 {
2132 compatible = "ti,mux-clock";
2133 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2134 ti,bit-shift = <24>;
2138 uart9_gfclk_mux: uart9_gfclk_mux@18e8 {
2140 compatible = "ti,mux-clock";
2141 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2142 ti,bit-shift = <24>;
2146 vip1_gclk_mux: vip1_gclk_mux@1020 {
2148 compatible = "ti,mux-clock";
2149 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
2150 ti,bit-shift = <24>;
2154 vip2_gclk_mux: vip2_gclk_mux@1028 {
2156 compatible = "ti,mux-clock";
2157 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
2158 ti,bit-shift = <24>;
2162 vip3_gclk_mux: vip3_gclk_mux@1030 {
2164 compatible = "ti,mux-clock";
2165 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
2166 ti,bit-shift = <24>;
2171 &cm_core_clockdomains {
2172 coreaon_clkdm: coreaon_clkdm {
2173 compatible = "ti,clockdomain";
2174 clocks = <&dpll_usb_ck>;
2179 dss_deshdcp_clk: dss_deshdcp_clk@558 {
2181 compatible = "ti,gate-clock";
2182 clocks = <&l3_iclk_div>;
2187 ehrpwm0_tbclk: ehrpwm0_tbclk@558 {
2189 compatible = "ti,gate-clock";
2190 clocks = <&l4_root_clk_div>;
2191 ti,bit-shift = <20>;
2195 ehrpwm1_tbclk: ehrpwm1_tbclk@558 {
2197 compatible = "ti,gate-clock";
2198 clocks = <&l4_root_clk_div>;
2199 ti,bit-shift = <21>;
2203 ehrpwm2_tbclk: ehrpwm2_tbclk@558 {
2205 compatible = "ti,gate-clock";
2206 clocks = <&l4_root_clk_div>;
2207 ti,bit-shift = <22>;
2211 sys_32k_ck: sys_32k_ck {
2213 compatible = "ti,mux-clock";
2214 clocks = <&sys_clk32_crystal_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>;