sys/gnu/dts/arm/exynos5250.dtsi

   1 /*
   2  * SAMSUNG EXYNOS5250 SoC device tree source
   3  *
   4  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
   8  * EXYNOS5250 based board files can include this file and provide
   9  * values for board specfic bindings.
  10  *
  11  * Note: This file does not include device nodes for all the controllers in
  12  * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
  13  * additional nodes can be added to this file.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18 */
  19
  20 #include <dt-bindings/clock/exynos5250.h>
  21 #include "exynos5.dtsi"
  22 #include "exynos4-cpu-thermal.dtsi"
  23 #include <dt-bindings/clock/exynos-audss-clk.h>
  24
  25 / {
  26         compatible = "samsung,exynos5250", "samsung,exynos5";
  27
  28         aliases {
  29                 spi0 = &spi_0;
  30                 spi1 = &spi_1;
  31                 spi2 = &spi_2;
  32                 gsc0 = &gsc_0;
  33                 gsc1 = &gsc_1;
  34                 gsc2 = &gsc_2;
  35                 gsc3 = &gsc_3;
  36                 mshc0 = &mmc_0;
  37                 mshc1 = &mmc_1;
  38                 mshc2 = &mmc_2;
  39                 mshc3 = &mmc_3;
  40                 i2c4 = &i2c_4;
  41                 i2c5 = &i2c_5;
  42                 i2c6 = &i2c_6;
  43                 i2c7 = &i2c_7;
  44                 i2c8 = &i2c_8;
  45                 i2c9 = &i2c_9;
  46                 pinctrl0 = &pinctrl_0;
  47                 pinctrl1 = &pinctrl_1;
  48                 pinctrl2 = &pinctrl_2;
  49                 pinctrl3 = &pinctrl_3;
  50         };
  51
  52         cpus {
  53                 #address-cells = <1>;
  54                 #size-cells = <0>;
  55
  56                 cpu0: cpu@0 {
  57                         device_type = "cpu";
  58                         compatible = "arm,cortex-a15";
  59                         reg = <0>;
  60                         clock-frequency = <1700000000>;
  61                         clocks = <&clock CLK_ARM_CLK>;
  62                         clock-names = "cpu";
  63                         clock-latency = <140000>;
  64
  65                         operating-points = <
  66                                 1700000 1300000
  67                                 1600000 1250000
  68                                 1500000 1225000
  69                                 1400000 1200000
  70                                 1300000 1150000
  71                                 1200000 1125000
  72                                 1100000 1100000
  73                                 1000000 1075000
  74                                  900000 1050000
  75                                  800000 1025000
  76                                  700000 1012500
  77                                  600000 1000000
  78                                  500000  975000
  79                                  400000  950000
  80                                  300000  937500
  81                                  200000  925000
  82                         >;
  83                         cooling-min-level = <15>;
  84                         cooling-max-level = <9>;
  85                         #cooling-cells = <2>; /* min followed by max */
  86                 };
  87                 cpu@1 {
  88                         device_type = "cpu";
  89                         compatible = "arm,cortex-a15";
  90                         reg = <1>;
  91                         clock-frequency = <1700000000>;
  92                 };
  93         };
  94
  95         soc: soc {
  96                 sysram@02020000 {
  97                         compatible = "mmio-sram";
  98                         reg = <0x02020000 0x30000>;
  99                         #address-cells = <1>;
 100                         #size-cells = <1>;
 101                         ranges = <0 0x02020000 0x30000>;
 102
 103                         smp-sysram@0 {
 104                                 compatible = "samsung,exynos4210-sysram";
 105                                 reg = <0x0 0x1000>;
 106                         };
 107
 108                         smp-sysram@2f000 {
 109                                 compatible = "samsung,exynos4210-sysram-ns";
 110                                 reg = <0x2f000 0x1000>;
 111                         };
 112                 };
 113
 114                 pd_gsc: gsc-power-domain@10044000 {
 115                         compatible = "samsung,exynos4210-pd";
 116                         reg = <0x10044000 0x20>;
 117                         #power-domain-cells = <0>;
 118                         label = "GSC";
 119                 };
 120
 121                 pd_mfc: mfc-power-domain@10044040 {
 122                         compatible = "samsung,exynos4210-pd";
 123                         reg = <0x10044040 0x20>;
 124                         #power-domain-cells = <0>;
 125                         label = "MFC";
 126                 };
 127
 128                 pd_disp1: disp1-power-domain@100440A0 {
 129                         compatible = "samsung,exynos4210-pd";
 130                         reg = <0x100440A0 0x20>;
 131                         #power-domain-cells = <0>;
 132                         label = "DISP1";
 133                         clocks = <&clock CLK_FIN_PLL>,
 134                                  <&clock CLK_MOUT_ACLK200_DISP1_SUB>,
 135                                  <&clock CLK_MOUT_ACLK300_DISP1_SUB>;
 136                         clock-names = "oscclk", "clk0", "clk1";
 137                 };
 138
 139                 clock: clock-controller@10010000 {
 140                         compatible = "samsung,exynos5250-clock";
 141                         reg = <0x10010000 0x30000>;
 142                         #clock-cells = <1>;
 143                 };
 144
 145                 clock_audss: audss-clock-controller@3810000 {
 146                         compatible = "samsung,exynos5250-audss-clock";
 147                         reg = <0x03810000 0x0C>;
 148                         #clock-cells = <1>;
 149                         clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
 150                                  <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>;
 151                         clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
 152                 };
 153
 154                 timer {
 155                         compatible = "arm,armv7-timer";
 156                         interrupts = <1 13 0xf08>,
 157                                      <1 14 0xf08>,
 158                                      <1 11 0xf08>,
 159                                      <1 10 0xf08>;
 160                         /*
 161                          * Unfortunately we need this since some versions
 162                          * of U-Boot on Exynos don't set the CNTFRQ register,
 163                          * so we need the value from DT.
 164                          */
 165                         clock-frequency = <24000000>;
 166                 };
 167
 168                 mct@101C0000 {
 169                         compatible = "samsung,exynos4210-mct";
 170                         reg = <0x101C0000 0x800>;
 171                         interrupt-controller;
 172                         #interrupt-cells = <2>;
 173                         interrupt-parent = <&mct_map>;
 174                         interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
 175                                      <4 0>, <5 0>;
 176                         clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
 177                         clock-names = "fin_pll", "mct";
 178
 179                         mct_map: mct-map {
 180                                 #interrupt-cells = <2>;
 181                                 #address-cells = <0>;
 182                                 #size-cells = <0>;
 183                                 interrupt-map = <0x0 0 &combiner 23 3>,
 184                                                 <0x1 0 &combiner 23 4>,
 185                                                 <0x2 0 &combiner 25 2>,
 186                                                 <0x3 0 &combiner 25 3>,
 187                                                 <0x4 0 &gic 0 120 IRQ_TYPE_LEVEL_HIGH>,
 188                                                 <0x5 0 &gic 0 121 IRQ_TYPE_LEVEL_HIGH>;
 189                         };
 190                 };
 191
 192                 pmu {
 193                         compatible = "arm,cortex-a15-pmu";
 194                         interrupt-parent = <&combiner>;
 195                         interrupts = <1 2>, <22 4>;
 196                 };
 197
 198                 pinctrl_0: pinctrl@11400000 {
 199                         compatible = "samsung,exynos5250-pinctrl";
 200                         reg = <0x11400000 0x1000>;
 201                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 202
 203                         wakup_eint: wakeup-interrupt-controller {
 204                                 compatible = "samsung,exynos4210-wakeup-eint";
 205                                 interrupt-parent = <&gic>;
 206                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 207                         };
 208                 };
 209
 210                 pinctrl_1: pinctrl@13400000 {
 211                         compatible = "samsung,exynos5250-pinctrl";
 212                         reg = <0x13400000 0x1000>;
 213                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 214                 };
 215
 216                 pinctrl_2: pinctrl@10d10000 {
 217                         compatible = "samsung,exynos5250-pinctrl";
 218                         reg = <0x10d10000 0x1000>;
 219                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 220                 };
 221
 222                 pinctrl_3: pinctrl@03860000 {
 223                         compatible = "samsung,exynos5250-pinctrl";
 224                         reg = <0x03860000 0x1000>;
 225                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 226                 };
 227
 228                 pmu_system_controller: system-controller@10040000 {
 229                         compatible = "samsung,exynos5250-pmu", "syscon";
 230                         reg = <0x10040000 0x5000>;
 231                         clock-names = "clkout16";
 232                         clocks = <&clock CLK_FIN_PLL>;
 233                         #clock-cells = <1>;
 234                         interrupt-controller;
 235                         #interrupt-cells = <3>;
 236                         interrupt-parent = <&gic>;
 237                 };
 238
 239                 watchdog@101D0000 {
 240                         compatible = "samsung,exynos5250-wdt";
 241                         reg = <0x101D0000 0x100>;
 242                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 243                         clocks = <&clock CLK_WDT>;
 244                         clock-names = "watchdog";
 245                         samsung,syscon-phandle = <&pmu_system_controller>;
 246                 };
 247
 248                 g2d@10850000 {
 249                         compatible = "samsung,exynos5250-g2d";
 250                         reg = <0x10850000 0x1000>;
 251                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 252                         clocks = <&clock CLK_G2D>;
 253                         clock-names = "fimg2d";
 254                         iommus = <&sysmmu_g2d>;
 255                 };
 256
 257                 mfc: codec@11000000 {
 258                         compatible = "samsung,mfc-v6";
 259                         reg = <0x11000000 0x10000>;
 260                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 261                         power-domains = <&pd_mfc>;
 262                         clocks = <&clock CLK_MFC>;
 263                         clock-names = "mfc";
 264                         iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
 265                         iommu-names = "left", "right";
 266                 };
 267
 268                 rotator: rotator@11C00000 {
 269                         compatible = "samsung,exynos5250-rotator";
 270                         reg = <0x11C00000 0x64>;
 271                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 272                         clocks = <&clock CLK_ROTATOR>;
 273                         clock-names = "rotator";
 274                         iommus = <&sysmmu_rotator>;
 275                 };
 276
 277                 tmu: tmu@10060000 {
 278                         compatible = "samsung,exynos5250-tmu";
 279                         reg = <0x10060000 0x100>;
 280                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 281                         clocks = <&clock CLK_TMU>;
 282                         clock-names = "tmu_apbif";
 283                         #include "exynos4412-tmu-sensor-conf.dtsi"
 284                 };
 285
 286                 sata: sata@122F0000 {
 287                         compatible = "snps,dwc-ahci";
 288                         samsung,sata-freq = <66>;
 289                         reg = <0x122F0000 0x1ff>;
 290                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 291                         clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
 292                         clock-names = "sata", "sclk_sata";
 293                         phys = <&sata_phy>;
 294                         phy-names = "sata-phy";
 295                         status = "disabled";
 296                 };
 297
 298                 sata_phy: sata-phy@12170000 {
 299                         compatible = "samsung,exynos5250-sata-phy";
 300                         reg = <0x12170000 0x1ff>;
 301                         clocks = <&clock CLK_SATA_PHYCTRL>;
 302                         clock-names = "sata_phyctrl";
 303                         #phy-cells = <0>;
 304                         samsung,syscon-phandle = <&pmu_system_controller>;
 305                         status = "disabled";
 306                 };
 307
 308                 /* i2c_0-3 are defined in exynos5.dtsi */
 309                 i2c_4: i2c@12CA0000 {
 310                         compatible = "samsung,s3c2440-i2c";
 311                         reg = <0x12CA0000 0x100>;
 312                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 313                         #address-cells = <1>;
 314                         #size-cells = <0>;
 315                         clocks = <&clock CLK_I2C4>;
 316                         clock-names = "i2c";
 317                         pinctrl-names = "default";
 318                         pinctrl-0 = <&i2c4_bus>;
 319                         status = "disabled";
 320                 };
 321
 322                 i2c_5: i2c@12CB0000 {
 323                         compatible = "samsung,s3c2440-i2c";
 324                         reg = <0x12CB0000 0x100>;
 325                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 326                         #address-cells = <1>;
 327                         #size-cells = <0>;
 328                         clocks = <&clock CLK_I2C5>;
 329                         clock-names = "i2c";
 330                         pinctrl-names = "default";
 331                         pinctrl-0 = <&i2c5_bus>;
 332                         status = "disabled";
 333                 };
 334
 335                 i2c_6: i2c@12CC0000 {
 336                         compatible = "samsung,s3c2440-i2c";
 337                         reg = <0x12CC0000 0x100>;
 338                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 339                         #address-cells = <1>;
 340                         #size-cells = <0>;
 341                         clocks = <&clock CLK_I2C6>;
 342                         clock-names = "i2c";
 343                         pinctrl-names = "default";
 344                         pinctrl-0 = <&i2c6_bus>;
 345                         status = "disabled";
 346                 };
 347
 348                 i2c_7: i2c@12CD0000 {
 349                         compatible = "samsung,s3c2440-i2c";
 350                         reg = <0x12CD0000 0x100>;
 351                         interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 352                         #address-cells = <1>;
 353                         #size-cells = <0>;
 354                         clocks = <&clock CLK_I2C7>;
 355                         clock-names = "i2c";
 356                         pinctrl-names = "default";
 357                         pinctrl-0 = <&i2c7_bus>;
 358                         status = "disabled";
 359                 };
 360
 361                 i2c_8: i2c@12CE0000 {
 362                         compatible = "samsung,s3c2440-hdmiphy-i2c";
 363                         reg = <0x12CE0000 0x1000>;
 364                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 365                         #address-cells = <1>;
 366                         #size-cells = <0>;
 367                         clocks = <&clock CLK_I2C_HDMI>;
 368                         clock-names = "i2c";
 369                         status = "disabled";
 370                 };
 371
 372                 i2c_9: i2c@121D0000 {
 373                         compatible = "samsung,exynos5-sata-phy-i2c";
 374                         reg = <0x121D0000 0x100>;
 375                         #address-cells = <1>;
 376                         #size-cells = <0>;
 377                         clocks = <&clock CLK_SATA_PHYI2C>;
 378                         clock-names = "i2c";
 379                         status = "disabled";
 380                 };
 381
 382                 spi_0: spi@12d20000 {
 383                         compatible = "samsung,exynos4210-spi";
 384                         status = "disabled";
 385                         reg = <0x12d20000 0x100>;
 386                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 387                         dmas = <&pdma0 5
 388                                 &pdma0 4>;
 389                         dma-names = "tx", "rx";
 390                         #address-cells = <1>;
 391                         #size-cells = <0>;
 392                         clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
 393                         clock-names = "spi", "spi_busclk0";
 394                         pinctrl-names = "default";
 395                         pinctrl-0 = <&spi0_bus>;
 396                 };
 397
 398                 spi_1: spi@12d30000 {
 399                         compatible = "samsung,exynos4210-spi";
 400                         status = "disabled";
 401                         reg = <0x12d30000 0x100>;
 402                         interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 403                         dmas = <&pdma1 5
 404                                 &pdma1 4>;
 405                         dma-names = "tx", "rx";
 406                         #address-cells = <1>;
 407                         #size-cells = <0>;
 408                         clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
 409                         clock-names = "spi", "spi_busclk0";
 410                         pinctrl-names = "default";
 411                         pinctrl-0 = <&spi1_bus>;
 412                 };
 413
 414                 spi_2: spi@12d40000 {
 415                         compatible = "samsung,exynos4210-spi";
 416                         status = "disabled";
 417                         reg = <0x12d40000 0x100>;
 418                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 419                         dmas = <&pdma0 7
 420                                 &pdma0 6>;
 421                         dma-names = "tx", "rx";
 422                         #address-cells = <1>;
 423                         #size-cells = <0>;
 424                         clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
 425                         clock-names = "spi", "spi_busclk0";
 426                         pinctrl-names = "default";
 427                         pinctrl-0 = <&spi2_bus>;
 428                 };
 429
 430                 mmc_0: mmc@12200000 {
 431                         compatible = "samsung,exynos5250-dw-mshc";
 432                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 433                         #address-cells = <1>;
 434                         #size-cells = <0>;
 435                         reg = <0x12200000 0x1000>;
 436                         clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
 437                         clock-names = "biu", "ciu";
 438                         fifo-depth = <0x80>;
 439                         status = "disabled";
 440                 };
 441
 442                 mmc_1: mmc@12210000 {
 443                         compatible = "samsung,exynos5250-dw-mshc";
 444                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 445                         #address-cells = <1>;
 446                         #size-cells = <0>;
 447                         reg = <0x12210000 0x1000>;
 448                         clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
 449                         clock-names = "biu", "ciu";
 450                         fifo-depth = <0x80>;
 451                         status = "disabled";
 452                 };
 453
 454                 mmc_2: mmc@12220000 {
 455                         compatible = "samsung,exynos5250-dw-mshc";
 456                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 457                         #address-cells = <1>;
 458                         #size-cells = <0>;
 459                         reg = <0x12220000 0x1000>;
 460                         clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
 461                         clock-names = "biu", "ciu";
 462                         fifo-depth = <0x80>;
 463                         status = "disabled";
 464                 };
 465
 466                 mmc_3: mmc@12230000 {
 467                         compatible = "samsung,exynos5250-dw-mshc";
 468                         reg = <0x12230000 0x1000>;
 469                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 470                         #address-cells = <1>;
 471                         #size-cells = <0>;
 472                         clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
 473                         clock-names = "biu", "ciu";
 474                         fifo-depth = <0x80>;
 475                         status = "disabled";
 476                 };
 477
 478                 i2s0: i2s@03830000 {
 479                         compatible = "samsung,s5pv210-i2s";
 480                         status = "disabled";
 481                         reg = <0x03830000 0x100>;
 482                         dmas = <&pdma0 10
 483                                 &pdma0 9
 484                                 &pdma0 8>;
 485                         dma-names = "tx", "rx", "tx-sec";
 486                         clocks = <&clock_audss EXYNOS_I2S_BUS>,
 487                                 <&clock_audss EXYNOS_I2S_BUS>,
 488                                 <&clock_audss EXYNOS_SCLK_I2S>;
 489                         clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
 490                         samsung,idma-addr = <0x03000000>;
 491                         pinctrl-names = "default";
 492                         pinctrl-0 = <&i2s0_bus>;
 493                 };
 494
 495                 i2s1: i2s@12D60000 {
 496                         compatible = "samsung,s3c6410-i2s";
 497                         status = "disabled";
 498                         reg = <0x12D60000 0x100>;
 499                         dmas = <&pdma1 12
 500                                 &pdma1 11>;
 501                         dma-names = "tx", "rx";
 502                         clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
 503                         clock-names = "iis", "i2s_opclk0";
 504                         pinctrl-names = "default";
 505                         pinctrl-0 = <&i2s1_bus>;
 506                 };
 507
 508                 i2s2: i2s@12D70000 {
 509                         compatible = "samsung,s3c6410-i2s";
 510                         status = "disabled";
 511                         reg = <0x12D70000 0x100>;
 512                         dmas = <&pdma0 12
 513                                 &pdma0 11>;
 514                         dma-names = "tx", "rx";
 515                         clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
 516                         clock-names = "iis", "i2s_opclk0";
 517                         pinctrl-names = "default";
 518                         pinctrl-0 = <&i2s2_bus>;
 519                 };
 520
 521                 usb_dwc3 {
 522                         compatible = "samsung,exynos5250-dwusb3";
 523                         clocks = <&clock CLK_USB3>;
 524                         clock-names = "usbdrd30";
 525                         #address-cells = <1>;
 526                         #size-cells = <1>;
 527                         ranges;
 528
 529                         usbdrd_dwc3: dwc3@12000000 {
 530                                 compatible = "synopsys,dwc3";
 531                                 reg = <0x12000000 0x10000>;
 532                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 533                                 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
 534                                 phy-names = "usb2-phy", "usb3-phy";
 535                         };
 536                 };
 537
 538                 usbdrd_phy: phy@12100000 {
 539                         compatible = "samsung,exynos5250-usbdrd-phy";
 540                         reg = <0x12100000 0x100>;
 541                         clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
 542                         clock-names = "phy", "ref";
 543                         samsung,pmu-syscon = <&pmu_system_controller>;
 544                         #phy-cells = <1>;
 545                 };
 546
 547                 ehci: usb@12110000 {
 548                         compatible = "samsung,exynos4210-ehci";
 549                         reg = <0x12110000 0x100>;
 550                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 551
 552                         clocks = <&clock CLK_USB2>;
 553                         clock-names = "usbhost";
 554                         #address-cells = <1>;
 555                         #size-cells = <0>;
 556                         port@0 {
 557                                 reg = <0>;
 558                                 phys = <&usb2_phy_gen 1>;
 559                         };
 560                 };
 561
 562                 ohci: usb@12120000 {
 563                         compatible = "samsung,exynos4210-ohci";
 564                         reg = <0x12120000 0x100>;
 565                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 566
 567                         clocks = <&clock CLK_USB2>;
 568                         clock-names = "usbhost";
 569                         #address-cells = <1>;
 570                         #size-cells = <0>;
 571                         port@0 {
 572                                 reg = <0>;
 573                                 phys = <&usb2_phy_gen 1>;
 574                         };
 575                 };
 576
 577                 usb2_phy_gen: phy@12130000 {
 578                         compatible = "samsung,exynos5250-usb2-phy";
 579                         reg = <0x12130000 0x100>;
 580                         clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
 581                         clock-names = "phy", "ref";
 582                         #phy-cells = <1>;
 583                         samsung,sysreg-phandle = <&sysreg_system_controller>;
 584                         samsung,pmureg-phandle = <&pmu_system_controller>;
 585                 };
 586
 587                 amba {
 588                         #address-cells = <1>;
 589                         #size-cells = <1>;
 590                         compatible = "simple-bus";
 591                         interrupt-parent = <&gic>;
 592                         ranges;
 593
 594                         pdma0: pdma@121A0000 {
 595                                 compatible = "arm,pl330", "arm,primecell";
 596                                 reg = <0x121A0000 0x1000>;
 597                                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 598                                 clocks = <&clock CLK_PDMA0>;
 599                                 clock-names = "apb_pclk";
 600                                 #dma-cells = <1>;
 601                                 #dma-channels = <8>;
 602                                 #dma-requests = <32>;
 603                         };
 604
 605                         pdma1: pdma@121B0000 {
 606                                 compatible = "arm,pl330", "arm,primecell";
 607                                 reg = <0x121B0000 0x1000>;
 608                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 609                                 clocks = <&clock CLK_PDMA1>;
 610                                 clock-names = "apb_pclk";
 611                                 #dma-cells = <1>;
 612                                 #dma-channels = <8>;
 613                                 #dma-requests = <32>;
 614                         };
 615
 616                         mdma0: mdma@10800000 {
 617                                 compatible = "arm,pl330", "arm,primecell";
 618                                 reg = <0x10800000 0x1000>;
 619                                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 620                                 clocks = <&clock CLK_MDMA0>;
 621                                 clock-names = "apb_pclk";
 622                                 #dma-cells = <1>;
 623                                 #dma-channels = <8>;
 624                                 #dma-requests = <1>;
 625                         };
 626
 627                         mdma1: mdma@11C10000 {
 628                                 compatible = "arm,pl330", "arm,primecell";
 629                                 reg = <0x11C10000 0x1000>;
 630                                 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
 631                                 clocks = <&clock CLK_MDMA1>;
 632                                 clock-names = "apb_pclk";
 633                                 #dma-cells = <1>;
 634                                 #dma-channels = <8>;
 635                                 #dma-requests = <1>;
 636                         };
 637                 };
 638
 639                 gsc_0:  gsc@13e00000 {
 640                         compatible = "samsung,exynos5-gsc";
 641                         reg = <0x13e00000 0x1000>;
 642                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 643                         power-domains = <&pd_gsc>;
 644                         clocks = <&clock CLK_GSCL0>;
 645                         clock-names = "gscl";
 646                         iommu = <&sysmmu_gsc0>;
 647                 };
 648
 649                 gsc_1:  gsc@13e10000 {
 650                         compatible = "samsung,exynos5-gsc";
 651                         reg = <0x13e10000 0x1000>;
 652                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 653                         power-domains = <&pd_gsc>;
 654                         clocks = <&clock CLK_GSCL1>;
 655                         clock-names = "gscl";
 656                         iommu = <&sysmmu_gsc1>;
 657                 };
 658
 659                 gsc_2:  gsc@13e20000 {
 660                         compatible = "samsung,exynos5-gsc";
 661                         reg = <0x13e20000 0x1000>;
 662                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 663                         power-domains = <&pd_gsc>;
 664                         clocks = <&clock CLK_GSCL2>;
 665                         clock-names = "gscl";
 666                         iommu = <&sysmmu_gsc2>;
 667                 };
 668
 669                 gsc_3:  gsc@13e30000 {
 670                         compatible = "samsung,exynos5-gsc";
 671                         reg = <0x13e30000 0x1000>;
 672                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 673                         power-domains = <&pd_gsc>;
 674                         clocks = <&clock CLK_GSCL3>;
 675                         clock-names = "gscl";
 676                         iommu = <&sysmmu_gsc3>;
 677                 };
 678
 679                 hdmi: hdmi@14530000 {
 680                         compatible = "samsung,exynos4212-hdmi";
 681                         reg = <0x14530000 0x70000>;
 682                         power-domains = <&pd_disp1>;
 683                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 684                         clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
 685                                  <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
 686                                  <&clock CLK_MOUT_HDMI>;
 687                         clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
 688                                         "sclk_hdmiphy", "mout_hdmi";
 689                         samsung,syscon-phandle = <&pmu_system_controller>;
 690                 };
 691
 692                 mixer@14450000 {
 693                         compatible = "samsung,exynos5250-mixer";
 694                         reg = <0x14450000 0x10000>;
 695                         power-domains = <&pd_disp1>;
 696                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 697                         clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
 698                                  <&clock CLK_SCLK_HDMI>;
 699                         clock-names = "mixer", "hdmi", "sclk_hdmi";
 700                         iommus = <&sysmmu_tv>;
 701                 };
 702
 703                 dp_phy: video-phy {
 704                         compatible = "samsung,exynos5250-dp-video-phy";
 705                         samsung,pmu-syscon = <&pmu_system_controller>;
 706                         #phy-cells = <0>;
 707                 };
 708
 709                 adc: adc@12D10000 {
 710                         compatible = "samsung,exynos-adc-v1";
 711                         reg = <0x12D10000 0x100>;
 712                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 713                         clocks = <&clock CLK_ADC>;
 714                         clock-names = "adc";
 715                         #io-channel-cells = <1>;
 716                         io-channel-ranges;
 717                         samsung,syscon-phandle = <&pmu_system_controller>;
 718                         status = "disabled";
 719                 };
 720
 721                 sss@10830000 {
 722                         compatible = "samsung,exynos4210-secss";
 723                         reg = <0x10830000 0x300>;
 724                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 725                         clocks = <&clock CLK_SSS>;
 726                         clock-names = "secss";
 727                 };
 728
 729                 sysmmu_g2d: sysmmu@10A60000 {
 730                         compatible = "samsung,exynos-sysmmu";
 731                         reg = <0x10A60000 0x1000>;
 732                         interrupt-parent = <&combiner>;
 733                         interrupts = <24 5>;
 734                         clock-names = "sysmmu", "master";
 735                         clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>;
 736                         #iommu-cells = <0>;
 737                 };
 738
 739                 sysmmu_mfc_r: sysmmu@11200000 {
 740                         compatible = "samsung,exynos-sysmmu";
 741                         reg = <0x11200000 0x1000>;
 742                         interrupt-parent = <&combiner>;
 743                         interrupts = <6 2>;
 744                         power-domains = <&pd_mfc>;
 745                         clock-names = "sysmmu", "master";
 746                         clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
 747                         #iommu-cells = <0>;
 748                 };
 749
 750                 sysmmu_mfc_l: sysmmu@11210000 {
 751                         compatible = "samsung,exynos-sysmmu";
 752                         reg = <0x11210000 0x1000>;
 753                         interrupt-parent = <&combiner>;
 754                         interrupts = <8 5>;
 755                         power-domains = <&pd_mfc>;
 756                         clock-names = "sysmmu", "master";
 757                         clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
 758                         #iommu-cells = <0>;
 759                 };
 760
 761                 sysmmu_rotator: sysmmu@11D40000 {
 762                         compatible = "samsung,exynos-sysmmu";
 763                         reg = <0x11D40000 0x1000>;
 764                         interrupt-parent = <&combiner>;
 765                         interrupts = <4 0>;
 766                         clock-names = "sysmmu", "master";
 767                         clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
 768                         #iommu-cells = <0>;
 769                 };
 770
 771                 sysmmu_jpeg: sysmmu@11F20000 {
 772                         compatible = "samsung,exynos-sysmmu";
 773                         reg = <0x11F20000 0x1000>;
 774                         interrupt-parent = <&combiner>;
 775                         interrupts = <4 2>;
 776                         power-domains = <&pd_gsc>;
 777                         clock-names = "sysmmu", "master";
 778                         clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
 779                         #iommu-cells = <0>;
 780                 };
 781
 782                 sysmmu_fimc_isp: sysmmu@13260000 {
 783                         compatible = "samsung,exynos-sysmmu";
 784                         reg = <0x13260000 0x1000>;
 785                         interrupt-parent = <&combiner>;
 786                         interrupts = <10 6>;
 787                         clock-names = "sysmmu";
 788                         clocks = <&clock CLK_SMMU_FIMC_ISP>;
 789                         #iommu-cells = <0>;
 790                 };
 791
 792                 sysmmu_fimc_drc: sysmmu@13270000 {
 793                         compatible = "samsung,exynos-sysmmu";
 794                         reg = <0x13270000 0x1000>;
 795                         interrupt-parent = <&combiner>;
 796                         interrupts = <11 6>;
 797                         clock-names = "sysmmu";
 798                         clocks = <&clock CLK_SMMU_FIMC_DRC>;
 799                         #iommu-cells = <0>;
 800                 };
 801
 802                 sysmmu_fimc_fd: sysmmu@132A0000 {
 803                         compatible = "samsung,exynos-sysmmu";
 804                         reg = <0x132A0000 0x1000>;
 805                         interrupt-parent = <&combiner>;
 806                         interrupts = <5 0>;
 807                         clock-names = "sysmmu";
 808                         clocks = <&clock CLK_SMMU_FIMC_FD>;
 809                         #iommu-cells = <0>;
 810                 };
 811
 812                 sysmmu_fimc_scc: sysmmu@13280000 {
 813                         compatible = "samsung,exynos-sysmmu";
 814                         reg = <0x13280000 0x1000>;
 815                         interrupt-parent = <&combiner>;
 816                         interrupts = <5 2>;
 817                         clock-names = "sysmmu";
 818                         clocks = <&clock CLK_SMMU_FIMC_SCC>;
 819                         #iommu-cells = <0>;
 820                 };
 821
 822                 sysmmu_fimc_scp: sysmmu@13290000 {
 823                         compatible = "samsung,exynos-sysmmu";
 824                         reg = <0x13290000 0x1000>;
 825                         interrupt-parent = <&combiner>;
 826                         interrupts = <3 6>;
 827                         clock-names = "sysmmu";
 828                         clocks = <&clock CLK_SMMU_FIMC_SCP>;
 829                         #iommu-cells = <0>;
 830                 };
 831
 832                 sysmmu_fimc_mcuctl: sysmmu@132B0000 {
 833                         compatible = "samsung,exynos-sysmmu";
 834                         reg = <0x132B0000 0x1000>;
 835                         interrupt-parent = <&combiner>;
 836                         interrupts = <5 4>;
 837                         clock-names = "sysmmu";
 838                         clocks = <&clock CLK_SMMU_FIMC_MCU>;
 839                         #iommu-cells = <0>;
 840                 };
 841
 842                 sysmmu_fimc_odc: sysmmu@132C0000 {
 843                         compatible = "samsung,exynos-sysmmu";
 844                         reg = <0x132C0000 0x1000>;
 845                         interrupt-parent = <&combiner>;
 846                         interrupts = <11 0>;
 847                         clock-names = "sysmmu";
 848                         clocks = <&clock CLK_SMMU_FIMC_ODC>;
 849                         #iommu-cells = <0>;
 850                 };
 851
 852                 sysmmu_fimc_dis0: sysmmu@132D0000 {
 853                         compatible = "samsung,exynos-sysmmu";
 854                         reg = <0x132D0000 0x1000>;
 855                         interrupt-parent = <&combiner>;
 856                         interrupts = <10 4>;
 857                         clock-names = "sysmmu";
 858                         clocks = <&clock CLK_SMMU_FIMC_DIS0>;
 859                         #iommu-cells = <0>;
 860                 };
 861
 862                 sysmmu_fimc_dis1: sysmmu@132E0000{
 863                         compatible = "samsung,exynos-sysmmu";
 864                         reg = <0x132E0000 0x1000>;
 865                         interrupt-parent = <&combiner>;
 866                         interrupts = <9 4>;
 867                         clock-names = "sysmmu";
 868                         clocks = <&clock CLK_SMMU_FIMC_DIS1>;
 869                         #iommu-cells = <0>;
 870                 };
 871
 872                 sysmmu_fimc_3dnr: sysmmu@132F0000 {
 873                         compatible = "samsung,exynos-sysmmu";
 874                         reg = <0x132F0000 0x1000>;
 875                         interrupt-parent = <&combiner>;
 876                         interrupts = <5 6>;
 877                         clock-names = "sysmmu";
 878                         clocks = <&clock CLK_SMMU_FIMC_3DNR>;
 879                         #iommu-cells = <0>;
 880                 };
 881
 882                 sysmmu_fimc_lite0: sysmmu@13C40000 {
 883                         compatible = "samsung,exynos-sysmmu";
 884                         reg = <0x13C40000 0x1000>;
 885                         interrupt-parent = <&combiner>;
 886                         interrupts = <3 4>;
 887                         power-domains = <&pd_gsc>;
 888                         clock-names = "sysmmu", "master";
 889                         clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>;
 890                         #iommu-cells = <0>;
 891                 };
 892
 893                 sysmmu_fimc_lite1: sysmmu@13C50000 {
 894                         compatible = "samsung,exynos-sysmmu";
 895                         reg = <0x13C50000 0x1000>;
 896                         interrupt-parent = <&combiner>;
 897                         interrupts = <24 1>;
 898                         power-domains = <&pd_gsc>;
 899                         clock-names = "sysmmu", "master";
 900                         clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>;
 901                         #iommu-cells = <0>;
 902                 };
 903
 904                 sysmmu_gsc0: sysmmu@13E80000 {
 905                         compatible = "samsung,exynos-sysmmu";
 906                         reg = <0x13E80000 0x1000>;
 907                         interrupt-parent = <&combiner>;
 908                         interrupts = <2 0>;
 909                         power-domains = <&pd_gsc>;
 910                         clock-names = "sysmmu", "master";
 911                         clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
 912                         #iommu-cells = <0>;
 913                 };
 914
 915                 sysmmu_gsc1: sysmmu@13E90000 {
 916                         compatible = "samsung,exynos-sysmmu";
 917                         reg = <0x13E90000 0x1000>;
 918                         interrupt-parent = <&combiner>;
 919                         interrupts = <2 2>;
 920                         power-domains = <&pd_gsc>;
 921                         clock-names = "sysmmu", "master";
 922                         clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
 923                         #iommu-cells = <0>;
 924                 };
 925
 926                 sysmmu_gsc2: sysmmu@13EA0000 {
 927                         compatible = "samsung,exynos-sysmmu";
 928                         reg = <0x13EA0000 0x1000>;
 929                         interrupt-parent = <&combiner>;
 930                         interrupts = <2 4>;
 931                         power-domains = <&pd_gsc>;
 932                         clock-names = "sysmmu", "master";
 933                         clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>;
 934                         #iommu-cells = <0>;
 935                 };
 936
 937                 sysmmu_gsc3: sysmmu@13EB0000 {
 938                         compatible = "samsung,exynos-sysmmu";
 939                         reg = <0x13EB0000 0x1000>;
 940                         interrupt-parent = <&combiner>;
 941                         interrupts = <2 6>;
 942                         power-domains = <&pd_gsc>;
 943                         clock-names = "sysmmu", "master";
 944                         clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>;
 945                         #iommu-cells = <0>;
 946                 };
 947
 948                 sysmmu_fimd1: sysmmu@14640000 {
 949                         compatible = "samsung,exynos-sysmmu";
 950                         reg = <0x14640000 0x1000>;
 951                         interrupt-parent = <&combiner>;
 952                         interrupts = <3 2>;
 953                         power-domains = <&pd_disp1>;
 954                         clock-names = "sysmmu", "master";
 955                         clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
 956                         #iommu-cells = <0>;
 957                 };
 958
 959                 sysmmu_tv: sysmmu@14650000 {
 960                         compatible = "samsung,exynos-sysmmu";
 961                         reg = <0x14650000 0x1000>;
 962                         interrupt-parent = <&combiner>;
 963                         interrupts = <7 4>;
 964                         power-domains = <&pd_disp1>;
 965                         clock-names = "sysmmu", "master";
 966                         clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
 967                         #iommu-cells = <0>;
 968                 };
 969         };
 970
 971         thermal-zones {
 972                 cpu_thermal: cpu-thermal {
 973                         polling-delay-passive = <0>;
 974                         polling-delay = <0>;
 975                         thermal-sensors = <&tmu 0>;
 976
 977                         cooling-maps {
 978                                 map0 {
 979                                      /* Corresponds to 800MHz at freq_table */
 980                                      cooling-device = <&cpu0 9 9>;
 981                                 };
 982                                 map1 {
 983                                      /* Corresponds to 200MHz at freq_table */
 984                                      cooling-device = <&cpu0 15 15>;
 985                                };
 986                        };
 987                 };
 988         };
 989 };
 990
 991 &dp {
 992         power-domains = <&pd_disp1>;
 993         clocks = <&clock CLK_DP>;
 994         clock-names = "dp";
 995         phys = <&dp_phy>;
 996         phy-names = "dp";
 997 };
 998
 999 &fimd {
1000         power-domains = <&pd_disp1>;
1001         clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1002         clock-names = "sclk_fimd", "fimd";
1003         iommus = <&sysmmu_fimd1>;
1004 };
1005
1006 &i2c_0 {
1007         clocks = <&clock CLK_I2C0>;
1008         clock-names = "i2c";
1009         pinctrl-names = "default";
1010         pinctrl-0 = <&i2c0_bus>;
1011 };
1012
1013 &i2c_1 {
1014         clocks = <&clock CLK_I2C1>;
1015         clock-names = "i2c";
1016         pinctrl-names = "default";
1017         pinctrl-0 = <&i2c1_bus>;
1018 };
1019
1020 &i2c_2 {
1021         clocks = <&clock CLK_I2C2>;
1022         clock-names = "i2c";
1023         pinctrl-names = "default";
1024         pinctrl-0 = <&i2c2_bus>;
1025 };
1026
1027 &i2c_3 {
1028         clocks = <&clock CLK_I2C3>;
1029         clock-names = "i2c";
1030         pinctrl-names = "default";
1031         pinctrl-0 = <&i2c3_bus>;
1032 };
1033
1034 &pwm {
1035         clocks = <&clock CLK_PWM>;
1036         clock-names = "timers";
1037 };
1038
1039 &rtc {
1040         clocks = <&clock CLK_RTC>;
1041         clock-names = "rtc";
1042         interrupt-parent = <&pmu_system_controller>;
1043         status = "disabled";
1044 };
1045
1046 &serial_0 {
1047         clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1048         clock-names = "uart", "clk_uart_baud0";
1049         dmas = <&pdma0 13>, <&pdma0 14>;
1050         dma-names = "rx", "tx";
1051 };
1052
1053 &serial_1 {
1054         clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1055         clock-names = "uart", "clk_uart_baud0";
1056         dmas = <&pdma1 15>, <&pdma1 16>;
1057         dma-names = "rx", "tx";
1058 };
1059
1060 &serial_2 {
1061         clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1062         clock-names = "uart", "clk_uart_baud0";
1063         dmas = <&pdma0 15>, <&pdma0 16>;
1064         dma-names = "rx", "tx";
1065 };
1066
1067 &serial_3 {
1068         clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1069         clock-names = "uart", "clk_uart_baud0";
1070         dmas = <&pdma1 17>, <&pdma1 18>;
1071         dma-names = "rx", "tx";
1072 };
1073
1074 #include "exynos5250-pinctrl.dtsi"