1 // SPDX-License-Identifier: GPL-2.0
3 * SAMSUNG EXYNOS5410 SoC device tree source
5 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
8 * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
9 * EXYNOS5410 based board files can include this file and provide
10 * values for board specfic bindings.
13 #include "exynos54xx.dtsi"
14 #include "exynos-syscon-restart.dtsi"
15 #include <dt-bindings/clock/exynos5410.h>
16 #include <dt-bindings/clock/exynos-audss-clk.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 compatible = "samsung,exynos5410", "samsung,exynos5";
21 interrupt-parent = <&gic>;
24 pinctrl0 = &pinctrl_0;
25 pinctrl1 = &pinctrl_1;
26 pinctrl2 = &pinctrl_2;
27 pinctrl3 = &pinctrl_3;
36 compatible = "arm,cortex-a15";
38 clock-frequency = <1600000000>;
43 compatible = "arm,cortex-a15";
45 clock-frequency = <1600000000>;
50 compatible = "arm,cortex-a15";
52 clock-frequency = <1600000000>;
57 compatible = "arm,cortex-a15";
59 clock-frequency = <1600000000>;
64 compatible = "simple-bus";
69 pmu_system_controller: system-controller@10040000 {
70 compatible = "samsung,exynos5410-pmu", "syscon";
71 reg = <0x10040000 0x5000>;
72 clock-names = "clkout16";
77 clock: clock-controller@10010000 {
78 compatible = "samsung,exynos5410-clock";
79 reg = <0x10010000 0x30000>;
83 clock_audss: audss-clock-controller@3810000 {
84 compatible = "samsung,exynos5410-audss-clock";
85 reg = <0x03810000 0x0C>;
87 clocks = <&fin_pll>, <&clock CLK_FOUT_EPLL>;
88 clock-names = "pll_ref", "pll_in";
91 tmu_cpu0: tmu@10060000 {
92 compatible = "samsung,exynos5420-tmu";
93 reg = <0x10060000 0x100>;
94 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
95 clocks = <&clock CLK_TMU>;
96 clock-names = "tmu_apbif";
97 #include "exynos4412-tmu-sensor-conf.dtsi"
100 tmu_cpu1: tmu@10064000 {
101 compatible = "samsung,exynos5420-tmu";
102 reg = <0x10064000 0x100>;
103 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
104 clocks = <&clock CLK_TMU>;
105 clock-names = "tmu_apbif";
106 #include "exynos4412-tmu-sensor-conf.dtsi"
109 tmu_cpu2: tmu@10068000 {
110 compatible = "samsung,exynos5420-tmu";
111 reg = <0x10068000 0x100>;
112 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
113 clocks = <&clock CLK_TMU>;
114 clock-names = "tmu_apbif";
115 #include "exynos4412-tmu-sensor-conf.dtsi"
118 tmu_cpu3: tmu@1006c000 {
119 compatible = "samsung,exynos5420-tmu";
120 reg = <0x1006c000 0x100>;
121 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
122 clocks = <&clock CLK_TMU>;
123 clock-names = "tmu_apbif";
124 #include "exynos4412-tmu-sensor-conf.dtsi"
127 mmc_0: mmc@12200000 {
128 compatible = "samsung,exynos5250-dw-mshc";
129 reg = <0x12200000 0x1000>;
130 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
131 #address-cells = <1>;
133 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
134 clock-names = "biu", "ciu";
139 mmc_1: mmc@12210000 {
140 compatible = "samsung,exynos5250-dw-mshc";
141 reg = <0x12210000 0x1000>;
142 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
143 #address-cells = <1>;
145 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
146 clock-names = "biu", "ciu";
151 mmc_2: mmc@12220000 {
152 compatible = "samsung,exynos5250-dw-mshc";
153 reg = <0x12220000 0x1000>;
154 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
155 #address-cells = <1>;
157 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
158 clock-names = "biu", "ciu";
163 pinctrl_0: pinctrl@13400000 {
164 compatible = "samsung,exynos5410-pinctrl";
165 reg = <0x13400000 0x1000>;
166 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
168 wakeup-interrupt-controller {
169 compatible = "samsung,exynos4210-wakeup-eint";
170 interrupt-parent = <&gic>;
171 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
175 pinctrl_1: pinctrl@14000000 {
176 compatible = "samsung,exynos5410-pinctrl";
177 reg = <0x14000000 0x1000>;
178 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
181 pinctrl_2: pinctrl@10d10000 {
182 compatible = "samsung,exynos5410-pinctrl";
183 reg = <0x10d10000 0x1000>;
184 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
187 pinctrl_3: pinctrl@3860000 {
188 compatible = "samsung,exynos5410-pinctrl";
189 reg = <0x03860000 0x1000>;
190 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
194 #address-cells = <1>;
196 compatible = "simple-bus";
197 interrupt-parent = <&gic>;
200 pdma0: pdma@12680000 {
201 compatible = "arm,pl330", "arm,primecell";
202 reg = <0x121A0000 0x1000>;
203 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
204 clocks = <&clock CLK_PDMA0>;
205 clock-names = "apb_pclk";
208 #dma-requests = <32>;
211 pdma1: pdma@12690000 {
212 compatible = "arm,pl330", "arm,primecell";
213 reg = <0x121B0000 0x1000>;
214 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
215 clocks = <&clock CLK_PDMA1>;
216 clock-names = "apb_pclk";
219 #dma-requests = <32>;
223 audi2s0: i2s@3830000 {
224 compatible = "samsung,exynos5420-i2s";
225 reg = <0x03830000 0x100>;
229 dma-names = "tx", "rx", "tx-sec";
230 clocks = <&clock_audss EXYNOS_I2S_BUS>,
231 <&clock_audss EXYNOS_I2S_BUS>,
232 <&clock_audss EXYNOS_SCLK_I2S>;
233 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
235 clock-output-names = "i2s_cdclk0";
236 #sound-dai-cells = <1>;
237 samsung,idma-addr = <0x03000000>;
238 pinctrl-names = "default";
239 pinctrl-0 = <&audi2s0_bus>;
245 cpu0_thermal: cpu0-thermal {
246 thermal-sensors = <&tmu_cpu0>;
247 #include "exynos5420-trip-points.dtsi"
249 cpu1_thermal: cpu1-thermal {
250 thermal-sensors = <&tmu_cpu1>;
251 #include "exynos5420-trip-points.dtsi"
253 cpu2_thermal: cpu2-thermal {
254 thermal-sensors = <&tmu_cpu2>;
255 #include "exynos5420-trip-points.dtsi"
257 cpu3_thermal: cpu3-thermal {
258 thermal-sensors = <&tmu_cpu3>;
259 #include "exynos5420-trip-points.dtsi"
265 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
270 clocks = <&clock CLK_I2C0>;
272 pinctrl-names = "default";
273 pinctrl-0 = <&i2c0_bus>;
277 clocks = <&clock CLK_I2C1>;
279 pinctrl-names = "default";
280 pinctrl-0 = <&i2c1_bus>;
284 clocks = <&clock CLK_I2C2>;
286 pinctrl-names = "default";
287 pinctrl-0 = <&i2c2_bus>;
291 clocks = <&clock CLK_I2C3>;
293 pinctrl-names = "default";
294 pinctrl-0 = <&i2c3_bus>;
298 clocks = <&clock CLK_USI0>;
299 clock-names = "hsi2c";
300 pinctrl-names = "default";
301 pinctrl-0 = <&i2c4_hs_bus>;
305 clocks = <&clock CLK_USI1>;
306 clock-names = "hsi2c";
307 pinctrl-names = "default";
308 pinctrl-0 = <&i2c5_hs_bus>;
312 clocks = <&clock CLK_USI2>;
313 clock-names = "hsi2c";
314 pinctrl-names = "default";
315 pinctrl-0 = <&i2c6_hs_bus>;
319 clocks = <&clock CLK_USI3>;
320 clock-names = "hsi2c";
321 pinctrl-names = "default";
322 pinctrl-0 = <&i2c7_hs_bus>;
326 clocks = <&fin_pll>, <&clock CLK_MCT>;
327 clock-names = "fin_pll", "mct";
331 clocks = <&clock CLK_SSS>;
332 clock-names = "secss";
336 clocks = <&clock CLK_PWM>;
337 clock-names = "timers";
341 clocks = <&clock CLK_RTC>;
347 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
348 clock-names = "uart", "clk_uart_baud0";
349 dmas = <&pdma0 13>, <&pdma0 14>;
350 dma-names = "rx", "tx";
354 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
355 clock-names = "uart", "clk_uart_baud0";
356 dmas = <&pdma1 15>, <&pdma1 16>;
357 dma-names = "rx", "tx";
361 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
362 clock-names = "uart", "clk_uart_baud0";
363 dmas = <&pdma0 15>, <&pdma0 16>;
364 dma-names = "rx", "tx";
368 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
369 clock-names = "uart", "clk_uart_baud0";
370 dmas = <&pdma1 17>, <&pdma1 18>;
371 dma-names = "rx", "tx";
375 clocks = <&clock CLK_SSS>;
376 clock-names = "secss";
380 #address-cells = <2>;
382 ranges = <0 0 0x04000000 0x20000
383 1 0 0x05000000 0x20000
384 2 0 0x06000000 0x20000
385 3 0 0x07000000 0x20000>;
389 clocks = <&clock CLK_SSS>;
390 clock-names = "secss";
394 clocks = <&clock CLK_USBD300>;
395 clock-names = "usbdrd30";
399 clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
400 clock-names = "phy", "ref";
401 samsung,pmu-syscon = <&pmu_system_controller>;
405 clocks = <&clock CLK_USBD301>;
406 clock-names = "usbdrd30";
410 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
414 clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
415 clock-names = "phy", "ref";
416 samsung,pmu-syscon = <&pmu_system_controller>;
420 clocks = <&clock CLK_USBH20>;
421 clock-names = "usbhost";
425 clocks = <&clock CLK_USBH20>;
426 clock-names = "usbhost";
430 clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
431 clock-names = "phy", "ref";
432 samsung,sysreg-phandle = <&sysreg_system_controller>;
433 samsung,pmureg-phandle = <&pmu_system_controller>;
437 clocks = <&clock CLK_WDT>;
438 clock-names = "watchdog";
439 samsung,syscon-phandle = <&pmu_system_controller>;
442 #include "exynos5410-pinctrl.dtsi"