sys/gnu/dts/arm/exynos5410.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * SAMSUNG EXYNOS5410 SoC device tree source
   4  *
   5  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   6  *              http://www.samsung.com
   7  *
   8  * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
   9  * EXYNOS5410 based board files can include this file and provide
  10  * values for board specfic bindings.
  11  */
  12
  13 #include "exynos54xx.dtsi"
  14 #include "exynos-syscon-restart.dtsi"
  15 #include <dt-bindings/clock/exynos5410.h>
  16 #include <dt-bindings/clock/exynos-audss-clk.h>
  17 #include <dt-bindings/interrupt-controller/arm-gic.h>
  18
  19 / {
  20         compatible = "samsung,exynos5410", "samsung,exynos5";
  21         interrupt-parent = <&gic>;
  22
  23         aliases {
  24                 pinctrl0 = &pinctrl_0;
  25                 pinctrl1 = &pinctrl_1;
  26                 pinctrl2 = &pinctrl_2;
  27                 pinctrl3 = &pinctrl_3;
  28         };
  29
  30         cpus {
  31                 #address-cells = <1>;
  32                 #size-cells = <0>;
  33
  34                 cpu0: cpu@0 {
  35                         device_type = "cpu";
  36                         compatible = "arm,cortex-a15";
  37                         reg = <0x0>;
  38                         clock-frequency = <1600000000>;
  39                 };
  40
  41                 cpu1: cpu@1 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a15";
  44                         reg = <0x1>;
  45                         clock-frequency = <1600000000>;
  46                 };
  47
  48                 cpu2: cpu@2 {
  49                         device_type = "cpu";
  50                         compatible = "arm,cortex-a15";
  51                         reg = <0x2>;
  52                         clock-frequency = <1600000000>;
  53                 };
  54
  55                 cpu3: cpu@3 {
  56                         device_type = "cpu";
  57                         compatible = "arm,cortex-a15";
  58                         reg = <0x3>;
  59                         clock-frequency = <1600000000>;
  60                 };
  61         };
  62
  63         soc: soc {
  64                 compatible = "simple-bus";
  65                 #address-cells = <1>;
  66                 #size-cells = <1>;
  67                 ranges;
  68
  69                 pmu_system_controller: system-controller@10040000 {
  70                         compatible = "samsung,exynos5410-pmu", "syscon";
  71                         reg = <0x10040000 0x5000>;
  72                         clock-names = "clkout16";
  73                         clocks = <&fin_pll>;
  74                         #clock-cells = <1>;
  75                 };
  76
  77                 clock: clock-controller@10010000 {
  78                         compatible = "samsung,exynos5410-clock";
  79                         reg = <0x10010000 0x30000>;
  80                         #clock-cells = <1>;
  81                 };
  82
  83                 clock_audss: audss-clock-controller@3810000 {
  84                         compatible = "samsung,exynos5410-audss-clock";
  85                         reg = <0x03810000 0x0C>;
  86                         #clock-cells = <1>;
  87                         clocks = <&fin_pll>, <&clock CLK_FOUT_EPLL>;
  88                         clock-names = "pll_ref", "pll_in";
  89                 };
  90
  91                 tmu_cpu0: tmu@10060000 {
  92                         compatible = "samsung,exynos5420-tmu";
  93                         reg = <0x10060000 0x100>;
  94                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
  95                         clocks = <&clock CLK_TMU>;
  96                         clock-names = "tmu_apbif";
  97                         #include "exynos4412-tmu-sensor-conf.dtsi"
  98                 };
  99
 100                 tmu_cpu1: tmu@10064000 {
 101                         compatible = "samsung,exynos5420-tmu";
 102                         reg = <0x10064000 0x100>;
 103                         interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
 104                         clocks = <&clock CLK_TMU>;
 105                         clock-names = "tmu_apbif";
 106                         #include "exynos4412-tmu-sensor-conf.dtsi"
 107                 };
 108
 109                 tmu_cpu2: tmu@10068000 {
 110                         compatible = "samsung,exynos5420-tmu";
 111                         reg = <0x10068000 0x100>;
 112                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 113                         clocks = <&clock CLK_TMU>;
 114                         clock-names = "tmu_apbif";
 115                         #include "exynos4412-tmu-sensor-conf.dtsi"
 116                 };
 117
 118                 tmu_cpu3: tmu@1006c000 {
 119                         compatible = "samsung,exynos5420-tmu";
 120                         reg = <0x1006c000 0x100>;
 121                         interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
 122                         clocks = <&clock CLK_TMU>;
 123                         clock-names = "tmu_apbif";
 124                         #include "exynos4412-tmu-sensor-conf.dtsi"
 125                 };
 126
 127                 mmc_0: mmc@12200000 {
 128                         compatible = "samsung,exynos5250-dw-mshc";
 129                         reg = <0x12200000 0x1000>;
 130                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 131                         #address-cells = <1>;
 132                         #size-cells = <0>;
 133                         clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
 134                         clock-names = "biu", "ciu";
 135                         fifo-depth = <0x80>;
 136                         status = "disabled";
 137                 };
 138
 139                 mmc_1: mmc@12210000 {
 140                         compatible = "samsung,exynos5250-dw-mshc";
 141                         reg = <0x12210000 0x1000>;
 142                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 143                         #address-cells = <1>;
 144                         #size-cells = <0>;
 145                         clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
 146                         clock-names = "biu", "ciu";
 147                         fifo-depth = <0x80>;
 148                         status = "disabled";
 149                 };
 150
 151                 mmc_2: mmc@12220000 {
 152                         compatible = "samsung,exynos5250-dw-mshc";
 153                         reg = <0x12220000 0x1000>;
 154                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 155                         #address-cells = <1>;
 156                         #size-cells = <0>;
 157                         clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
 158                         clock-names = "biu", "ciu";
 159                         fifo-depth = <0x80>;
 160                         status = "disabled";
 161                 };
 162
 163                 pinctrl_0: pinctrl@13400000 {
 164                         compatible = "samsung,exynos5410-pinctrl";
 165                         reg = <0x13400000 0x1000>;
 166                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 167
 168                         wakeup-interrupt-controller {
 169                                 compatible = "samsung,exynos4210-wakeup-eint";
 170                                 interrupt-parent = <&gic>;
 171                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 172                         };
 173                 };
 174
 175                 pinctrl_1: pinctrl@14000000 {
 176                         compatible = "samsung,exynos5410-pinctrl";
 177                         reg = <0x14000000 0x1000>;
 178                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 179                 };
 180
 181                 pinctrl_2: pinctrl@10d10000 {
 182                         compatible = "samsung,exynos5410-pinctrl";
 183                         reg = <0x10d10000 0x1000>;
 184                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 185                 };
 186
 187                 pinctrl_3: pinctrl@3860000 {
 188                         compatible = "samsung,exynos5410-pinctrl";
 189                         reg = <0x03860000 0x1000>;
 190                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 191                 };
 192
 193                 amba {
 194                         #address-cells = <1>;
 195                         #size-cells = <1>;
 196                         compatible = "simple-bus";
 197                         interrupt-parent = <&gic>;
 198                         ranges;
 199
 200                         pdma0: pdma@12680000 {
 201                                 compatible = "arm,pl330", "arm,primecell";
 202                                 reg = <0x121A0000 0x1000>;
 203                                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 204                                 clocks = <&clock CLK_PDMA0>;
 205                                 clock-names = "apb_pclk";
 206                                 #dma-cells = <1>;
 207                                 #dma-channels = <8>;
 208                                 #dma-requests = <32>;
 209                         };
 210
 211                         pdma1: pdma@12690000 {
 212                                 compatible = "arm,pl330", "arm,primecell";
 213                                 reg = <0x121B0000 0x1000>;
 214                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 215                                 clocks = <&clock CLK_PDMA1>;
 216                                 clock-names = "apb_pclk";
 217                                 #dma-cells = <1>;
 218                                 #dma-channels = <8>;
 219                                 #dma-requests = <32>;
 220                         };
 221                 };
 222
 223                 audi2s0: i2s@3830000 {
 224                         compatible = "samsung,exynos5420-i2s";
 225                         reg = <0x03830000 0x100>;
 226                         dmas = <&pdma0 10
 227                                 &pdma0 9
 228                                 &pdma0 8>;
 229                         dma-names = "tx", "rx", "tx-sec";
 230                         clocks = <&clock_audss EXYNOS_I2S_BUS>,
 231                                 <&clock_audss EXYNOS_I2S_BUS>,
 232                                 <&clock_audss EXYNOS_SCLK_I2S>;
 233                         clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
 234                         #clock-cells = <1>;
 235                         clock-output-names = "i2s_cdclk0";
 236                         #sound-dai-cells = <1>;
 237                         samsung,idma-addr = <0x03000000>;
 238                         pinctrl-names = "default";
 239                         pinctrl-0 = <&audi2s0_bus>;
 240                         status = "disabled";
 241                 };
 242         };
 243
 244         thermal-zones {
 245                 cpu0_thermal: cpu0-thermal {
 246                         thermal-sensors = <&tmu_cpu0>;
 247                         #include "exynos5420-trip-points.dtsi"
 248                 };
 249                 cpu1_thermal: cpu1-thermal {
 250                        thermal-sensors = <&tmu_cpu1>;
 251                        #include "exynos5420-trip-points.dtsi"
 252                 };
 253                 cpu2_thermal: cpu2-thermal {
 254                        thermal-sensors = <&tmu_cpu2>;
 255                        #include "exynos5420-trip-points.dtsi"
 256                 };
 257                 cpu3_thermal: cpu3-thermal {
 258                        thermal-sensors = <&tmu_cpu3>;
 259                        #include "exynos5420-trip-points.dtsi"
 260                 };
 261         };
 262 };
 263
 264 &arm_a15_pmu {
 265         interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 266         status = "okay";
 267 };
 268
 269 &i2c_0 {
 270         clocks = <&clock CLK_I2C0>;
 271         clock-names = "i2c";
 272         pinctrl-names = "default";
 273         pinctrl-0 = <&i2c0_bus>;
 274 };
 275
 276 &i2c_1 {
 277         clocks = <&clock CLK_I2C1>;
 278         clock-names = "i2c";
 279         pinctrl-names = "default";
 280         pinctrl-0 = <&i2c1_bus>;
 281 };
 282
 283 &i2c_2 {
 284         clocks = <&clock CLK_I2C2>;
 285         clock-names = "i2c";
 286         pinctrl-names = "default";
 287         pinctrl-0 = <&i2c2_bus>;
 288 };
 289
 290 &i2c_3 {
 291         clocks = <&clock CLK_I2C3>;
 292         clock-names = "i2c";
 293         pinctrl-names = "default";
 294         pinctrl-0 = <&i2c3_bus>;
 295 };
 296
 297 &hsi2c_4 {
 298         clocks = <&clock CLK_USI0>;
 299         clock-names = "hsi2c";
 300         pinctrl-names = "default";
 301         pinctrl-0 = <&i2c4_hs_bus>;
 302 };
 303
 304 &hsi2c_5 {
 305         clocks = <&clock CLK_USI1>;
 306         clock-names = "hsi2c";
 307         pinctrl-names = "default";
 308         pinctrl-0 = <&i2c5_hs_bus>;
 309 };
 310
 311 &hsi2c_6 {
 312         clocks = <&clock CLK_USI2>;
 313         clock-names = "hsi2c";
 314         pinctrl-names = "default";
 315         pinctrl-0 = <&i2c6_hs_bus>;
 316 };
 317
 318 &hsi2c_7 {
 319         clocks = <&clock CLK_USI3>;
 320         clock-names = "hsi2c";
 321         pinctrl-names = "default";
 322         pinctrl-0 = <&i2c7_hs_bus>;
 323 };
 324
 325 &mct {
 326         clocks = <&fin_pll>, <&clock CLK_MCT>;
 327         clock-names = "fin_pll", "mct";
 328 };
 329
 330 &prng {
 331         clocks = <&clock CLK_SSS>;
 332         clock-names = "secss";
 333 };
 334
 335 &pwm {
 336         clocks = <&clock CLK_PWM>;
 337         clock-names = "timers";
 338 };
 339
 340 &rtc {
 341         clocks = <&clock CLK_RTC>;
 342         clock-names = "rtc";
 343         status = "disabled";
 344 };
 345
 346 &serial_0 {
 347         clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
 348         clock-names = "uart", "clk_uart_baud0";
 349         dmas = <&pdma0 13>, <&pdma0 14>;
 350         dma-names = "rx", "tx";
 351 };
 352
 353 &serial_1 {
 354         clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
 355         clock-names = "uart", "clk_uart_baud0";
 356         dmas = <&pdma1 15>, <&pdma1 16>;
 357         dma-names = "rx", "tx";
 358 };
 359
 360 &serial_2 {
 361         clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
 362         clock-names = "uart", "clk_uart_baud0";
 363         dmas = <&pdma0 15>, <&pdma0 16>;
 364         dma-names = "rx", "tx";
 365 };
 366
 367 &serial_3 {
 368         clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
 369         clock-names = "uart", "clk_uart_baud0";
 370         dmas = <&pdma1 17>, <&pdma1 18>;
 371         dma-names = "rx", "tx";
 372 };
 373
 374 &sss {
 375         clocks = <&clock CLK_SSS>;
 376         clock-names = "secss";
 377 };
 378
 379 &sromc {
 380         #address-cells = <2>;
 381         #size-cells = <1>;
 382         ranges = <0 0 0x04000000 0x20000
 383                   1 0 0x05000000 0x20000
 384                   2 0 0x06000000 0x20000
 385                   3 0 0x07000000 0x20000>;
 386 };
 387
 388 &trng {
 389         clocks = <&clock CLK_SSS>;
 390         clock-names = "secss";
 391 };
 392
 393 &usbdrd3_0 {
 394         clocks = <&clock CLK_USBD300>;
 395         clock-names = "usbdrd30";
 396 };
 397
 398 &usbdrd_phy0 {
 399         clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
 400         clock-names = "phy", "ref";
 401         samsung,pmu-syscon = <&pmu_system_controller>;
 402 };
 403
 404 &usbdrd3_1 {
 405         clocks = <&clock CLK_USBD301>;
 406         clock-names = "usbdrd30";
 407 };
 408
 409 &usbdrd_dwc3_1 {
 410         interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
 411 };
 412
 413 &usbdrd_phy1 {
 414         clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
 415         clock-names = "phy", "ref";
 416         samsung,pmu-syscon = <&pmu_system_controller>;
 417 };
 418
 419 &usbhost1 {
 420         clocks = <&clock CLK_USBH20>;
 421         clock-names = "usbhost";
 422 };
 423
 424 &usbhost2 {
 425         clocks = <&clock CLK_USBH20>;
 426         clock-names = "usbhost";
 427 };
 428
 429 &usb2_phy {
 430         clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
 431         clock-names = "phy", "ref";
 432         samsung,sysreg-phandle = <&sysreg_system_controller>;
 433         samsung,pmureg-phandle = <&pmu_system_controller>;
 434 };
 435
 436 &watchdog {
 437         clocks = <&clock CLK_WDT>;
 438         clock-names = "watchdog";
 439         samsung,syscon-phandle = <&pmu_system_controller>;
 440 };
 441
 442 #include "exynos5410-pinctrl.dtsi"