1 // SPDX-License-Identifier: GPL-2.0
3 * SAMSUNG EXYNOS5420 SoC cpu device tree source
5 * Copyright (c) 2015 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
8 * This file provides desired ordering for Exynos5420 and Exynos5800
9 * boards: CPU[0123] being the A15.
11 * The Exynos5420, 5422 and 5800 actually share the same CPU configuration
12 * but particular boards choose different booting order.
14 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
15 * booting cluster (big or LITTLE) is chosen by IROM code by reading
16 * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
17 * from the LITTLE: Cortex-A7.
27 compatible = "arm,cortex-a15";
29 clocks = <&clock CLK_ARM_CLK>;
30 clock-frequency = <1800000000>;
31 cci-control-port = <&cci_control1>;
32 operating-points-v2 = <&cluster_a15_opp_table>;
33 #cooling-cells = <2>; /* min followed by max */
34 capacity-dmips-mhz = <1024>;
39 compatible = "arm,cortex-a15";
41 clock-frequency = <1800000000>;
42 cci-control-port = <&cci_control1>;
43 operating-points-v2 = <&cluster_a15_opp_table>;
44 #cooling-cells = <2>; /* min followed by max */
45 capacity-dmips-mhz = <1024>;
50 compatible = "arm,cortex-a15";
52 clock-frequency = <1800000000>;
53 cci-control-port = <&cci_control1>;
54 operating-points-v2 = <&cluster_a15_opp_table>;
55 #cooling-cells = <2>; /* min followed by max */
56 capacity-dmips-mhz = <1024>;
61 compatible = "arm,cortex-a15";
63 clock-frequency = <1800000000>;
64 cci-control-port = <&cci_control1>;
65 operating-points-v2 = <&cluster_a15_opp_table>;
66 #cooling-cells = <2>; /* min followed by max */
67 capacity-dmips-mhz = <1024>;
72 compatible = "arm,cortex-a7";
74 clocks = <&clock CLK_KFC_CLK>;
75 clock-frequency = <1000000000>;
76 cci-control-port = <&cci_control0>;
77 operating-points-v2 = <&cluster_a7_opp_table>;
78 #cooling-cells = <2>; /* min followed by max */
79 capacity-dmips-mhz = <539>;
84 compatible = "arm,cortex-a7";
86 clock-frequency = <1000000000>;
87 cci-control-port = <&cci_control0>;
88 operating-points-v2 = <&cluster_a7_opp_table>;
89 #cooling-cells = <2>; /* min followed by max */
90 capacity-dmips-mhz = <539>;
95 compatible = "arm,cortex-a7";
97 clock-frequency = <1000000000>;
98 cci-control-port = <&cci_control0>;
99 operating-points-v2 = <&cluster_a7_opp_table>;
100 #cooling-cells = <2>; /* min followed by max */
101 capacity-dmips-mhz = <539>;
106 compatible = "arm,cortex-a7";
108 clock-frequency = <1000000000>;
109 cci-control-port = <&cci_control0>;
110 operating-points-v2 = <&cluster_a7_opp_table>;
111 #cooling-cells = <2>; /* min followed by max */
112 capacity-dmips-mhz = <539>;
118 interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
123 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;