1 // SPDX-License-Identifier: GPL-2.0
3 * SAMSUNG EXYNOS5422 SoC cpu device tree source
5 * Copyright (c) 2015 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
8 * This file provides desired ordering for Exynos5422: CPU[0123] being the A7.
10 * The Exynos5420, 5422 and 5800 actually share the same CPU configuration
11 * but particular boards choose different booting order.
13 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
14 * booting cluster (big or LITTLE) is chosen by IROM code by reading
15 * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
16 * from the LITTLE: Cortex-A7.
26 compatible = "arm,cortex-a7";
28 clocks = <&clock CLK_KFC_CLK>;
29 clock-frequency = <1000000000>;
30 cci-control-port = <&cci_control0>;
31 operating-points-v2 = <&cluster_a7_opp_table>;
32 #cooling-cells = <2>; /* min followed by max */
33 capacity-dmips-mhz = <539>;
38 compatible = "arm,cortex-a7";
40 clock-frequency = <1000000000>;
41 cci-control-port = <&cci_control0>;
42 operating-points-v2 = <&cluster_a7_opp_table>;
43 #cooling-cells = <2>; /* min followed by max */
44 capacity-dmips-mhz = <539>;
49 compatible = "arm,cortex-a7";
51 clock-frequency = <1000000000>;
52 cci-control-port = <&cci_control0>;
53 operating-points-v2 = <&cluster_a7_opp_table>;
54 #cooling-cells = <2>; /* min followed by max */
55 capacity-dmips-mhz = <539>;
60 compatible = "arm,cortex-a7";
62 clock-frequency = <1000000000>;
63 cci-control-port = <&cci_control0>;
64 operating-points-v2 = <&cluster_a7_opp_table>;
65 #cooling-cells = <2>; /* min followed by max */
66 capacity-dmips-mhz = <539>;
71 compatible = "arm,cortex-a15";
72 clocks = <&clock CLK_ARM_CLK>;
74 clock-frequency = <1800000000>;
75 cci-control-port = <&cci_control1>;
76 operating-points-v2 = <&cluster_a15_opp_table>;
77 #cooling-cells = <2>; /* min followed by max */
78 capacity-dmips-mhz = <1024>;
83 compatible = "arm,cortex-a15";
85 clock-frequency = <1800000000>;
86 cci-control-port = <&cci_control1>;
87 operating-points-v2 = <&cluster_a15_opp_table>;
88 #cooling-cells = <2>; /* min followed by max */
89 capacity-dmips-mhz = <1024>;
94 compatible = "arm,cortex-a15";
96 clock-frequency = <1800000000>;
97 cci-control-port = <&cci_control1>;
98 operating-points-v2 = <&cluster_a15_opp_table>;
99 #cooling-cells = <2>; /* min followed by max */
100 capacity-dmips-mhz = <1024>;
105 compatible = "arm,cortex-a15";
107 clock-frequency = <1800000000>;
108 cci-control-port = <&cci_control1>;
109 operating-points-v2 = <&cluster_a15_opp_table>;
110 #cooling-cells = <2>; /* min followed by max */
111 capacity-dmips-mhz = <1024>;
117 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
122 interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;