2 * SAMSUNG EXYNOS5422 SoC cpu device tree source
4 * Copyright (c) 2015 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * This file provides desired ordering for Exynos5422: CPU[0123] being the A7.
9 * The Exynos5420, 5422 and 5800 actually share the same CPU configuration
10 * but particular boards choose different booting order.
12 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
13 * booting cluster (big or LITTLE) is chosen by IROM code by reading
14 * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
15 * from the LITTLE: Cortex-A7.
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
29 compatible = "arm,cortex-a7";
31 clocks = <&clock CLK_KFC_CLK>;
32 clock-frequency = <1000000000>;
33 cci-control-port = <&cci_control0>;
34 operating-points-v2 = <&cluster_a7_opp_table>;
35 cooling-min-level = <0>;
36 cooling-max-level = <11>;
37 #cooling-cells = <2>; /* min followed by max */
38 capacity-dmips-mhz = <539>;
43 compatible = "arm,cortex-a7";
45 clock-frequency = <1000000000>;
46 cci-control-port = <&cci_control0>;
47 operating-points-v2 = <&cluster_a7_opp_table>;
48 cooling-min-level = <0>;
49 cooling-max-level = <11>;
50 #cooling-cells = <2>; /* min followed by max */
51 capacity-dmips-mhz = <539>;
56 compatible = "arm,cortex-a7";
58 clock-frequency = <1000000000>;
59 cci-control-port = <&cci_control0>;
60 operating-points-v2 = <&cluster_a7_opp_table>;
61 cooling-min-level = <0>;
62 cooling-max-level = <11>;
63 #cooling-cells = <2>; /* min followed by max */
64 capacity-dmips-mhz = <539>;
69 compatible = "arm,cortex-a7";
71 clock-frequency = <1000000000>;
72 cci-control-port = <&cci_control0>;
73 operating-points-v2 = <&cluster_a7_opp_table>;
74 cooling-min-level = <0>;
75 cooling-max-level = <11>;
76 #cooling-cells = <2>; /* min followed by max */
77 capacity-dmips-mhz = <539>;
82 compatible = "arm,cortex-a15";
83 clocks = <&clock CLK_ARM_CLK>;
85 clock-frequency = <1800000000>;
86 cci-control-port = <&cci_control1>;
87 operating-points-v2 = <&cluster_a15_opp_table>;
88 cooling-min-level = <0>;
89 cooling-max-level = <15>;
90 #cooling-cells = <2>; /* min followed by max */
91 capacity-dmips-mhz = <1024>;
96 compatible = "arm,cortex-a15";
98 clock-frequency = <1800000000>;
99 cci-control-port = <&cci_control1>;
100 operating-points-v2 = <&cluster_a15_opp_table>;
101 cooling-min-level = <0>;
102 cooling-max-level = <15>;
103 #cooling-cells = <2>; /* min followed by max */
104 capacity-dmips-mhz = <1024>;
109 compatible = "arm,cortex-a15";
111 clock-frequency = <1800000000>;
112 cci-control-port = <&cci_control1>;
113 operating-points-v2 = <&cluster_a15_opp_table>;
114 cooling-min-level = <0>;
115 cooling-max-level = <15>;
116 #cooling-cells = <2>; /* min followed by max */
117 capacity-dmips-mhz = <1024>;
122 compatible = "arm,cortex-a15";
124 clock-frequency = <1800000000>;
125 cci-control-port = <&cci_control1>;
126 operating-points-v2 = <&cluster_a15_opp_table>;
127 cooling-min-level = <0>;
128 cooling-max-level = <15>;
129 #cooling-cells = <2>; /* min followed by max */
130 capacity-dmips-mhz = <1024>;