1 // SPDX-License-Identifier: GPL-2.0+
3 // Copyright 2016-2018 Vladimir Zapolskiy <vz@mleia.com>
4 // Copyright 2012 Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
10 * The decompressor and also some bootloaders rely on a
11 * pre-existing /chosen node to be available to insert the
12 * command line and merge other ATAGS info.
13 * Also for U-Boot there must be a pre-existing /memory node.
16 memory { device_type = "memory"; };
40 compatible = "arm,arm1136jf-s";
46 avic: interrupt-controller@68000000 {
47 compatible = "fsl,imx31-avic", "fsl,avic";
49 #interrupt-cells = <1>;
50 reg = <0x68000000 0x100000>;
56 compatible = "simple-bus";
57 interrupt-parent = <&avic>;
61 compatible = "mmio-sram";
62 reg = <0x1fffc000 0x4000>;
65 ranges = <0 0x1fffc000 0x4000>;
68 aips@43f00000 { /* AIPS1 */
69 compatible = "fsl,aips-bus", "simple-bus";
72 reg = <0x43f00000 0x100000>;
76 compatible = "fsl,imx31-i2c", "fsl,imx21-i2c";
77 reg = <0x43f80000 0x4000>;
86 compatible = "fsl,imx31-i2c", "fsl,imx21-i2c";
87 reg = <0x43f84000 0x4000>;
96 compatible = "fsl,imx31-pata", "fsl,imx27-pata";
97 reg = <0x43f8c000 0x4000>;
103 uart1: serial@43f90000 {
104 compatible = "fsl,imx31-uart", "fsl,imx21-uart";
105 reg = <0x43f90000 0x4000>;
107 clocks = <&clks 10>, <&clks 30>;
108 clock-names = "ipg", "per";
112 uart2: serial@43f94000 {
113 compatible = "fsl,imx31-uart", "fsl,imx21-uart";
114 reg = <0x43f94000 0x4000>;
116 clocks = <&clks 10>, <&clks 31>;
117 clock-names = "ipg", "per";
122 compatible = "fsl,imx31-i2c", "fsl,imx21-i2c";
123 reg = <0x43f98000 0x4000>;
126 #address-cells = <1>;
132 compatible = "fsl,imx31-cspi";
133 reg = <0x43fa4000 0x4000>;
135 clocks = <&clks 10>, <&clks 53>;
136 clock-names = "ipg", "per";
137 dmas = <&sdma 8 8 0>, <&sdma 9 8 0>;
138 dma-names = "rx", "tx";
139 #address-cells = <1>;
145 compatible = "fsl,imx31-kpp", "fsl,imx21-kpp";
146 reg = <0x43fa8000 0x4000>;
152 uart4: serial@43fb0000 {
153 compatible = "fsl,imx31-uart", "fsl,imx21-uart";
154 reg = <0x43fb0000 0x4000>;
155 clocks = <&clks 10>, <&clks 49>;
156 clock-names = "ipg", "per";
161 uart5: serial@43fb4000 {
162 compatible = "fsl,imx31-uart", "fsl,imx21-uart";
163 reg = <0x43fb4000 0x4000>;
165 clocks = <&clks 10>, <&clks 50>;
166 clock-names = "ipg", "per";
172 compatible = "fsl,spba-bus", "simple-bus";
173 #address-cells = <1>;
175 reg = <0x50000000 0x100000>;
178 sdhci1: sdhci@50004000 {
179 compatible = "fsl,imx31-mmc";
180 reg = <0x50004000 0x4000>;
182 clocks = <&clks 10>, <&clks 20>;
183 clock-names = "ipg", "per";
184 dmas = <&sdma 20 3 0>;
189 sdhci2: sdhci@50008000 {
190 compatible = "fsl,imx31-mmc";
191 reg = <0x50008000 0x4000>;
193 clocks = <&clks 10>, <&clks 21>;
194 clock-names = "ipg", "per";
195 dmas = <&sdma 21 3 0>;
200 uart3: serial@5000c000 {
201 compatible = "fsl,imx31-uart", "fsl,imx21-uart";
202 reg = <0x5000c000 0x4000>;
204 clocks = <&clks 10>, <&clks 48>;
205 clock-names = "ipg", "per";
210 compatible = "fsl,imx31-cspi";
211 reg = <0x50010000 0x4000>;
213 clocks = <&clks 10>, <&clks 54>;
214 clock-names = "ipg", "per";
215 dmas = <&sdma 6 8 0>, <&sdma 7 8 0>;
216 dma-names = "rx", "tx";
217 #address-cells = <1>;
223 compatible = "fsl,imx31-iim", "fsl,imx27-iim";
224 reg = <0x5001c000 0x1000>;
230 aips@53f00000 { /* AIPS2 */
231 compatible = "fsl,aips-bus", "simple-bus";
232 #address-cells = <1>;
234 reg = <0x53f00000 0x100000>;
238 compatible = "fsl,imx31-ccm";
239 reg = <0x53f80000 0x4000>;
240 interrupts = <31>, <53>;
245 compatible = "fsl,imx31-cspi";
246 reg = <0x53f84000 0x4000>;
248 clocks = <&clks 10>, <&clks 28>;
249 clock-names = "ipg", "per";
250 dmas = <&sdma 10 8 0>, <&sdma 11 8 0>;
251 dma-names = "rx", "tx";
252 #address-cells = <1>;
257 gpt: timer@53f90000 {
258 compatible = "fsl,imx31-gpt";
259 reg = <0x53f90000 0x4000>;
261 clocks = <&clks 10>, <&clks 22>;
262 clock-names = "ipg", "per";
265 gpio3: gpio@53fa4000 {
266 compatible = "fsl,imx31-gpio";
267 reg = <0x53fa4000 0x4000>;
271 interrupt-controller;
272 #interrupt-cells = <2>;
276 compatible = "fsl,imx31-rnga";
277 reg = <0x53fb0000 0x4000>;
282 gpio1: gpio@53fcc000 {
283 compatible = "fsl,imx31-gpio";
284 reg = <0x53fcc000 0x4000>;
288 interrupt-controller;
289 #interrupt-cells = <2>;
292 gpio2: gpio@53fd0000 {
293 compatible = "fsl,imx31-gpio";
294 reg = <0x53fd0000 0x4000>;
298 interrupt-controller;
299 #interrupt-cells = <2>;
302 sdma: sdma@53fd4000 {
303 compatible = "fsl,imx31-sdma";
304 reg = <0x53fd4000 0x4000>;
306 clocks = <&clks 10>, <&clks 27>;
307 clock-names = "ipg", "ahb";
309 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx31.bin";
313 compatible = "fsl,imx31-rtc", "fsl,imx21-rtc";
314 reg = <0x53fd8000 0x4000>;
316 clocks = <&clks 2>, <&clks 40>;
317 clock-names = "ref", "ipg";
320 wdog: wdog@53fdc000 {
321 compatible = "fsl,imx31-wdt", "fsl,imx21-wdt";
322 reg = <0x53fdc000 0x4000>;
327 compatible = "fsl,imx31-pwm", "fsl,imx27-pwm";
328 reg = <0x53fe0000 0x4000>;
330 clocks = <&clks 10>, <&clks 42>;
331 clock-names = "ipg", "per";
337 emi@b8000000 { /* External Memory Interface */
338 compatible = "simple-bus";
339 reg = <0xb8000000 0x5000>;
341 #address-cells = <1>;
345 compatible = "fsl,imx31-nand", "fsl,imx27-nand";
346 reg = <0xb8000000 0x1000>;
349 dmas = <&sdma 30 17 0>;
351 #address-cells = <1>;
356 weim: weim@b8002000 {
357 compatible = "fsl,imx31-weim", "fsl,imx27-weim";
358 reg = <0xb8002000 0x1000>;
360 #address-cells = <2>;
362 ranges = <0 0 0xa0000000 0x08000000
363 1 0 0xa8000000 0x08000000
364 2 0 0xb0000000 0x02000000
365 3 0 0xb2000000 0x02000000
366 4 0 0xb4000000 0x02000000
367 5 0 0xb6000000 0x02000000>;