1 // SPDX-License-Identifier: GPL-2.0+
3 // Copyright 2013 Greg Ungerer <gerg@uclinux.org>
4 // Copyright 2011 Freescale Semiconductor, Inc.
5 // Copyright 2011 Linaro Ltd.
7 #include "imx50-pinfunc.h"
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/imx5-clock.h>
15 * The decompressor and also some bootloaders rely on a
16 * pre-existing /chosen node to be available to insert the
17 * command line and merge other ATAGS info.
41 compatible = "arm,cortex-a8";
46 tzic: tz-interrupt-controller@fffc000 {
47 compatible = "fsl,imx50-tzic", "fsl,imx53-tzic", "fsl,tzic";
49 #interrupt-cells = <1>;
50 reg = <0x0fffc000 0x4000>;
55 compatible = "fsl,imx-ckil", "fixed-clock";
57 clock-frequency = <32768>;
61 compatible = "fsl,imx-ckih1", "fixed-clock";
63 clock-frequency = <22579200>;
67 compatible = "fsl,imx-ckih2", "fixed-clock";
69 clock-frequency = <0>;
73 compatible = "fsl,imx-osc", "fixed-clock";
75 clock-frequency = <24000000>;
82 compatible = "simple-bus";
83 interrupt-parent = <&tzic>;
86 aips@50000000 { /* AIPS1 */
87 compatible = "fsl,aips-bus", "simple-bus";
90 reg = <0x50000000 0x10000000>;
94 compatible = "fsl,spba-bus", "simple-bus";
97 reg = <0x50000000 0x40000>;
100 esdhc1: esdhc@50004000 {
101 compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
102 reg = <0x50004000 0x4000>;
104 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
105 <&clks IMX5_CLK_DUMMY>,
106 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
107 clock-names = "ipg", "ahb", "per";
112 esdhc2: esdhc@50008000 {
113 compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
114 reg = <0x50008000 0x4000>;
116 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
117 <&clks IMX5_CLK_DUMMY>,
118 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
119 clock-names = "ipg", "ahb", "per";
124 uart3: serial@5000c000 {
125 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
126 reg = <0x5000c000 0x4000>;
128 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
129 <&clks IMX5_CLK_UART3_PER_GATE>;
130 clock-names = "ipg", "per";
134 ecspi1: spi@50010000 {
135 #address-cells = <1>;
137 compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
138 reg = <0x50010000 0x4000>;
140 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
141 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
142 clock-names = "ipg", "per";
147 #sound-dai-cells = <0>;
148 compatible = "fsl,imx50-ssi",
151 reg = <0x50014000 0x4000>;
153 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
154 dmas = <&sdma 24 1 0>,
156 dma-names = "rx", "tx";
157 fsl,fifo-depth = <15>;
161 esdhc3: esdhc@50020000 {
162 compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
163 reg = <0x50020000 0x4000>;
165 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
166 <&clks IMX5_CLK_DUMMY>,
167 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
168 clock-names = "ipg", "ahb", "per";
173 esdhc4: esdhc@50024000 {
174 compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
175 reg = <0x50024000 0x4000>;
177 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
178 <&clks IMX5_CLK_DUMMY>,
179 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
180 clock-names = "ipg", "ahb", "per";
186 usbotg: usb@53f80000 {
187 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
188 reg = <0x53f80000 0x0200>;
190 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
194 usbh1: usb@53f80200 {
195 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
196 reg = <0x53f80200 0x0200>;
198 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
203 gpio1: gpio@53f84000 {
204 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
205 reg = <0x53f84000 0x4000>;
206 interrupts = <50 51>;
209 interrupt-controller;
210 #interrupt-cells = <2>;
211 gpio-ranges = <&iomuxc 0 151 28>;
214 gpio2: gpio@53f88000 {
215 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
216 reg = <0x53f88000 0x4000>;
217 interrupts = <52 53>;
220 interrupt-controller;
221 #interrupt-cells = <2>;
222 gpio-ranges = <&iomuxc 0 75 8>, <&iomuxc 8 100 8>,
223 <&iomuxc 16 83 1>, <&iomuxc 17 85 1>,
224 <&iomuxc 18 87 1>, <&iomuxc 19 84 1>,
225 <&iomuxc 20 88 1>, <&iomuxc 21 86 1>;
228 gpio3: gpio@53f8c000 {
229 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
230 reg = <0x53f8c000 0x4000>;
231 interrupts = <54 55>;
234 interrupt-controller;
235 #interrupt-cells = <2>;
236 gpio-ranges = <&iomuxc 0 108 32>;
239 gpio4: gpio@53f90000 {
240 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
241 reg = <0x53f90000 0x4000>;
242 interrupts = <56 57>;
245 interrupt-controller;
246 #interrupt-cells = <2>;
247 gpio-ranges = <&iomuxc 0 8 8>, <&iomuxc 8 45 12>,
251 wdog1: wdog@53f98000 {
252 compatible = "fsl,imx50-wdt", "fsl,imx21-wdt";
253 reg = <0x53f98000 0x4000>;
255 clocks = <&clks IMX5_CLK_DUMMY>;
258 gpt: timer@53fa0000 {
259 compatible = "fsl,imx50-gpt", "fsl,imx31-gpt";
260 reg = <0x53fa0000 0x4000>;
262 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
263 <&clks IMX5_CLK_GPT_HF_GATE>;
264 clock-names = "ipg", "per";
267 iomuxc: iomuxc@53fa8000 {
268 compatible = "fsl,imx50-iomuxc", "fsl,imx53-iomuxc";
269 reg = <0x53fa8000 0x4000>;
272 gpr: iomuxc-gpr@53fa8000 {
273 compatible = "fsl,imx50-iomuxc-gpr", "syscon";
274 reg = <0x53fa8000 0xc>;
279 compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
280 reg = <0x53fb4000 0x4000>;
281 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
282 <&clks IMX5_CLK_PWM1_HF_GATE>;
283 clock-names = "ipg", "per";
289 compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
290 reg = <0x53fb8000 0x4000>;
291 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
292 <&clks IMX5_CLK_PWM2_HF_GATE>;
293 clock-names = "ipg", "per";
297 uart1: serial@53fbc000 {
298 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
299 reg = <0x53fbc000 0x4000>;
301 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
302 <&clks IMX5_CLK_UART1_PER_GATE>;
303 clock-names = "ipg", "per";
307 uart2: serial@53fc0000 {
308 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
309 reg = <0x53fc0000 0x4000>;
311 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
312 <&clks IMX5_CLK_UART2_PER_GATE>;
313 clock-names = "ipg", "per";
318 compatible = "fsl,imx50-src", "fsl,imx51-src";
319 reg = <0x53fd0000 0x4000>;
324 compatible = "fsl,imx50-ccm";
325 reg = <0x53fd4000 0x4000>;
326 interrupts = <0 71 0x04 0 72 0x04>;
330 gpio5: gpio@53fdc000 {
331 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
332 reg = <0x53fdc000 0x4000>;
333 interrupts = <103 104>;
336 interrupt-controller;
337 #interrupt-cells = <2>;
338 gpio-ranges = <&iomuxc 0 57 18>, <&iomuxc 18 89 11>;
341 gpio6: gpio@53fe0000 {
342 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
343 reg = <0x53fe0000 0x4000>;
344 interrupts = <105 106>;
347 interrupt-controller;
348 #interrupt-cells = <2>;
349 gpio-ranges = <&iomuxc 0 27 18>, <&iomuxc 18 16 11>;
353 #address-cells = <1>;
355 compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
356 reg = <0x53fec000 0x4000>;
358 clocks = <&clks IMX5_CLK_I2C3_GATE>;
362 uart4: serial@53ff0000 {
363 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
364 reg = <0x53ff0000 0x4000>;
366 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
367 <&clks IMX5_CLK_UART4_PER_GATE>;
368 clock-names = "ipg", "per";
373 aips@60000000 { /* AIPS2 */
374 compatible = "fsl,aips-bus", "simple-bus";
375 #address-cells = <1>;
377 reg = <0x60000000 0x10000000>;
380 uart5: serial@63f90000 {
381 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
382 reg = <0x63f90000 0x4000>;
384 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
385 <&clks IMX5_CLK_UART5_PER_GATE>;
386 clock-names = "ipg", "per";
390 owire: owire@63fa4000 {
391 compatible = "fsl,imx50-owire", "fsl,imx21-owire";
392 reg = <0x63fa4000 0x4000>;
393 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
397 ecspi2: spi@63fac000 {
398 #address-cells = <1>;
400 compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
401 reg = <0x63fac000 0x4000>;
403 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
404 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
405 clock-names = "ipg", "per";
409 sdma: sdma@63fb0000 {
410 compatible = "fsl,imx50-sdma", "fsl,imx35-sdma";
411 reg = <0x63fb0000 0x4000>;
413 clocks = <&clks IMX5_CLK_SDMA_GATE>,
414 <&clks IMX5_CLK_SDMA_GATE>;
415 clock-names = "ipg", "ahb";
417 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin";
421 #address-cells = <1>;
423 compatible = "fsl,imx50-cspi", "fsl,imx35-cspi";
424 reg = <0x63fc0000 0x4000>;
426 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
427 <&clks IMX5_CLK_CSPI_IPG_GATE>;
428 clock-names = "ipg", "per";
433 #address-cells = <1>;
435 compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
436 reg = <0x63fc4000 0x4000>;
438 clocks = <&clks IMX5_CLK_I2C2_GATE>;
443 #address-cells = <1>;
445 compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
446 reg = <0x63fc8000 0x4000>;
448 clocks = <&clks IMX5_CLK_I2C1_GATE>;
453 #sound-dai-cells = <0>;
454 compatible = "fsl,imx50-ssi", "fsl,imx51-ssi",
456 reg = <0x63fcc000 0x4000>;
458 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
459 dmas = <&sdma 28 0 0>,
461 dma-names = "rx", "tx";
462 fsl,fifo-depth = <15>;
466 audmux: audmux@63fd0000 {
467 compatible = "fsl,imx50-audmux", "fsl,imx31-audmux";
468 reg = <0x63fd0000 0x4000>;
472 fec: ethernet@63fec000 {
473 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
474 reg = <0x63fec000 0x4000>;
476 clocks = <&clks IMX5_CLK_FEC_GATE>,
477 <&clks IMX5_CLK_FEC_GATE>,
478 <&clks IMX5_CLK_FEC_GATE>;
479 clock-names = "ipg", "ahb", "ptp";