sys/gnu/dts/arm/imx53-qsb-common.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 //
   3 // Copyright 2011 Freescale Semiconductor, Inc.
   4 // Copyright 2011 Linaro Ltd.
   5
   6 #include "imx53.dtsi"
   7
   8 / {
   9         chosen {
  10                 stdout-path = &uart1;
  11         };
  12
  13         memory@70000000 {
  14                 reg = <0x70000000 0x20000000>,
  15                       <0xb0000000 0x20000000>;
  16         };
  17
  18         display0: disp0 {
  19                 compatible = "fsl,imx-parallel-display";
  20                 interface-pix-fmt = "rgb565";
  21                 pinctrl-names = "default";
  22                 pinctrl-0 = <&pinctrl_ipu_disp0>;
  23                 status = "disabled";
  24                 display-timings {
  25                         claawvga {
  26                                 native-mode;
  27                                 clock-frequency = <27000000>;
  28                                 hactive = <800>;
  29                                 vactive = <480>;
  30                                 hback-porch = <40>;
  31                                 hfront-porch = <60>;
  32                                 vback-porch = <10>;
  33                                 vfront-porch = <10>;
  34                                 hsync-len = <20>;
  35                                 vsync-len = <10>;
  36                                 hsync-active = <0>;
  37                                 vsync-active = <0>;
  38                                 de-active = <1>;
  39                                 pixelclk-active = <0>;
  40                         };
  41                 };
  42
  43                 port {
  44                         display0_in: endpoint {
  45                                 remote-endpoint = <&ipu_di0_disp0>;
  46                         };
  47                 };
  48         };
  49
  50         gpio-keys {
  51                 compatible = "gpio-keys";
  52
  53                 power {
  54                         label = "Power Button";
  55                         gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
  56                         linux,code = <KEY_POWER>;
  57                 };
  58
  59                 volume-up {
  60                         label = "Volume Up";
  61                         gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
  62                         linux,code = <KEY_VOLUMEUP>;
  63                         wakeup-source;
  64                 };
  65
  66                 volume-down {
  67                         label = "Volume Down";
  68                         gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
  69                         linux,code = <KEY_VOLUMEDOWN>;
  70                         wakeup-source;
  71                 };
  72         };
  73
  74         leds {
  75                 compatible = "gpio-leds";
  76                 pinctrl-names = "default";
  77                 pinctrl-0 = <&led_pin_gpio7_7>;
  78
  79                 user {
  80                         label = "Heartbeat";
  81                         gpios = <&gpio7 7 0>;
  82                         linux,default-trigger = "heartbeat";
  83                 };
  84         };
  85
  86         regulators {
  87                 compatible = "simple-bus";
  88                 #address-cells = <1>;
  89                 #size-cells = <0>;
  90
  91                 reg_3p2v: regulator@0 {
  92                         compatible = "regulator-fixed";
  93                         reg = <0>;
  94                         regulator-name = "3P2V";
  95                         regulator-min-microvolt = <3200000>;
  96                         regulator-max-microvolt = <3200000>;
  97                         regulator-always-on;
  98                 };
  99
 100                 reg_usb_vbus: regulator@1 {
 101                         compatible = "regulator-fixed";
 102                         reg = <1>;
 103                         regulator-name = "usb_vbus";
 104                         regulator-min-microvolt = <5000000>;
 105                         regulator-max-microvolt = <5000000>;
 106                         gpio = <&gpio7 8 0>;
 107                         enable-active-high;
 108                 };
 109         };
 110
 111         sound {
 112                 compatible = "fsl,imx53-qsb-sgtl5000",
 113                              "fsl,imx-audio-sgtl5000";
 114                 model = "imx53-qsb-sgtl5000";
 115                 ssi-controller = <&ssi2>;
 116                 audio-codec = <&sgtl5000>;
 117                 audio-routing =
 118                         "MIC_IN", "Mic Jack",
 119                         "Mic Jack", "Mic Bias",
 120                         "Headphone Jack", "HP_OUT";
 121                 mux-int-port = <2>;
 122                 mux-ext-port = <5>;
 123         };
 124 };
 125
 126 &cpu0 {
 127         /* CPU rated to 1GHz, not 1.2GHz as per the default settings */
 128         operating-points = <
 129                 /* kHz   uV */
 130                 166666  850000
 131                 400000  900000
 132                 800000  1050000
 133                 1000000 1200000
 134         >;
 135 };
 136
 137 &esdhc1 {
 138         pinctrl-names = "default";
 139         pinctrl-0 = <&pinctrl_esdhc1>;
 140         status = "okay";
 141 };
 142
 143 &ipu_di0_disp0 {
 144         remote-endpoint = <&display0_in>;
 145 };
 146
 147 &ssi2 {
 148         status = "okay";
 149 };
 150
 151 &esdhc3 {
 152         pinctrl-names = "default";
 153         pinctrl-0 = <&pinctrl_esdhc3>;
 154         cd-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
 155         wp-gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>;
 156         bus-width = <8>;
 157         status = "okay";
 158 };
 159
 160 &iomuxc {
 161         pinctrl-names = "default";
 162         pinctrl-0 = <&pinctrl_hog>;
 163
 164         imx53-qsb {
 165                 pinctrl_hog: hoggrp {
 166                         fsl,pins = <
 167                                 MX53_PAD_GPIO_8__GPIO1_8          0x80000000
 168                                 MX53_PAD_PATA_DATA14__GPIO2_14    0x80000000
 169                                 MX53_PAD_PATA_DATA15__GPIO2_15    0x80000000
 170                                 MX53_PAD_EIM_DA11__GPIO3_11       0x80000000
 171                                 MX53_PAD_EIM_DA12__GPIO3_12       0x80000000
 172                                 MX53_PAD_PATA_DA_0__GPIO7_6       0x80000000
 173                                 MX53_PAD_PATA_DA_2__GPIO7_8       0x80000000
 174                                 MX53_PAD_GPIO_16__GPIO7_11        0x80000000
 175                         >;
 176                 };
 177
 178                 led_pin_gpio7_7: led_gpio7_7 {
 179                         fsl,pins = <
 180                                 MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000
 181                         >;
 182                 };
 183
 184                 pinctrl_audmux: audmuxgrp {
 185                         fsl,pins = <
 186                                 MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC      0x80000000
 187                                 MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD      0x80000000
 188                                 MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS     0x80000000
 189                                 MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD      0x80000000
 190                         >;
 191                 };
 192
 193                 pinctrl_codec: codecgrp {
 194                         fsl,pins = <
 195                                 MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK       0x1c4
 196                         >;
 197                 };
 198
 199                 pinctrl_esdhc1: esdhc1grp {
 200                         fsl,pins = <
 201                                 MX53_PAD_SD1_DATA0__ESDHC1_DAT0         0x1d5
 202                                 MX53_PAD_SD1_DATA1__ESDHC1_DAT1         0x1d5
 203                                 MX53_PAD_SD1_DATA2__ESDHC1_DAT2         0x1d5
 204                                 MX53_PAD_SD1_DATA3__ESDHC1_DAT3         0x1d5
 205                                 MX53_PAD_SD1_CMD__ESDHC1_CMD            0x1d5
 206                                 MX53_PAD_SD1_CLK__ESDHC1_CLK            0x1d5
 207                         >;
 208                 };
 209
 210                 pinctrl_esdhc3: esdhc3grp {
 211                         fsl,pins = <
 212                                 MX53_PAD_PATA_DATA8__ESDHC3_DAT0        0x1d5
 213                                 MX53_PAD_PATA_DATA9__ESDHC3_DAT1        0x1d5
 214                                 MX53_PAD_PATA_DATA10__ESDHC3_DAT2       0x1d5
 215                                 MX53_PAD_PATA_DATA11__ESDHC3_DAT3       0x1d5
 216                                 MX53_PAD_PATA_DATA0__ESDHC3_DAT4        0x1d5
 217                                 MX53_PAD_PATA_DATA1__ESDHC3_DAT5        0x1d5
 218                                 MX53_PAD_PATA_DATA2__ESDHC3_DAT6        0x1d5
 219                                 MX53_PAD_PATA_DATA3__ESDHC3_DAT7        0x1d5
 220                                 MX53_PAD_PATA_RESET_B__ESDHC3_CMD       0x1d5
 221                                 MX53_PAD_PATA_IORDY__ESDHC3_CLK         0x1d5
 222                         >;
 223                 };
 224
 225                 pinctrl_fec: fecgrp {
 226                         fsl,pins = <
 227                                 MX53_PAD_FEC_MDC__FEC_MDC               0x4
 228                                 MX53_PAD_FEC_MDIO__FEC_MDIO             0x1fc
 229                                 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK        0x180
 230                                 MX53_PAD_FEC_RX_ER__FEC_RX_ER           0x180
 231                                 MX53_PAD_FEC_CRS_DV__FEC_RX_DV          0x180
 232                                 MX53_PAD_FEC_RXD1__FEC_RDATA_1          0x180
 233                                 MX53_PAD_FEC_RXD0__FEC_RDATA_0          0x180
 234                                 MX53_PAD_FEC_TX_EN__FEC_TX_EN           0x4
 235                                 MX53_PAD_FEC_TXD1__FEC_TDATA_1          0x4
 236                                 MX53_PAD_FEC_TXD0__FEC_TDATA_0          0x4
 237                         >;
 238                 };
 239
 240                 /* open drain */
 241                 pinctrl_i2c1: i2c1grp {
 242                         fsl,pins = <
 243                                 MX53_PAD_CSI0_DAT8__I2C1_SDA            0x400001ec
 244                                 MX53_PAD_CSI0_DAT9__I2C1_SCL            0x400001ec
 245                         >;
 246                 };
 247
 248                 pinctrl_i2c2: i2c2grp {
 249                         fsl,pins = <
 250                                 MX53_PAD_KEY_ROW3__I2C2_SDA             0xc0000000
 251                                 MX53_PAD_KEY_COL3__I2C2_SCL             0xc0000000
 252                         >;
 253                 };
 254
 255                 pinctrl_ipu_disp0: ipudisp0grp {
 256                         fsl,pins = <
 257                                 MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5
 258                                 MX53_PAD_DI0_PIN15__IPU_DI0_PIN15       0x5
 259                                 MX53_PAD_DI0_PIN2__IPU_DI0_PIN2         0x5
 260                                 MX53_PAD_DI0_PIN3__IPU_DI0_PIN3         0x5
 261                                 MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0    0x5
 262                                 MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1    0x5
 263                                 MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2    0x5
 264                                 MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3    0x5
 265                                 MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4    0x5
 266                                 MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5    0x5
 267                                 MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6    0x5
 268                                 MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7    0x5
 269                                 MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8    0x5
 270                                 MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9    0x5
 271                                 MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10  0x5
 272                                 MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11  0x5
 273                                 MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12  0x5
 274                                 MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13  0x5
 275                                 MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14  0x5
 276                                 MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15  0x5
 277                                 MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16  0x5
 278                                 MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17  0x5
 279                                 MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18  0x5
 280                                 MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19  0x5
 281                                 MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20  0x5
 282                                 MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21  0x5
 283                                 MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22  0x5
 284                                 MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23  0x5
 285                         >;
 286                 };
 287
 288                 pinctrl_vga_sync: vgasync-grp {
 289                         fsl,pins = <
 290                                 /* VGA_HSYNC, VSYNC with max drive strength */
 291                                 MX53_PAD_EIM_OE__IPU_DI1_PIN7 0xe6
 292                                 MX53_PAD_EIM_RW__IPU_DI1_PIN8 0xe6
 293                         >;
 294                 };
 295
 296                 pinctrl_uart1: uart1grp {
 297                         fsl,pins = <
 298                                 MX53_PAD_CSI0_DAT10__UART1_TXD_MUX      0x1e4
 299                                 MX53_PAD_CSI0_DAT11__UART1_RXD_MUX      0x1e4
 300                         >;
 301                 };
 302         };
 303 };
 304
 305 &tve {
 306         pinctrl-names = "default";
 307         pinctrl-0 = <&pinctrl_vga_sync>;
 308         ddc-i2c-bus = <&i2c2>;
 309         fsl,tve-mode = "vga";
 310         fsl,hsync-pin = <7>;    /* IPU DI1 PIN7 via EIM_OE */
 311         fsl,vsync-pin = <8>;    /* IPU DI1 PIN8 via EIM_RW */
 312         status = "okay";
 313 };
 314
 315 &uart1 {
 316         pinctrl-names = "default";
 317         pinctrl-0 = <&pinctrl_uart1>;
 318         status = "okay";
 319 };
 320
 321 &i2c2 {
 322         pinctrl-names = "default";
 323         pinctrl-0 = <&pinctrl_i2c2>;
 324         status = "okay";
 325
 326         sgtl5000: codec@a {
 327                 compatible = "fsl,sgtl5000";
 328                 reg = <0x0a>;
 329                 pinctrl-names = "default";
 330                 pinctrl-0 = <&pinctrl_codec>;
 331                 #sound-dai-cells = <0>;
 332                 VDDA-supply = <&reg_3p2v>;
 333                 VDDIO-supply = <&reg_3p2v>;
 334                 clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>;
 335         };
 336 };
 337
 338 &i2c1 {
 339         pinctrl-names = "default";
 340         pinctrl-0 = <&pinctrl_i2c1>;
 341         status = "okay";
 342
 343         accelerometer: mma8450@1c {
 344                 compatible = "fsl,mma8450";
 345                 reg = <0x1c>;
 346         };
 347 };
 348
 349 &audmux {
 350         pinctrl-names = "default";
 351         pinctrl-0 = <&pinctrl_audmux>;
 352         status = "okay";
 353 };
 354
 355 &fec {
 356         pinctrl-names = "default";
 357         pinctrl-0 = <&pinctrl_fec>;
 358         phy-mode = "rmii";
 359         phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
 360         status = "okay";
 361 };
 362
 363 &sata {
 364         status = "okay";
 365 };
 366
 367 &vpu {
 368         status = "okay";
 369 };
 370
 371 &usbh1 {
 372         vbus-supply = <&reg_usb_vbus>;
 373         phy_type = "utmi";
 374         status = "okay";
 375 };
 376
 377 &usbotg {
 378         dr_mode = "peripheral";
 379         status = "okay";
 380 };