3 * Copyright 2013 Freescale Semiconductor, Inc.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include "imx6q-pinfunc.h"
13 #include "imx6qdl.dtsi"
26 compatible = "arm,cortex-a9";
29 next-level-cache = <&L2>;
38 fsl,soc-operating-points = <
39 /* ARM kHz SOC-PU uV */
46 clock-latency = <61036>; /* two CLK32 periods */
47 clocks = <&clks IMX6QDL_CLK_ARM>,
48 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
49 <&clks IMX6QDL_CLK_STEP>,
50 <&clks IMX6QDL_CLK_PLL1_SW>,
51 <&clks IMX6QDL_CLK_PLL1_SYS>;
52 clock-names = "arm", "pll2_pfd2_396m", "step",
53 "pll1_sw", "pll1_sys";
54 arm-supply = <®_arm>;
55 pu-supply = <®_pu>;
56 soc-supply = <®_soc>;
60 compatible = "arm,cortex-a9";
63 next-level-cache = <&L2>;
67 compatible = "arm,cortex-a9";
70 next-level-cache = <&L2>;
74 compatible = "arm,cortex-a9";
77 next-level-cache = <&L2>;
83 compatible = "mmio-sram";
84 reg = <0x00900000 0x40000>;
85 clocks = <&clks IMX6QDL_CLK_OCRAM>;
88 aips-bus@2000000 { /* AIPS1 */
90 ecspi5: ecspi@2018000 {
93 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
94 reg = <0x02018000 0x4000>;
95 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
96 clocks = <&clks IMX6Q_CLK_ECSPI5>,
97 <&clks IMX6Q_CLK_ECSPI5>;
98 clock-names = "ipg", "per";
99 dmas = <&sdma 11 7 1>, <&sdma 12 7 2>;
100 dma-names = "rx", "tx";
105 iomuxc: iomuxc@20e0000 {
106 compatible = "fsl,imx6q-iomuxc";
111 compatible = "fsl,imx6q-ahci";
112 reg = <0x02200000 0x4000>;
113 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
114 clocks = <&clks IMX6QDL_CLK_SATA>,
115 <&clks IMX6QDL_CLK_SATA_REF_100M>,
116 <&clks IMX6QDL_CLK_AHB>;
117 clock-names = "sata", "sata_ref", "ahb";
121 gpu_vg: gpu@2204000 {
122 compatible = "vivante,gc";
123 reg = <0x02204000 0x4000>;
124 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
125 clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>,
126 <&clks IMX6QDL_CLK_GPU2D_CORE>;
127 clock-names = "bus", "core";
128 power-domains = <&pd_pu>;
132 #address-cells = <1>;
134 compatible = "fsl,imx6q-ipu";
135 reg = <0x02800000 0x400000>;
136 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
137 <0 7 IRQ_TYPE_LEVEL_HIGH>;
138 clocks = <&clks IMX6QDL_CLK_IPU2>,
139 <&clks IMX6QDL_CLK_IPU2_DI0>,
140 <&clks IMX6QDL_CLK_IPU2_DI1>;
141 clock-names = "bus", "di0", "di1";
147 ipu2_csi0_from_mipi_vc2: endpoint {
148 remote-endpoint = <&mipi_vc2_to_ipu2_csi0>;
155 ipu2_csi1_from_ipu2_csi1_mux: endpoint {
156 remote-endpoint = <&ipu2_csi1_mux_to_ipu2_csi1>;
161 #address-cells = <1>;
165 ipu2_di0_disp0: disp0-endpoint {
168 ipu2_di0_hdmi: hdmi-endpoint {
169 remote-endpoint = <&hdmi_mux_2>;
172 ipu2_di0_mipi: mipi-endpoint {
173 remote-endpoint = <&mipi_mux_2>;
176 ipu2_di0_lvds0: lvds0-endpoint {
177 remote-endpoint = <&lvds0_mux_2>;
180 ipu2_di0_lvds1: lvds1-endpoint {
181 remote-endpoint = <&lvds1_mux_2>;
186 #address-cells = <1>;
190 ipu2_di1_hdmi: hdmi-endpoint {
191 remote-endpoint = <&hdmi_mux_3>;
194 ipu2_di1_mipi: mipi-endpoint {
195 remote-endpoint = <&mipi_mux_3>;
198 ipu2_di1_lvds0: lvds0-endpoint {
199 remote-endpoint = <&lvds0_mux_3>;
202 ipu2_di1_lvds1: lvds1-endpoint {
203 remote-endpoint = <&lvds1_mux_3>;
210 compatible = "fsl,imx-capture-subsystem";
211 ports = <&ipu1_csi0>, <&ipu1_csi1>, <&ipu2_csi0>, <&ipu2_csi1>;
215 compatible = "fsl,imx-display-subsystem";
216 ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
221 gpio-ranges = <&iomuxc 0 136 2>, <&iomuxc 2 141 1>, <&iomuxc 3 139 1>,
222 <&iomuxc 4 142 2>, <&iomuxc 6 140 1>, <&iomuxc 7 144 2>,
223 <&iomuxc 9 138 1>, <&iomuxc 10 213 3>, <&iomuxc 13 20 1>,
224 <&iomuxc 14 19 1>, <&iomuxc 15 21 1>, <&iomuxc 16 208 1>,
225 <&iomuxc 17 207 1>, <&iomuxc 18 210 3>, <&iomuxc 21 209 1>,
230 gpio-ranges = <&iomuxc 0 191 16>, <&iomuxc 16 55 14>, <&iomuxc 30 35 1>,
235 gpio-ranges = <&iomuxc 0 69 16>, <&iomuxc 16 36 8>, <&iomuxc 24 45 8>;
239 gpio-ranges = <&iomuxc 5 149 1>, <&iomuxc 6 126 10>, <&iomuxc 16 87 16>;
243 gpio-ranges = <&iomuxc 0 85 1>, <&iomuxc 2 34 1>, <&iomuxc 4 53 1>,
244 <&iomuxc 5 103 13>, <&iomuxc 18 150 14>;
248 gpio-ranges = <&iomuxc 0 164 6>, <&iomuxc 6 54 1>, <&iomuxc 7 181 5>,
249 <&iomuxc 14 186 3>, <&iomuxc 17 170 2>, <&iomuxc 19 22 12>,
254 gpio-ranges = <&iomuxc 0 172 9>, <&iomuxc 9 189 2>, <&iomuxc 11 146 3>;
259 compatible = "video-mux";
260 mux-controls = <&mux 0>;
261 #address-cells = <1>;
267 ipu1_csi0_mux_from_mipi_vc0: endpoint {
268 remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
275 ipu1_csi0_mux_from_parallel_sensor: endpoint {
282 ipu1_csi0_mux_to_ipu1_csi0: endpoint {
283 remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
289 compatible = "video-mux";
290 mux-controls = <&mux 1>;
291 #address-cells = <1>;
297 ipu2_csi1_mux_from_mipi_vc3: endpoint {
298 remote-endpoint = <&mipi_vc3_to_ipu2_csi1_mux>;
305 ipu2_csi1_mux_from_parallel_sensor: endpoint {
312 ipu2_csi1_mux_to_ipu2_csi1: endpoint {
313 remote-endpoint = <&ipu2_csi1_from_ipu2_csi1_mux>;
320 compatible = "fsl,imx6q-hdmi";
325 hdmi_mux_2: endpoint {
326 remote-endpoint = <&ipu2_di0_hdmi>;
333 hdmi_mux_3: endpoint {
334 remote-endpoint = <&ipu2_di1_hdmi>;
340 ipu1_csi1_from_mipi_vc1: endpoint {
341 remote-endpoint = <&mipi_vc1_to_ipu1_csi1>;
346 clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
347 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
348 <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
349 <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
350 clock-names = "di0_pll", "di1_pll",
351 "di0_sel", "di1_sel", "di2_sel", "di3_sel",
358 lvds0_mux_2: endpoint {
359 remote-endpoint = <&ipu2_di0_lvds0>;
366 lvds0_mux_3: endpoint {
367 remote-endpoint = <&ipu2_di1_lvds0>;
376 lvds1_mux_2: endpoint {
377 remote-endpoint = <&ipu2_di0_lvds1>;
384 lvds1_mux_3: endpoint {
385 remote-endpoint = <&ipu2_di1_lvds1>;
395 mipi_vc0_to_ipu1_csi0_mux: endpoint {
396 remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
403 mipi_vc1_to_ipu1_csi1: endpoint {
404 remote-endpoint = <&ipu1_csi1_from_mipi_vc1>;
411 mipi_vc2_to_ipu2_csi0: endpoint {
412 remote-endpoint = <&ipu2_csi0_from_mipi_vc2>;
419 mipi_vc3_to_ipu2_csi1_mux: endpoint {
420 remote-endpoint = <&ipu2_csi1_mux_from_mipi_vc3>;
430 mipi_mux_2: endpoint {
431 remote-endpoint = <&ipu2_di0_mipi>;
438 mipi_mux_3: endpoint {
439 remote-endpoint = <&ipu2_di1_mipi>;
446 mux-reg-masks = <0x04 0x00080000>, /* MIPI_IPU1_MUX */
447 <0x04 0x00100000>, /* MIPI_IPU2_MUX */
448 <0x0c 0x0000000c>, /* HDMI_MUX_CTL */
449 <0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
450 <0x0c 0x00000300>, /* LVDS1_MUX_CTL */
451 <0x28 0x00000003>, /* DCIC1_MUX_CTL */
452 <0x28 0x0000000c>; /* DCIC2_MUX_CTL */
456 compatible = "fsl,imx6q-vpu", "cnm,coda960";