sys/gnu/dts/arm/imx6qdl-gw5910.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright 2019 Gateworks Corporation
   4  */
   5
   6 #include <dt-bindings/gpio/gpio.h>
   7
   8 / {
   9         /* these are used by bootloader for disabling nodes */
  10         aliases {
  11                 led0 = &led0;
  12                 led1 = &led1;
  13                 led2 = &led2;
  14         };
  15
  16         chosen {
  17                 stdout-path = &uart2;
  18         };
  19
  20         memory@10000000 {
  21                 device_type = "memory";
  22                 reg = <0x10000000 0x20000000>;
  23         };
  24
  25         leds {
  26                 compatible = "gpio-leds";
  27                 pinctrl-names = "default";
  28                 pinctrl-0 = <&pinctrl_gpio_leds>;
  29
  30                 led0: user1 {
  31                         label = "user1";
  32                         gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
  33                         default-state = "on";
  34                         linux,default-trigger = "heartbeat";
  35                 };
  36
  37                 led1: user2 {
  38                         label = "user2";
  39                         gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
  40                         default-state = "off";
  41                 };
  42
  43                 led2: user3 {
  44                         label = "user3";
  45                         gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
  46                         default-state = "off";
  47                 };
  48         };
  49
  50         pps {
  51                 compatible = "pps-gpio";
  52                 pinctrl-names = "default";
  53                 pinctrl-0 = <&pinctrl_pps>;
  54                 gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
  55                 status = "okay";
  56         };
  57
  58         reg_3p3v: regulator-3p3v {
  59                 compatible = "regulator-fixed";
  60                 regulator-name = "3P3V";
  61                 regulator-min-microvolt = <3300000>;
  62                 regulator-max-microvolt = <3300000>;
  63                 regulator-always-on;
  64         };
  65
  66         reg_5p0v: regulator-5p0v {
  67                 compatible = "regulator-fixed";
  68                 regulator-name = "5P0V";
  69                 regulator-min-microvolt = <5000000>;
  70                 regulator-max-microvolt = <5000000>;
  71                 regulator-always-on;
  72         };
  73
  74         reg_wl: regulator-wl {
  75                 pinctrl-names = "default";
  76                 pinctrl-0 = <&pinctrl_reg_wl>;
  77                 compatible = "regulator-fixed";
  78                 regulator-name = "wl";
  79                 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
  80                 startup-delay-us = <100>;
  81                 enable-active-high;
  82                 regulator-min-microvolt = <3300000>;
  83                 regulator-max-microvolt = <3300000>;
  84         };
  85 };
  86
  87
  88 &ecspi3 {
  89         cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
  90         pinctrl-names = "default";
  91         pinctrl-0 = <&pinctrl_ecspi3>;
  92         status = "okay";
  93 };
  94
  95 &fec {
  96         pinctrl-names = "default";
  97         pinctrl-0 = <&pinctrl_enet>;
  98         phy-mode = "rgmii-id";
  99         status = "okay";
 100 };
 101
 102 &gpmi {
 103         pinctrl-names = "default";
 104         pinctrl-0 = <&pinctrl_gpmi_nand>;
 105         status = "okay";
 106 };
 107
 108 &i2c1 {
 109         clock-frequency = <100000>;
 110         pinctrl-names = "default";
 111         pinctrl-0 = <&pinctrl_i2c1>;
 112         status = "okay";
 113
 114         gpio@23 {
 115                 compatible = "nxp,pca9555";
 116                 reg = <0x23>;
 117                 gpio-controller;
 118                 #gpio-cells = <2>;
 119         };
 120
 121         eeprom@50 {
 122                 compatible = "atmel,24c02";
 123                 reg = <0x50>;
 124                 pagesize = <16>;
 125         };
 126
 127         eeprom@51 {
 128                 compatible = "atmel,24c02";
 129                 reg = <0x51>;
 130                 pagesize = <16>;
 131         };
 132
 133         eeprom@52 {
 134                 compatible = "atmel,24c02";
 135                 reg = <0x52>;
 136                 pagesize = <16>;
 137         };
 138
 139         eeprom@53 {
 140                 compatible = "atmel,24c02";
 141                 reg = <0x53>;
 142                 pagesize = <16>;
 143         };
 144
 145         rtc@68 {
 146                 compatible = "dallas,ds1672";
 147                 reg = <0x68>;
 148         };
 149 };
 150
 151 &i2c2 {
 152         clock-frequency = <100000>;
 153         pinctrl-names = "default";
 154         pinctrl-0 = <&pinctrl_i2c2>;
 155         status = "okay";
 156 };
 157
 158 &i2c3 {
 159         clock-frequency = <100000>;
 160         pinctrl-names = "default";
 161         pinctrl-0 = <&pinctrl_i2c3>;
 162         status = "okay";
 163
 164         accel@19 {
 165                 pinctrl-names = "default";
 166                 pinctrl-0 = <&pinctrl_accel>;
 167                 compatible = "st,lis2de12";
 168                 reg = <0x19>;
 169                 st,drdy-int-pin = <1>;
 170                 interrupt-parent = <&gpio7>;
 171                 interrupts = <13 0>;
 172                 interrupt-names = "INT1";
 173         };
 174 };
 175
 176 &pcie {
 177         pinctrl-names = "default";
 178         pinctrl-0 = <&pinctrl_pcie>;
 179         reset-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>;
 180         status = "okay";
 181 };
 182
 183 &pwm2 {
 184         pinctrl-names = "default";
 185         pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
 186         status = "disabled";
 187 };
 188
 189 &pwm3 {
 190         pinctrl-names = "default";
 191         pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
 192         status = "disabled";
 193 };
 194
 195 /* off-board RS232 */
 196 &uart1 {
 197         pinctrl-names = "default";
 198         pinctrl-0 = <&pinctrl_uart1>;
 199         status = "okay";
 200 };
 201
 202 /* serial console */
 203 &uart2 {
 204         pinctrl-names = "default";
 205         pinctrl-0 = <&pinctrl_uart2>;
 206         status = "okay";
 207 };
 208
 209 /* cc1352 */
 210 &uart3 {
 211         pinctrl-names = "default";
 212         pinctrl-0 = <&pinctrl_uart3>;
 213         uart-has-rtscts;
 214         status = "okay";
 215 };
 216
 217 /* Sterling-LWB Bluetooth */
 218 &uart4 {
 219         pinctrl-names = "default";
 220         pinctrl-0 = <&pinctrl_uart4>,<&pinctrl_bten>;
 221         uart-has-rtscts;
 222         status = "okay";
 223
 224         bluetooth {
 225                 compatible = "brcm,bcm4330-bt";
 226                 shutdown-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
 227         };
 228 };
 229
 230 /* GPS */
 231 &uart5 {
 232         pinctrl-names = "default";
 233         pinctrl-0 = <&pinctrl_uart5>;
 234         status = "okay";
 235 };
 236
 237 &usbotg {
 238         vbus-supply = <&reg_5p0v>;
 239         pinctrl-names = "default";
 240         pinctrl-0 = <&pinctrl_usbotg>;
 241         disable-over-current;
 242         status = "okay";
 243 };
 244
 245 &usbh1 {
 246         status = "okay";
 247 };
 248
 249 /* Sterling-LWB SDIO WiFi */
 250 &usdhc2 {
 251         pinctrl-names = "default";
 252         pinctrl-0 = <&pinctrl_usdhc2>;
 253         vmmc-supply = <&reg_wl>;
 254         non-removable;
 255         bus-width = <4>;
 256         status = "okay";
 257 };
 258
 259 &usdhc3 {
 260         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 261         pinctrl-0 = <&pinctrl_usdhc3>;
 262         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 263         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 264         cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
 265         vmmc-supply = <&reg_3p3v>;
 266         status = "okay";
 267 };
 268
 269 &wdog1 {
 270         pinctrl-names = "default";
 271         pinctrl-0 = <&pinctrl_wdog>;
 272         fsl,ext-reset-output;
 273 };
 274
 275 &iomuxc {
 276         pinctrl_accel: accelmuxgrp {
 277                 fsl,pins = <
 278                         MX6QDL_PAD_GPIO_18__GPIO7_IO13          0x1b0b1
 279                 >;
 280         };
 281
 282         pinctrl_bten: btengrp {
 283                 fsl,pins = <
 284                         MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x1b0b1
 285                 >;
 286         };
 287
 288         pinctrl_ecspi3: escpi3grp {
 289                 fsl,pins = <
 290                         MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK      0x100b1
 291                         MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI      0x100b1
 292                         MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO      0x100b1
 293                         MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24       0x100b1
 294                 >;
 295         };
 296
 297         pinctrl_enet: enetgrp {
 298                 fsl,pins = <
 299                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
 300                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
 301                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
 302                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
 303                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
 304                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
 305                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
 306                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
 307                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
 308                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
 309                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
 310                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
 311                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 312                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 313                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 314                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
 315                         MX6QDL_PAD_ENET_TXD0__GPIO1_IO30        0x1b0b0
 316                 >;
 317         };
 318
 319         pinctrl_gpio_leds: gpioledsgrp {
 320                 fsl,pins = <
 321                         MX6QDL_PAD_KEY_COL0__GPIO4_IO06  0x1b0b0
 322                         MX6QDL_PAD_KEY_ROW0__GPIO4_IO07  0x1b0b0
 323                         MX6QDL_PAD_KEY_ROW4__GPIO4_IO15  0x1b0b0
 324                 >;
 325         };
 326
 327         pinctrl_gpmi_nand: gpminandgrp {
 328                 fsl,pins = <
 329                         MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
 330                         MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
 331                         MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
 332                         MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
 333                         MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
 334                         MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
 335                         MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
 336                         MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
 337                         MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
 338                         MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
 339                         MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
 340                         MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
 341                         MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
 342                         MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
 343                         MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
 344                 >;
 345         };
 346
 347         pinctrl_i2c1: i2c1grp {
 348                 fsl,pins = <
 349                         MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 350                         MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 351                         MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x0001b0b0
 352                 >;
 353         };
 354
 355         pinctrl_i2c2: i2c2grp {
 356                 fsl,pins = <
 357                         MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 358                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 359                 >;
 360         };
 361
 362         pinctrl_i2c3: i2c3grp {
 363                 fsl,pins = <
 364                         MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 365                         MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 366                 >;
 367         };
 368
 369         pinctrl_pcie: pciegrp {
 370                 fsl,pins = <
 371                         MX6QDL_PAD_EIM_D20__GPIO3_IO20          0x1b0b0
 372                 >;
 373         };
 374
 375         pinctrl_pps: ppsgrp {
 376                 fsl,pins = <
 377                         MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16     0x1b0b1
 378                 >;
 379         };
 380
 381         pinctrl_pwm2: pwm2grp {
 382                 fsl,pins = <
 383                         MX6QDL_PAD_SD1_DAT2__PWM2_OUT           0x1b0b1
 384                 >;
 385         };
 386
 387         pinctrl_pwm3: pwm3grp {
 388                 fsl,pins = <
 389                         MX6QDL_PAD_SD1_DAT1__PWM3_OUT           0x1b0b1
 390                 >;
 391         };
 392
 393         pinctrl_reg_wl: regwlgrp {
 394                 fsl,pins = <
 395                         MX6QDL_PAD_GPIO_5__GPIO1_IO05           0x1b0b1
 396                 >;
 397         };
 398
 399         pinctrl_uart1: uart1grp {
 400                 fsl,pins = <
 401                         MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA    0x1b0b1
 402                         MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA    0x1b0b1
 403                 >;
 404         };
 405
 406         pinctrl_uart2: uart2grp {
 407                 fsl,pins = <
 408                         MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 409                         MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 410                 >;
 411         };
 412
 413         pinctrl_uart3: uart3grp {
 414                 fsl,pins = <
 415                         MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
 416                         MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
 417                         MX6QDL_PAD_EIM_D23__UART3_RTS_B         0x1b0b1
 418                         MX6QDL_PAD_EIM_D31__UART3_CTS_B         0x1b0b1
 419                         MX6QDL_PAD_EIM_A25__GPIO5_IO02          0x4001b0b1 /* DIO20 */
 420                         MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05      0x4001b0b1 /* DIO14 */
 421                         MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06      0x4001b0b1 /* DIO15 */
 422                         MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08      0x1b0b1 /* TMS */
 423                         MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09      0x1b0b1 /* TCK */
 424                         MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10      0x1b0b1 /* TDO */
 425                         MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11      0x1b0b1 /* TDI */
 426                         MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17      0x4001b0b1 /* RST# */
 427                 >;
 428         };
 429
 430         pinctrl_uart4: uart4grp {
 431                 fsl,pins = <
 432                         MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA    0x1b0b1
 433                         MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA    0x1b0b1
 434                         MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B      0x1b0b1
 435                         MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B      0x1b0b1
 436                 >;
 437         };
 438
 439         pinctrl_uart5: uart5grp {
 440                 fsl,pins = <
 441                         MX6QDL_PAD_KEY_COL1__UART5_TX_DATA      0x1b0b1
 442                         MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA      0x1b0b1
 443                 >;
 444         };
 445
 446         pinctrl_usbotg: usbotggrp {
 447                 fsl,pins = <
 448                         MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x13059
 449                 >;
 450         };
 451
 452         pinctrl_usdhc2: usdhc2grp {
 453                 fsl,pins = <
 454                         MX6QDL_PAD_SD2_CMD__SD2_CMD             0x17059
 455                         MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10059
 456                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17059
 457                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17059
 458                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17059
 459                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17059
 460                 >;
 461         };
 462
 463         pinctrl_usdhc3: usdhc3grp {
 464                 fsl,pins = <
 465                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 466                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 467                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 468                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 469                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 470                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 471                         MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x17059 /* CD */
 472                         MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x17059
 473                 >;
 474         };
 475
 476         pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
 477                 fsl,pins = <
 478                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170b9
 479                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x170b9
 480                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170b9
 481                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170b9
 482                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170b9
 483                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170b9
 484                         MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x170b9 /* CD */
 485                         MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x170b9
 486                 >;
 487         };
 488
 489         pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
 490                 fsl,pins = <
 491                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170f9
 492                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100f9
 493                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170f9
 494                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170f9
 495                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170f9
 496                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170f9
 497                         MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x170f9 /* CD */
 498                         MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x170f9
 499                 >;
 500         };
 501
 502         pinctrl_wdog: wdoggrp {
 503                 fsl,pins = <
 504                         MX6QDL_PAD_DISP0_DAT8__WDOG1_B          0x1b0b0
 505                 >;
 506         };
 507 };