1 // SPDX-License-Identifier: GPL-2.0 OR X11
3 * Copyright (C) 2016 Amarula Solutions B.V.
4 * Copyright (C) 2016 Engicam S.r.l.
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/sound/fsl-imx-audmux.h>
13 reg = <0x10000000 0x80000000>;
16 backlight_lvds: backlight-lvds {
17 compatible = "pwm-backlight";
18 pwms = <&pwm3 0 100000>;
19 brightness-levels = <0 4 8 16 32 64 128 255>;
20 default-brightness-level = <7>;
23 reg_1p8v: regulator-1p8v {
24 compatible = "regulator-fixed";
25 regulator-name = "1P8V";
26 regulator-min-microvolt = <1800000>;
27 regulator-max-microvolt = <1800000>;
32 reg_2p5v: regulator-2p5v {
33 compatible = "regulator-fixed";
34 regulator-name = "2P5V";
35 regulator-min-microvolt = <2500000>;
36 regulator-max-microvolt = <2500000>;
41 reg_3p3v: regulator-3p3v {
42 compatible = "regulator-fixed";
43 regulator-name = "3P3V";
44 regulator-min-microvolt = <3300000>;
45 regulator-max-microvolt = <3300000>;
50 reg_usb_h1_vbus: regulator-usb-h1-vbus {
51 compatible = "regulator-fixed";
52 regulator-name = "usb_h1_vbus";
53 regulator-min-microvolt = <5000000>;
54 regulator-max-microvolt = <5000000>;
59 reg_usb_otg_vbus: regulator-usb-otg-vbus {
60 compatible = "regulator-fixed";
61 regulator-name = "usb_otg_vbus";
62 regulator-min-microvolt = <5000000>;
63 regulator-max-microvolt = <5000000>;
68 rmii_clk: clock-rmii-clk {
69 compatible = "fixed-clock";
71 clock-frequency = <25000000>; /* 25MHz for example */
75 compatible = "simple-audio-card";
76 simple-audio-card,name = "imx6qdl-icore-sgtl5000";
77 simple-audio-card,format = "i2s";
78 simple-audio-card,bitclock-master = <&dailink_master>;
79 simple-audio-card,frame-master = <&dailink_master>;
80 simple-audio-card,widgets =
81 "Microphone", "Mic Jack",
82 "Headphone", "Headphone Jack",
83 "Line", "Line In Jack",
84 "Speaker", "Line Out Jack",
86 simple-audio-card,routing =
88 "Mic Jack", "Mic Bias",
89 "Headphone Jack", "HP_OUT";
91 simple-audio-card,cpu {
95 dailink_master: simple-audio-card,codec {
96 sound-dai = <&sgtl5000>;
102 pinctrl-names = "default";
103 pinctrl-0 = <&pinctrl_audmux>;
108 fsl,audmux-port = <MX51_AUDMUX_PORT1_SSI0>;
110 (IMX_AUDMUX_V2_PTCR_TFSDIR |
111 IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT4) |
112 IMX_AUDMUX_V2_PTCR_TCLKDIR |
113 IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT4) |
114 IMX_AUDMUX_V2_PTCR_SYN)
115 IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT4)
120 fsl,audmux-port = <MX51_AUDMUX_PORT4>;
122 IMX_AUDMUX_V2_PTCR_SYN
123 IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0)
129 pinctrl-names = "default";
130 pinctrl-0 = <&pinctrl_flexcan1>;
131 xceiver-supply = <®_3p3v>;
135 pinctrl-names = "default";
136 pinctrl-0 = <&pinctrl_flexcan2>;
137 xceiver-supply = <®_3p3v>;
141 assigned-clocks = <&clks IMX6QDL_CLK_LVDS2_SEL>;
142 assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>;
146 pinctrl-names = "default";
147 pinctrl-0 = <&pinctrl_enet>;
148 phy-reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
149 clocks = <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET>, <&rmii_clk>;
155 pinctrl-names = "default";
156 pinctrl-0 = <&pinctrl_gpmi_nand>;
162 clock-frequency = <100000>;
163 pinctrl-names = "default";
164 pinctrl-0 = <&pinctrl_i2c1>;
169 clock-frequency = <100000>;
170 pinctrl-names = "default";
171 pinctrl-0 = <&pinctrl_i2c2>;
176 clock-frequency = <100000>;
177 pinctrl-names = "default";
178 pinctrl-0 = <&pinctrl_i2c3>;
182 compatible = "ovti,ov5640";
183 pinctrl-names = "default";
184 pinctrl-0 = <&pinctrl_ov5640>;
186 clocks = <&clks IMX6QDL_CLK_CKO>;
187 clock-names = "xclk";
188 DOVDD-supply = <®_1p8v>;
189 AVDD-supply = <®_3p3v>;
190 DVDD-supply = <®_3p3v>;
191 powerdown-gpios = <&gpio5 30 GPIO_ACTIVE_HIGH>;
192 reset-gpios = <&gpio5 31 GPIO_ACTIVE_LOW>;
196 ov5640_to_mipi_csi2: endpoint {
197 remote-endpoint = <&mipi_csi2_in>;
205 #sound-dai-cells = <0>;
206 compatible = "fsl,sgtl5000";
208 clocks = <&clks IMX6QDL_CLK_CKO>;
209 VDDA-supply = <®_2p5v>;
210 VDDIO-supply = <®_3p3v>;
211 VDDD-supply = <®_1p8v>;
221 mipi_csi2_in: endpoint {
222 remote-endpoint = <&ov5640_to_mipi_csi2>;
230 pinctrl-names = "default";
231 pinctrl-0 = <&pinctrl_pwm3>;
236 fsl,mode = "i2s-slave";
241 pinctrl-names = "default";
242 pinctrl-0 = <&pinctrl_uart4>;
247 vbus-supply = <®_usb_h1_vbus>;
248 disable-over-current;
253 vbus-supply = <®_usb_otg_vbus>;
254 pinctrl-names = "default";
255 pinctrl-0 = <&pinctrl_usbotg>;
256 disable-over-current;
261 pinctrl-names = "default";
262 pinctrl-0 = <&pinctrl_usdhc1>;
263 cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
269 pinctrl-names = "default";
270 pinctrl-0 = <&pinctrl_usdhc3>;
277 pinctrl_audmux: audmuxgrp {
279 MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
280 MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0
281 MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
282 MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
286 pinctrl_enet: enetgrp {
288 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
289 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b1
290 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
291 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
292 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
293 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
294 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
295 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
296 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
297 MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0
298 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
302 pinctrl_flexcan1: flexcan1grp {
304 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b020
305 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b020
309 pinctrl_flexcan2: flexcan2grp {
311 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b020
312 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b020
316 pinctrl_gpmi_nand: gpminandgrp {
318 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
319 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
320 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
321 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
322 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
323 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
324 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
325 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
326 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
327 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
328 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
329 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
330 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
331 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
332 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
333 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
334 MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
338 pinctrl_i2c1: i2c1grp {
340 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
341 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
345 pinctrl_i2c2: i2c2grp {
347 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
348 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
352 pinctrl_i2c3: i2c3grp {
354 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
355 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
359 pinctrl_ov5640: ov5640grp {
361 MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x1b0b0
362 MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x1b0b0
363 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
367 pinctrl_uart4: uart4grp {
369 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
370 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
374 pinctrl_pwm3: pwm3grp {
376 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
380 pinctrl_usbotg: usbotggrp {
382 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
386 pinctrl_usdhc1: usdhc1grp {
388 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17070
389 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10070
390 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17070
391 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17070
392 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17070
393 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17070
397 pinctrl_usdhc3: usdhc3grp {
399 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
400 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
401 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
402 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
403 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
404 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
405 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
406 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
407 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
408 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059