1 // SPDX-License-Identifier: GPL-2.0
3 // Copyright 2013 Freescale Semiconductor, Inc.
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include "imx6sl-pinfunc.h"
7 #include <dt-bindings/clock/imx6sl-clock.h>
13 * The decompressor and also some bootloaders rely on a
14 * pre-existing /chosen node to be available to insert the
15 * command line and merge other ATAGS info.
16 * Also for U-Boot there must be a pre-existing /memory node.
19 memory { device_type = "memory"; };
46 compatible = "arm,cortex-a9";
49 next-level-cache = <&L2>;
56 fsl,soc-operating-points = <
57 /* ARM kHz SOC-PU uV */
62 clock-latency = <61036>; /* two CLK32 periods */
63 clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
64 <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
65 <&clks IMX6SL_CLK_PLL1_SYS>;
66 clock-names = "arm", "pll2_pfd2_396m", "step",
67 "pll1_sw", "pll1_sys";
68 arm-supply = <®_arm>;
69 pu-supply = <®_pu>;
70 soc-supply = <®_soc>;
74 intc: interrupt-controller@a01000 {
75 compatible = "arm,cortex-a9-gic";
76 #interrupt-cells = <3>;
78 reg = <0x00a01000 0x1000>,
80 interrupt-parent = <&intc>;
85 compatible = "fixed-clock";
87 clock-frequency = <32768>;
91 compatible = "fixed-clock";
93 clock-frequency = <24000000>;
98 compatible = "fsl,imx6q-tempmon";
99 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
100 interrupt-parent = <&gpc>;
101 fsl,tempmon = <&anatop>;
102 fsl,tempmon-data = <&ocotp>;
103 clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>;
107 compatible = "arm,cortex-a9-pmu";
108 interrupt-parent = <&gpc>;
109 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
113 #address-cells = <1>;
115 compatible = "simple-bus";
116 interrupt-parent = <&gpc>;
120 compatible = "mmio-sram";
121 reg = <0x00900000 0x20000>;
122 clocks = <&clks IMX6SL_CLK_OCRAM>;
125 L2: l2-cache@a02000 {
126 compatible = "arm,pl310-cache";
127 reg = <0x00a02000 0x1000>;
128 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
131 arm,tag-latency = <4 2 3>;
132 arm,data-latency = <4 2 3>;
135 aips1: aips-bus@2000000 {
136 compatible = "fsl,aips-bus", "simple-bus";
137 #address-cells = <1>;
139 reg = <0x02000000 0x100000>;
142 spba: spba-bus@2000000 {
143 compatible = "fsl,spba-bus", "simple-bus";
144 #address-cells = <1>;
146 reg = <0x02000000 0x40000>;
149 spdif: spdif@2004000 {
150 compatible = "fsl,imx6sl-spdif",
152 reg = <0x02004000 0x4000>;
153 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
154 dmas = <&sdma 14 18 0>,
156 dma-names = "rx", "tx";
157 clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>,
158 <&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_DUMMY>,
159 <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_DUMMY>,
160 <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_DUMMY>,
161 <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_SPBA>;
162 clock-names = "core", "rxtx0",
170 ecspi1: ecspi@2008000 {
171 #address-cells = <1>;
173 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
174 reg = <0x02008000 0x4000>;
175 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
176 clocks = <&clks IMX6SL_CLK_ECSPI1>,
177 <&clks IMX6SL_CLK_ECSPI1>;
178 clock-names = "ipg", "per";
182 ecspi2: ecspi@200c000 {
183 #address-cells = <1>;
185 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
186 reg = <0x0200c000 0x4000>;
187 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
188 clocks = <&clks IMX6SL_CLK_ECSPI2>,
189 <&clks IMX6SL_CLK_ECSPI2>;
190 clock-names = "ipg", "per";
194 ecspi3: ecspi@2010000 {
195 #address-cells = <1>;
197 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
198 reg = <0x02010000 0x4000>;
199 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
200 clocks = <&clks IMX6SL_CLK_ECSPI3>,
201 <&clks IMX6SL_CLK_ECSPI3>;
202 clock-names = "ipg", "per";
206 ecspi4: ecspi@2014000 {
207 #address-cells = <1>;
209 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
210 reg = <0x02014000 0x4000>;
211 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
212 clocks = <&clks IMX6SL_CLK_ECSPI4>,
213 <&clks IMX6SL_CLK_ECSPI4>;
214 clock-names = "ipg", "per";
218 uart5: serial@2018000 {
219 compatible = "fsl,imx6sl-uart",
220 "fsl,imx6q-uart", "fsl,imx21-uart";
221 reg = <0x02018000 0x4000>;
222 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
223 clocks = <&clks IMX6SL_CLK_UART>,
224 <&clks IMX6SL_CLK_UART_SERIAL>;
225 clock-names = "ipg", "per";
226 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
227 dma-names = "rx", "tx";
231 uart1: serial@2020000 {
232 compatible = "fsl,imx6sl-uart",
233 "fsl,imx6q-uart", "fsl,imx21-uart";
234 reg = <0x02020000 0x4000>;
235 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
236 clocks = <&clks IMX6SL_CLK_UART>,
237 <&clks IMX6SL_CLK_UART_SERIAL>;
238 clock-names = "ipg", "per";
239 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
240 dma-names = "rx", "tx";
244 uart2: serial@2024000 {
245 compatible = "fsl,imx6sl-uart",
246 "fsl,imx6q-uart", "fsl,imx21-uart";
247 reg = <0x02024000 0x4000>;
248 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
249 clocks = <&clks IMX6SL_CLK_UART>,
250 <&clks IMX6SL_CLK_UART_SERIAL>;
251 clock-names = "ipg", "per";
252 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
253 dma-names = "rx", "tx";
258 #sound-dai-cells = <0>;
259 compatible = "fsl,imx6sl-ssi",
261 reg = <0x02028000 0x4000>;
262 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
263 clocks = <&clks IMX6SL_CLK_SSI1_IPG>,
264 <&clks IMX6SL_CLK_SSI1>;
265 clock-names = "ipg", "baud";
266 dmas = <&sdma 37 1 0>,
268 dma-names = "rx", "tx";
269 fsl,fifo-depth = <15>;
274 #sound-dai-cells = <0>;
275 compatible = "fsl,imx6sl-ssi",
277 reg = <0x0202c000 0x4000>;
278 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
279 clocks = <&clks IMX6SL_CLK_SSI2_IPG>,
280 <&clks IMX6SL_CLK_SSI2>;
281 clock-names = "ipg", "baud";
282 dmas = <&sdma 41 1 0>,
284 dma-names = "rx", "tx";
285 fsl,fifo-depth = <15>;
290 #sound-dai-cells = <0>;
291 compatible = "fsl,imx6sl-ssi",
293 reg = <0x02030000 0x4000>;
294 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
295 clocks = <&clks IMX6SL_CLK_SSI3_IPG>,
296 <&clks IMX6SL_CLK_SSI3>;
297 clock-names = "ipg", "baud";
298 dmas = <&sdma 45 1 0>,
300 dma-names = "rx", "tx";
301 fsl,fifo-depth = <15>;
305 uart3: serial@2034000 {
306 compatible = "fsl,imx6sl-uart",
307 "fsl,imx6q-uart", "fsl,imx21-uart";
308 reg = <0x02034000 0x4000>;
309 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
310 clocks = <&clks IMX6SL_CLK_UART>,
311 <&clks IMX6SL_CLK_UART_SERIAL>;
312 clock-names = "ipg", "per";
313 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
314 dma-names = "rx", "tx";
318 uart4: serial@2038000 {
319 compatible = "fsl,imx6sl-uart",
320 "fsl,imx6q-uart", "fsl,imx21-uart";
321 reg = <0x02038000 0x4000>;
322 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
323 clocks = <&clks IMX6SL_CLK_UART>,
324 <&clks IMX6SL_CLK_UART_SERIAL>;
325 clock-names = "ipg", "per";
326 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
327 dma-names = "rx", "tx";
334 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
335 reg = <0x02080000 0x4000>;
336 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
337 clocks = <&clks IMX6SL_CLK_PWM1>,
338 <&clks IMX6SL_CLK_PWM1>;
339 clock-names = "ipg", "per";
344 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
345 reg = <0x02084000 0x4000>;
346 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
347 clocks = <&clks IMX6SL_CLK_PWM2>,
348 <&clks IMX6SL_CLK_PWM2>;
349 clock-names = "ipg", "per";
354 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
355 reg = <0x02088000 0x4000>;
356 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
357 clocks = <&clks IMX6SL_CLK_PWM3>,
358 <&clks IMX6SL_CLK_PWM3>;
359 clock-names = "ipg", "per";
364 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
365 reg = <0x0208c000 0x4000>;
366 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
367 clocks = <&clks IMX6SL_CLK_PWM4>,
368 <&clks IMX6SL_CLK_PWM4>;
369 clock-names = "ipg", "per";
373 compatible = "fsl,imx6sl-gpt";
374 reg = <0x02098000 0x4000>;
375 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
376 clocks = <&clks IMX6SL_CLK_GPT>,
377 <&clks IMX6SL_CLK_GPT_SERIAL>;
378 clock-names = "ipg", "per";
381 gpio1: gpio@209c000 {
382 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
383 reg = <0x0209c000 0x4000>;
384 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
385 <0 67 IRQ_TYPE_LEVEL_HIGH>;
388 interrupt-controller;
389 #interrupt-cells = <2>;
390 gpio-ranges = <&iomuxc 0 22 1>, <&iomuxc 1 20 2>,
391 <&iomuxc 3 23 1>, <&iomuxc 4 25 1>,
392 <&iomuxc 5 24 1>, <&iomuxc 6 19 1>,
393 <&iomuxc 7 36 2>, <&iomuxc 9 44 8>,
394 <&iomuxc 17 38 6>, <&iomuxc 23 68 4>,
395 <&iomuxc 27 64 4>, <&iomuxc 31 52 1>;
398 gpio2: gpio@20a0000 {
399 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
400 reg = <0x020a0000 0x4000>;
401 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
402 <0 69 IRQ_TYPE_LEVEL_HIGH>;
405 interrupt-controller;
406 #interrupt-cells = <2>;
407 gpio-ranges = <&iomuxc 0 53 3>, <&iomuxc 3 72 2>,
408 <&iomuxc 5 34 2>, <&iomuxc 7 57 4>,
409 <&iomuxc 11 56 1>, <&iomuxc 12 61 3>,
410 <&iomuxc 15 107 1>, <&iomuxc 16 132 2>,
411 <&iomuxc 18 135 1>, <&iomuxc 19 134 1>,
412 <&iomuxc 20 108 2>, <&iomuxc 22 120 1>,
413 <&iomuxc 23 125 7>, <&iomuxc 30 110 2>;
416 gpio3: gpio@20a4000 {
417 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
418 reg = <0x020a4000 0x4000>;
419 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
420 <0 71 IRQ_TYPE_LEVEL_HIGH>;
423 interrupt-controller;
424 #interrupt-cells = <2>;
425 gpio-ranges = <&iomuxc 0 112 8>, <&iomuxc 8 121 4>,
426 <&iomuxc 12 97 4>, <&iomuxc 16 166 3>,
427 <&iomuxc 19 85 2>, <&iomuxc 21 137 2>,
428 <&iomuxc 23 136 1>, <&iomuxc 24 91 1>,
429 <&iomuxc 25 99 1>, <&iomuxc 26 92 1>,
430 <&iomuxc 27 100 1>, <&iomuxc 28 93 1>,
431 <&iomuxc 29 101 1>, <&iomuxc 30 94 1>,
435 gpio4: gpio@20a8000 {
436 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
437 reg = <0x020a8000 0x4000>;
438 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
439 <0 73 IRQ_TYPE_LEVEL_HIGH>;
442 interrupt-controller;
443 #interrupt-cells = <2>;
444 gpio-ranges = <&iomuxc 0 95 1>, <&iomuxc 1 103 1>,
445 <&iomuxc 2 96 1>, <&iomuxc 3 104 1>,
446 <&iomuxc 4 97 1>, <&iomuxc 5 105 1>,
447 <&iomuxc 6 98 1>, <&iomuxc 7 106 1>,
448 <&iomuxc 8 28 1>, <&iomuxc 9 27 1>,
449 <&iomuxc 10 26 1>, <&iomuxc 11 29 1>,
450 <&iomuxc 12 32 1>, <&iomuxc 13 31 1>,
451 <&iomuxc 14 30 1>, <&iomuxc 15 33 1>,
452 <&iomuxc 16 84 1>, <&iomuxc 17 79 2>,
453 <&iomuxc 19 78 1>, <&iomuxc 20 76 1>,
454 <&iomuxc 21 81 2>, <&iomuxc 23 75 1>,
455 <&iomuxc 24 83 1>, <&iomuxc 25 74 1>,
456 <&iomuxc 26 77 1>, <&iomuxc 27 159 1>,
457 <&iomuxc 28 154 1>, <&iomuxc 29 157 1>,
458 <&iomuxc 30 152 1>, <&iomuxc 31 156 1>;
461 gpio5: gpio@20ac000 {
462 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
463 reg = <0x020ac000 0x4000>;
464 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
465 <0 75 IRQ_TYPE_LEVEL_HIGH>;
468 interrupt-controller;
469 #interrupt-cells = <2>;
470 gpio-ranges = <&iomuxc 0 158 1>, <&iomuxc 1 151 1>,
471 <&iomuxc 2 155 1>, <&iomuxc 3 153 1>,
472 <&iomuxc 4 150 1>, <&iomuxc 5 149 1>,
473 <&iomuxc 6 144 1>, <&iomuxc 7 147 1>,
474 <&iomuxc 8 142 1>, <&iomuxc 9 146 1>,
475 <&iomuxc 10 148 1>, <&iomuxc 11 141 1>,
476 <&iomuxc 12 145 1>, <&iomuxc 13 143 1>,
477 <&iomuxc 14 140 1>, <&iomuxc 15 139 1>,
478 <&iomuxc 16 164 2>, <&iomuxc 18 160 1>,
479 <&iomuxc 19 162 1>, <&iomuxc 20 163 1>,
484 compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp";
485 reg = <0x020b8000 0x4000>;
486 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
487 clocks = <&clks IMX6SL_CLK_DUMMY>;
491 wdog1: wdog@20bc000 {
492 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
493 reg = <0x020bc000 0x4000>;
494 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
495 clocks = <&clks IMX6SL_CLK_DUMMY>;
498 wdog2: wdog@20c0000 {
499 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
500 reg = <0x020c0000 0x4000>;
501 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
502 clocks = <&clks IMX6SL_CLK_DUMMY>;
507 compatible = "fsl,imx6sl-ccm";
508 reg = <0x020c4000 0x4000>;
509 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
510 <0 88 IRQ_TYPE_LEVEL_HIGH>;
514 anatop: anatop@20c8000 {
515 compatible = "fsl,imx6sl-anatop",
517 "syscon", "simple-bus";
518 reg = <0x020c8000 0x1000>;
519 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
520 <0 54 IRQ_TYPE_LEVEL_HIGH>,
521 <0 127 IRQ_TYPE_LEVEL_HIGH>;
524 compatible = "fsl,anatop-regulator";
525 regulator-name = "vdd1p1";
526 regulator-min-microvolt = <800000>;
527 regulator-max-microvolt = <1375000>;
529 anatop-reg-offset = <0x110>;
530 anatop-vol-bit-shift = <8>;
531 anatop-vol-bit-width = <5>;
532 anatop-min-bit-val = <4>;
533 anatop-min-voltage = <800000>;
534 anatop-max-voltage = <1375000>;
535 anatop-enable-bit = <0>;
539 compatible = "fsl,anatop-regulator";
540 regulator-name = "vdd3p0";
541 regulator-min-microvolt = <2800000>;
542 regulator-max-microvolt = <3150000>;
544 anatop-reg-offset = <0x120>;
545 anatop-vol-bit-shift = <8>;
546 anatop-vol-bit-width = <5>;
547 anatop-min-bit-val = <0>;
548 anatop-min-voltage = <2625000>;
549 anatop-max-voltage = <3400000>;
550 anatop-enable-bit = <0>;
554 compatible = "fsl,anatop-regulator";
555 regulator-name = "vdd2p5";
556 regulator-min-microvolt = <2100000>;
557 regulator-max-microvolt = <2850000>;
559 anatop-reg-offset = <0x130>;
560 anatop-vol-bit-shift = <8>;
561 anatop-vol-bit-width = <5>;
562 anatop-min-bit-val = <0>;
563 anatop-min-voltage = <2100000>;
564 anatop-max-voltage = <2850000>;
565 anatop-enable-bit = <0>;
568 reg_arm: regulator-vddcore {
569 compatible = "fsl,anatop-regulator";
570 regulator-name = "vddarm";
571 regulator-min-microvolt = <725000>;
572 regulator-max-microvolt = <1450000>;
574 anatop-reg-offset = <0x140>;
575 anatop-vol-bit-shift = <0>;
576 anatop-vol-bit-width = <5>;
577 anatop-delay-reg-offset = <0x170>;
578 anatop-delay-bit-shift = <24>;
579 anatop-delay-bit-width = <2>;
580 anatop-min-bit-val = <1>;
581 anatop-min-voltage = <725000>;
582 anatop-max-voltage = <1450000>;
585 reg_pu: regulator-vddpu {
586 compatible = "fsl,anatop-regulator";
587 regulator-name = "vddpu";
588 regulator-min-microvolt = <725000>;
589 regulator-max-microvolt = <1450000>;
591 anatop-reg-offset = <0x140>;
592 anatop-vol-bit-shift = <9>;
593 anatop-vol-bit-width = <5>;
594 anatop-delay-reg-offset = <0x170>;
595 anatop-delay-bit-shift = <26>;
596 anatop-delay-bit-width = <2>;
597 anatop-min-bit-val = <1>;
598 anatop-min-voltage = <725000>;
599 anatop-max-voltage = <1450000>;
602 reg_soc: regulator-vddsoc {
603 compatible = "fsl,anatop-regulator";
604 regulator-name = "vddsoc";
605 regulator-min-microvolt = <725000>;
606 regulator-max-microvolt = <1450000>;
608 anatop-reg-offset = <0x140>;
609 anatop-vol-bit-shift = <18>;
610 anatop-vol-bit-width = <5>;
611 anatop-delay-reg-offset = <0x170>;
612 anatop-delay-bit-shift = <28>;
613 anatop-delay-bit-width = <2>;
614 anatop-min-bit-val = <1>;
615 anatop-min-voltage = <725000>;
616 anatop-max-voltage = <1450000>;
620 usbphy1: usbphy@20c9000 {
621 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
622 reg = <0x020c9000 0x1000>;
623 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
624 clocks = <&clks IMX6SL_CLK_USBPHY1>;
625 fsl,anatop = <&anatop>;
628 usbphy2: usbphy@20ca000 {
629 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
630 reg = <0x020ca000 0x1000>;
631 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
632 clocks = <&clks IMX6SL_CLK_USBPHY2>;
633 fsl,anatop = <&anatop>;
637 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
638 reg = <0x020cc000 0x4000>;
640 snvs_rtc: snvs-rtc-lp {
641 compatible = "fsl,sec-v4.0-mon-rtc-lp";
644 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
645 <0 20 IRQ_TYPE_LEVEL_HIGH>;
648 snvs_poweroff: snvs-poweroff {
649 compatible = "syscon-poweroff";
658 epit1: epit@20d0000 {
659 reg = <0x020d0000 0x4000>;
660 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
663 epit2: epit@20d4000 {
664 reg = <0x020d4000 0x4000>;
665 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
669 compatible = "fsl,imx6sl-src", "fsl,imx51-src";
670 reg = <0x020d8000 0x4000>;
671 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
672 <0 96 IRQ_TYPE_LEVEL_HIGH>;
677 compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
678 reg = <0x020dc000 0x4000>;
679 interrupt-controller;
680 #interrupt-cells = <3>;
681 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
682 interrupt-parent = <&intc>;
683 pu-supply = <®_pu>;
684 clocks = <&clks IMX6SL_CLK_GPU2D_OVG>,
685 <&clks IMX6SL_CLK_GPU2D_PODF>;
686 #power-domain-cells = <1>;
689 gpr: iomuxc-gpr@20e0000 {
690 compatible = "fsl,imx6sl-iomuxc-gpr",
691 "fsl,imx6q-iomuxc-gpr", "syscon";
692 reg = <0x020e0000 0x38>;
695 iomuxc: iomuxc@20e0000 {
696 compatible = "fsl,imx6sl-iomuxc";
697 reg = <0x020e0000 0x4000>;
701 reg = <0x020e4000 0x4000>;
702 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
706 reg = <0x020e8000 0x4000>;
707 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
711 compatible = "fsl,imx6sl-sdma", "fsl,imx6q-sdma";
712 reg = <0x020ec000 0x4000>;
713 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
714 clocks = <&clks IMX6SL_CLK_SDMA>,
715 <&clks IMX6SL_CLK_SDMA>;
716 clock-names = "ipg", "ahb";
718 /* imx6sl reuses imx6q sdma firmware */
719 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
723 reg = <0x020f0000 0x4000>;
724 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
728 reg = <0x020f4000 0x4000>;
729 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
732 lcdif: lcdif@20f8000 {
733 compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif";
734 reg = <0x020f8000 0x4000>;
735 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
736 clocks = <&clks IMX6SL_CLK_LCDIF_PIX>,
737 <&clks IMX6SL_CLK_LCDIF_AXI>,
738 <&clks IMX6SL_CLK_DUMMY>;
739 clock-names = "pix", "axi", "disp_axi";
744 compatible = "fsl,imx6sl-dcp", "fsl,imx28-dcp";
745 reg = <0x020fc000 0x4000>;
746 interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>,
747 <0 100 IRQ_TYPE_LEVEL_HIGH>,
748 <0 101 IRQ_TYPE_LEVEL_HIGH>;
752 aips2: aips-bus@2100000 {
753 compatible = "fsl,aips-bus", "simple-bus";
754 #address-cells = <1>;
756 reg = <0x02100000 0x100000>;
759 usbotg1: usb@2184000 {
760 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
761 reg = <0x02184000 0x200>;
762 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
763 clocks = <&clks IMX6SL_CLK_USBOH3>;
764 fsl,usbphy = <&usbphy1>;
765 fsl,usbmisc = <&usbmisc 0>;
766 ahb-burst-config = <0x0>;
767 tx-burst-size-dword = <0x10>;
768 rx-burst-size-dword = <0x10>;
772 usbotg2: usb@2184200 {
773 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
774 reg = <0x02184200 0x200>;
775 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
776 clocks = <&clks IMX6SL_CLK_USBOH3>;
777 fsl,usbphy = <&usbphy2>;
778 fsl,usbmisc = <&usbmisc 1>;
779 ahb-burst-config = <0x0>;
780 tx-burst-size-dword = <0x10>;
781 rx-burst-size-dword = <0x10>;
786 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
787 reg = <0x02184400 0x200>;
788 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
789 clocks = <&clks IMX6SL_CLK_USBOH3>;
790 fsl,usbmisc = <&usbmisc 2>;
792 ahb-burst-config = <0x0>;
793 tx-burst-size-dword = <0x10>;
794 rx-burst-size-dword = <0x10>;
798 usbmisc: usbmisc@2184800 {
800 compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
801 reg = <0x02184800 0x200>;
802 clocks = <&clks IMX6SL_CLK_USBOH3>;
805 fec: ethernet@2188000 {
806 compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
807 reg = <0x02188000 0x4000>;
808 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
809 clocks = <&clks IMX6SL_CLK_ENET>,
810 <&clks IMX6SL_CLK_ENET_REF>;
811 clock-names = "ipg", "ahb";
815 usdhc1: usdhc@2190000 {
816 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
817 reg = <0x02190000 0x4000>;
818 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
819 clocks = <&clks IMX6SL_CLK_USDHC1>,
820 <&clks IMX6SL_CLK_USDHC1>,
821 <&clks IMX6SL_CLK_USDHC1>;
822 clock-names = "ipg", "ahb", "per";
827 usdhc2: usdhc@2194000 {
828 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
829 reg = <0x02194000 0x4000>;
830 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
831 clocks = <&clks IMX6SL_CLK_USDHC2>,
832 <&clks IMX6SL_CLK_USDHC2>,
833 <&clks IMX6SL_CLK_USDHC2>;
834 clock-names = "ipg", "ahb", "per";
839 usdhc3: usdhc@2198000 {
840 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
841 reg = <0x02198000 0x4000>;
842 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
843 clocks = <&clks IMX6SL_CLK_USDHC3>,
844 <&clks IMX6SL_CLK_USDHC3>,
845 <&clks IMX6SL_CLK_USDHC3>;
846 clock-names = "ipg", "ahb", "per";
851 usdhc4: usdhc@219c000 {
852 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
853 reg = <0x0219c000 0x4000>;
854 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
855 clocks = <&clks IMX6SL_CLK_USDHC4>,
856 <&clks IMX6SL_CLK_USDHC4>,
857 <&clks IMX6SL_CLK_USDHC4>;
858 clock-names = "ipg", "ahb", "per";
864 #address-cells = <1>;
866 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
867 reg = <0x021a0000 0x4000>;
868 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
869 clocks = <&clks IMX6SL_CLK_I2C1>;
874 #address-cells = <1>;
876 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
877 reg = <0x021a4000 0x4000>;
878 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
879 clocks = <&clks IMX6SL_CLK_I2C2>;
884 #address-cells = <1>;
886 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
887 reg = <0x021a8000 0x4000>;
888 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
889 clocks = <&clks IMX6SL_CLK_I2C3>;
894 compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
895 reg = <0x021b0000 0x4000>;
899 reg = <0x021b4000 0x4000>;
900 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
904 #address-cells = <2>;
906 reg = <0x021b8000 0x4000>;
907 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
908 fsl,weim-cs-gpr = <&gpr>;
912 ocotp: ocotp@21bc000 {
913 compatible = "fsl,imx6sl-ocotp", "syscon";
914 reg = <0x021bc000 0x4000>;
915 clocks = <&clks IMX6SL_CLK_OCOTP>;
918 audmux: audmux@21d8000 {
919 compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux";
920 reg = <0x021d8000 0x4000>;