1 // SPDX-License-Identifier: GPL-2.0
3 // Copyright 2013 Freescale Semiconductor, Inc.
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include "imx6sl-pinfunc.h"
7 #include <dt-bindings/clock/imx6sl-clock.h>
13 * The decompressor and also some bootloaders rely on a
14 * pre-existing /chosen node to be available to insert the
15 * command line and merge other ATAGS info.
16 * Also for U-Boot there must be a pre-existing /memory node.
19 memory { device_type = "memory"; };
46 compatible = "arm,cortex-a9";
49 next-level-cache = <&L2>;
56 fsl,soc-operating-points = <
57 /* ARM kHz SOC-PU uV */
62 clock-latency = <61036>; /* two CLK32 periods */
64 clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
65 <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
66 <&clks IMX6SL_CLK_PLL1_SYS>;
67 clock-names = "arm", "pll2_pfd2_396m", "step",
68 "pll1_sw", "pll1_sys";
69 arm-supply = <®_arm>;
70 pu-supply = <®_pu>;
71 soc-supply = <®_soc>;
75 intc: interrupt-controller@a01000 {
76 compatible = "arm,cortex-a9-gic";
77 #interrupt-cells = <3>;
79 reg = <0x00a01000 0x1000>,
81 interrupt-parent = <&intc>;
86 compatible = "fixed-clock";
88 clock-frequency = <32768>;
92 compatible = "fixed-clock";
94 clock-frequency = <24000000>;
99 compatible = "fsl,imx6q-tempmon";
100 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
101 interrupt-parent = <&gpc>;
102 fsl,tempmon = <&anatop>;
103 fsl,tempmon-data = <&ocotp>;
104 clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>;
108 compatible = "arm,cortex-a9-pmu";
109 interrupt-parent = <&gpc>;
110 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
114 #address-cells = <1>;
116 compatible = "simple-bus";
117 interrupt-parent = <&gpc>;
121 compatible = "mmio-sram";
122 reg = <0x00900000 0x20000>;
123 clocks = <&clks IMX6SL_CLK_OCRAM>;
126 L2: l2-cache@a02000 {
127 compatible = "arm,pl310-cache";
128 reg = <0x00a02000 0x1000>;
129 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
132 arm,tag-latency = <4 2 3>;
133 arm,data-latency = <4 2 3>;
136 aips1: aips-bus@2000000 {
137 compatible = "fsl,aips-bus", "simple-bus";
138 #address-cells = <1>;
140 reg = <0x02000000 0x100000>;
143 spba: spba-bus@2000000 {
144 compatible = "fsl,spba-bus", "simple-bus";
145 #address-cells = <1>;
147 reg = <0x02000000 0x40000>;
150 spdif: spdif@2004000 {
151 compatible = "fsl,imx6sl-spdif",
153 reg = <0x02004000 0x4000>;
154 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
155 dmas = <&sdma 14 18 0>,
157 dma-names = "rx", "tx";
158 clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>,
159 <&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_DUMMY>,
160 <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_DUMMY>,
161 <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_DUMMY>,
162 <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_SPBA>;
163 clock-names = "core", "rxtx0",
171 ecspi1: spi@2008000 {
172 #address-cells = <1>;
174 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
175 reg = <0x02008000 0x4000>;
176 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
177 clocks = <&clks IMX6SL_CLK_ECSPI1>,
178 <&clks IMX6SL_CLK_ECSPI1>;
179 clock-names = "ipg", "per";
183 ecspi2: spi@200c000 {
184 #address-cells = <1>;
186 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
187 reg = <0x0200c000 0x4000>;
188 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
189 clocks = <&clks IMX6SL_CLK_ECSPI2>,
190 <&clks IMX6SL_CLK_ECSPI2>;
191 clock-names = "ipg", "per";
195 ecspi3: spi@2010000 {
196 #address-cells = <1>;
198 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
199 reg = <0x02010000 0x4000>;
200 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
201 clocks = <&clks IMX6SL_CLK_ECSPI3>,
202 <&clks IMX6SL_CLK_ECSPI3>;
203 clock-names = "ipg", "per";
207 ecspi4: spi@2014000 {
208 #address-cells = <1>;
210 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
211 reg = <0x02014000 0x4000>;
212 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
213 clocks = <&clks IMX6SL_CLK_ECSPI4>,
214 <&clks IMX6SL_CLK_ECSPI4>;
215 clock-names = "ipg", "per";
219 uart5: serial@2018000 {
220 compatible = "fsl,imx6sl-uart",
221 "fsl,imx6q-uart", "fsl,imx21-uart";
222 reg = <0x02018000 0x4000>;
223 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
224 clocks = <&clks IMX6SL_CLK_UART>,
225 <&clks IMX6SL_CLK_UART_SERIAL>;
226 clock-names = "ipg", "per";
227 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
228 dma-names = "rx", "tx";
232 uart1: serial@2020000 {
233 compatible = "fsl,imx6sl-uart",
234 "fsl,imx6q-uart", "fsl,imx21-uart";
235 reg = <0x02020000 0x4000>;
236 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
237 clocks = <&clks IMX6SL_CLK_UART>,
238 <&clks IMX6SL_CLK_UART_SERIAL>;
239 clock-names = "ipg", "per";
240 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
241 dma-names = "rx", "tx";
245 uart2: serial@2024000 {
246 compatible = "fsl,imx6sl-uart",
247 "fsl,imx6q-uart", "fsl,imx21-uart";
248 reg = <0x02024000 0x4000>;
249 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
250 clocks = <&clks IMX6SL_CLK_UART>,
251 <&clks IMX6SL_CLK_UART_SERIAL>;
252 clock-names = "ipg", "per";
253 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
254 dma-names = "rx", "tx";
259 #sound-dai-cells = <0>;
260 compatible = "fsl,imx6sl-ssi",
262 reg = <0x02028000 0x4000>;
263 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
264 clocks = <&clks IMX6SL_CLK_SSI1_IPG>,
265 <&clks IMX6SL_CLK_SSI1>;
266 clock-names = "ipg", "baud";
267 dmas = <&sdma 37 1 0>,
269 dma-names = "rx", "tx";
270 fsl,fifo-depth = <15>;
275 #sound-dai-cells = <0>;
276 compatible = "fsl,imx6sl-ssi",
278 reg = <0x0202c000 0x4000>;
279 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
280 clocks = <&clks IMX6SL_CLK_SSI2_IPG>,
281 <&clks IMX6SL_CLK_SSI2>;
282 clock-names = "ipg", "baud";
283 dmas = <&sdma 41 1 0>,
285 dma-names = "rx", "tx";
286 fsl,fifo-depth = <15>;
291 #sound-dai-cells = <0>;
292 compatible = "fsl,imx6sl-ssi",
294 reg = <0x02030000 0x4000>;
295 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
296 clocks = <&clks IMX6SL_CLK_SSI3_IPG>,
297 <&clks IMX6SL_CLK_SSI3>;
298 clock-names = "ipg", "baud";
299 dmas = <&sdma 45 1 0>,
301 dma-names = "rx", "tx";
302 fsl,fifo-depth = <15>;
306 uart3: serial@2034000 {
307 compatible = "fsl,imx6sl-uart",
308 "fsl,imx6q-uart", "fsl,imx21-uart";
309 reg = <0x02034000 0x4000>;
310 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
311 clocks = <&clks IMX6SL_CLK_UART>,
312 <&clks IMX6SL_CLK_UART_SERIAL>;
313 clock-names = "ipg", "per";
314 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
315 dma-names = "rx", "tx";
319 uart4: serial@2038000 {
320 compatible = "fsl,imx6sl-uart",
321 "fsl,imx6q-uart", "fsl,imx21-uart";
322 reg = <0x02038000 0x4000>;
323 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
324 clocks = <&clks IMX6SL_CLK_UART>,
325 <&clks IMX6SL_CLK_UART_SERIAL>;
326 clock-names = "ipg", "per";
327 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
328 dma-names = "rx", "tx";
335 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
336 reg = <0x02080000 0x4000>;
337 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
338 clocks = <&clks IMX6SL_CLK_PWM1>,
339 <&clks IMX6SL_CLK_PWM1>;
340 clock-names = "ipg", "per";
345 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
346 reg = <0x02084000 0x4000>;
347 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
348 clocks = <&clks IMX6SL_CLK_PWM2>,
349 <&clks IMX6SL_CLK_PWM2>;
350 clock-names = "ipg", "per";
355 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
356 reg = <0x02088000 0x4000>;
357 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
358 clocks = <&clks IMX6SL_CLK_PWM3>,
359 <&clks IMX6SL_CLK_PWM3>;
360 clock-names = "ipg", "per";
365 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
366 reg = <0x0208c000 0x4000>;
367 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
368 clocks = <&clks IMX6SL_CLK_PWM4>,
369 <&clks IMX6SL_CLK_PWM4>;
370 clock-names = "ipg", "per";
374 compatible = "fsl,imx6sl-gpt";
375 reg = <0x02098000 0x4000>;
376 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
377 clocks = <&clks IMX6SL_CLK_GPT>,
378 <&clks IMX6SL_CLK_GPT_SERIAL>;
379 clock-names = "ipg", "per";
382 gpio1: gpio@209c000 {
383 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
384 reg = <0x0209c000 0x4000>;
385 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
386 <0 67 IRQ_TYPE_LEVEL_HIGH>;
389 interrupt-controller;
390 #interrupt-cells = <2>;
391 gpio-ranges = <&iomuxc 0 22 1>, <&iomuxc 1 20 2>,
392 <&iomuxc 3 23 1>, <&iomuxc 4 25 1>,
393 <&iomuxc 5 24 1>, <&iomuxc 6 19 1>,
394 <&iomuxc 7 36 2>, <&iomuxc 9 44 8>,
395 <&iomuxc 17 38 6>, <&iomuxc 23 68 4>,
396 <&iomuxc 27 64 4>, <&iomuxc 31 52 1>;
399 gpio2: gpio@20a0000 {
400 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
401 reg = <0x020a0000 0x4000>;
402 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
403 <0 69 IRQ_TYPE_LEVEL_HIGH>;
406 interrupt-controller;
407 #interrupt-cells = <2>;
408 gpio-ranges = <&iomuxc 0 53 3>, <&iomuxc 3 72 2>,
409 <&iomuxc 5 34 2>, <&iomuxc 7 57 4>,
410 <&iomuxc 11 56 1>, <&iomuxc 12 61 3>,
411 <&iomuxc 15 107 1>, <&iomuxc 16 132 2>,
412 <&iomuxc 18 135 1>, <&iomuxc 19 134 1>,
413 <&iomuxc 20 108 2>, <&iomuxc 22 120 1>,
414 <&iomuxc 23 125 7>, <&iomuxc 30 110 2>;
417 gpio3: gpio@20a4000 {
418 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
419 reg = <0x020a4000 0x4000>;
420 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
421 <0 71 IRQ_TYPE_LEVEL_HIGH>;
424 interrupt-controller;
425 #interrupt-cells = <2>;
426 gpio-ranges = <&iomuxc 0 112 8>, <&iomuxc 8 121 4>,
427 <&iomuxc 12 97 4>, <&iomuxc 16 166 3>,
428 <&iomuxc 19 85 2>, <&iomuxc 21 137 2>,
429 <&iomuxc 23 136 1>, <&iomuxc 24 91 1>,
430 <&iomuxc 25 99 1>, <&iomuxc 26 92 1>,
431 <&iomuxc 27 100 1>, <&iomuxc 28 93 1>,
432 <&iomuxc 29 101 1>, <&iomuxc 30 94 1>,
436 gpio4: gpio@20a8000 {
437 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
438 reg = <0x020a8000 0x4000>;
439 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
440 <0 73 IRQ_TYPE_LEVEL_HIGH>;
443 interrupt-controller;
444 #interrupt-cells = <2>;
445 gpio-ranges = <&iomuxc 0 95 1>, <&iomuxc 1 103 1>,
446 <&iomuxc 2 96 1>, <&iomuxc 3 104 1>,
447 <&iomuxc 4 97 1>, <&iomuxc 5 105 1>,
448 <&iomuxc 6 98 1>, <&iomuxc 7 106 1>,
449 <&iomuxc 8 28 1>, <&iomuxc 9 27 1>,
450 <&iomuxc 10 26 1>, <&iomuxc 11 29 1>,
451 <&iomuxc 12 32 1>, <&iomuxc 13 31 1>,
452 <&iomuxc 14 30 1>, <&iomuxc 15 33 1>,
453 <&iomuxc 16 84 1>, <&iomuxc 17 79 2>,
454 <&iomuxc 19 78 1>, <&iomuxc 20 76 1>,
455 <&iomuxc 21 81 2>, <&iomuxc 23 75 1>,
456 <&iomuxc 24 83 1>, <&iomuxc 25 74 1>,
457 <&iomuxc 26 77 1>, <&iomuxc 27 159 1>,
458 <&iomuxc 28 154 1>, <&iomuxc 29 157 1>,
459 <&iomuxc 30 152 1>, <&iomuxc 31 156 1>;
462 gpio5: gpio@20ac000 {
463 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
464 reg = <0x020ac000 0x4000>;
465 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
466 <0 75 IRQ_TYPE_LEVEL_HIGH>;
469 interrupt-controller;
470 #interrupt-cells = <2>;
471 gpio-ranges = <&iomuxc 0 158 1>, <&iomuxc 1 151 1>,
472 <&iomuxc 2 155 1>, <&iomuxc 3 153 1>,
473 <&iomuxc 4 150 1>, <&iomuxc 5 149 1>,
474 <&iomuxc 6 144 1>, <&iomuxc 7 147 1>,
475 <&iomuxc 8 142 1>, <&iomuxc 9 146 1>,
476 <&iomuxc 10 148 1>, <&iomuxc 11 141 1>,
477 <&iomuxc 12 145 1>, <&iomuxc 13 143 1>,
478 <&iomuxc 14 140 1>, <&iomuxc 15 139 1>,
479 <&iomuxc 16 164 2>, <&iomuxc 18 160 1>,
480 <&iomuxc 19 162 1>, <&iomuxc 20 163 1>,
485 compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp";
486 reg = <0x020b8000 0x4000>;
487 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
488 clocks = <&clks IMX6SL_CLK_DUMMY>;
492 wdog1: wdog@20bc000 {
493 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
494 reg = <0x020bc000 0x4000>;
495 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
496 clocks = <&clks IMX6SL_CLK_DUMMY>;
499 wdog2: wdog@20c0000 {
500 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
501 reg = <0x020c0000 0x4000>;
502 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
503 clocks = <&clks IMX6SL_CLK_DUMMY>;
508 compatible = "fsl,imx6sl-ccm";
509 reg = <0x020c4000 0x4000>;
510 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
511 <0 88 IRQ_TYPE_LEVEL_HIGH>;
515 anatop: anatop@20c8000 {
516 compatible = "fsl,imx6sl-anatop",
518 "syscon", "simple-bus";
519 reg = <0x020c8000 0x1000>;
520 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
521 <0 54 IRQ_TYPE_LEVEL_HIGH>,
522 <0 127 IRQ_TYPE_LEVEL_HIGH>;
525 compatible = "fsl,anatop-regulator";
526 regulator-name = "vdd1p1";
527 regulator-min-microvolt = <1000000>;
528 regulator-max-microvolt = <1200000>;
530 anatop-reg-offset = <0x110>;
531 anatop-vol-bit-shift = <8>;
532 anatop-vol-bit-width = <5>;
533 anatop-min-bit-val = <4>;
534 anatop-min-voltage = <800000>;
535 anatop-max-voltage = <1375000>;
536 anatop-enable-bit = <0>;
540 compatible = "fsl,anatop-regulator";
541 regulator-name = "vdd3p0";
542 regulator-min-microvolt = <2800000>;
543 regulator-max-microvolt = <3150000>;
545 anatop-reg-offset = <0x120>;
546 anatop-vol-bit-shift = <8>;
547 anatop-vol-bit-width = <5>;
548 anatop-min-bit-val = <0>;
549 anatop-min-voltage = <2625000>;
550 anatop-max-voltage = <3400000>;
551 anatop-enable-bit = <0>;
555 compatible = "fsl,anatop-regulator";
556 regulator-name = "vdd2p5";
557 regulator-min-microvolt = <2250000>;
558 regulator-max-microvolt = <2750000>;
560 anatop-reg-offset = <0x130>;
561 anatop-vol-bit-shift = <8>;
562 anatop-vol-bit-width = <5>;
563 anatop-min-bit-val = <0>;
564 anatop-min-voltage = <2100000>;
565 anatop-max-voltage = <2850000>;
566 anatop-enable-bit = <0>;
569 reg_arm: regulator-vddcore {
570 compatible = "fsl,anatop-regulator";
571 regulator-name = "vddarm";
572 regulator-min-microvolt = <725000>;
573 regulator-max-microvolt = <1450000>;
575 anatop-reg-offset = <0x140>;
576 anatop-vol-bit-shift = <0>;
577 anatop-vol-bit-width = <5>;
578 anatop-delay-reg-offset = <0x170>;
579 anatop-delay-bit-shift = <24>;
580 anatop-delay-bit-width = <2>;
581 anatop-min-bit-val = <1>;
582 anatop-min-voltage = <725000>;
583 anatop-max-voltage = <1450000>;
586 reg_pu: regulator-vddpu {
587 compatible = "fsl,anatop-regulator";
588 regulator-name = "vddpu";
589 regulator-min-microvolt = <725000>;
590 regulator-max-microvolt = <1450000>;
592 anatop-reg-offset = <0x140>;
593 anatop-vol-bit-shift = <9>;
594 anatop-vol-bit-width = <5>;
595 anatop-delay-reg-offset = <0x170>;
596 anatop-delay-bit-shift = <26>;
597 anatop-delay-bit-width = <2>;
598 anatop-min-bit-val = <1>;
599 anatop-min-voltage = <725000>;
600 anatop-max-voltage = <1450000>;
603 reg_soc: regulator-vddsoc {
604 compatible = "fsl,anatop-regulator";
605 regulator-name = "vddsoc";
606 regulator-min-microvolt = <725000>;
607 regulator-max-microvolt = <1450000>;
609 anatop-reg-offset = <0x140>;
610 anatop-vol-bit-shift = <18>;
611 anatop-vol-bit-width = <5>;
612 anatop-delay-reg-offset = <0x170>;
613 anatop-delay-bit-shift = <28>;
614 anatop-delay-bit-width = <2>;
615 anatop-min-bit-val = <1>;
616 anatop-min-voltage = <725000>;
617 anatop-max-voltage = <1450000>;
621 usbphy1: usbphy@20c9000 {
622 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
623 reg = <0x020c9000 0x1000>;
624 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
625 clocks = <&clks IMX6SL_CLK_USBPHY1>;
626 fsl,anatop = <&anatop>;
629 usbphy2: usbphy@20ca000 {
630 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
631 reg = <0x020ca000 0x1000>;
632 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
633 clocks = <&clks IMX6SL_CLK_USBPHY2>;
634 fsl,anatop = <&anatop>;
638 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
639 reg = <0x020cc000 0x4000>;
641 snvs_rtc: snvs-rtc-lp {
642 compatible = "fsl,sec-v4.0-mon-rtc-lp";
645 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
646 <0 20 IRQ_TYPE_LEVEL_HIGH>;
649 snvs_poweroff: snvs-poweroff {
650 compatible = "syscon-poweroff";
659 epit1: epit@20d0000 {
660 reg = <0x020d0000 0x4000>;
661 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
664 epit2: epit@20d4000 {
665 reg = <0x020d4000 0x4000>;
666 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
670 compatible = "fsl,imx6sl-src", "fsl,imx51-src";
671 reg = <0x020d8000 0x4000>;
672 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
673 <0 96 IRQ_TYPE_LEVEL_HIGH>;
678 compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
679 reg = <0x020dc000 0x4000>;
680 interrupt-controller;
681 #interrupt-cells = <3>;
682 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
683 interrupt-parent = <&intc>;
684 clocks = <&clks IMX6SL_CLK_IPG>;
688 #address-cells = <1>;
693 #power-domain-cells = <0>;
696 pd_pu: power-domain@1 {
698 #power-domain-cells = <0>;
699 power-supply = <®_pu>;
700 clocks = <&clks IMX6SL_CLK_GPU2D_OVG>,
701 <&clks IMX6SL_CLK_GPU2D_PODF>;
704 pd_disp: power-domain@2 {
706 #power-domain-cells = <0>;
707 clocks = <&clks IMX6SL_CLK_LCDIF_AXI>,
708 <&clks IMX6SL_CLK_LCDIF_PIX>,
709 <&clks IMX6SL_CLK_EPDC_AXI>,
710 <&clks IMX6SL_CLK_EPDC_PIX>,
711 <&clks IMX6SL_CLK_PXP_AXI>;
716 gpr: iomuxc-gpr@20e0000 {
717 compatible = "fsl,imx6sl-iomuxc-gpr",
718 "fsl,imx6q-iomuxc-gpr", "syscon";
719 reg = <0x020e0000 0x38>;
722 iomuxc: iomuxc@20e0000 {
723 compatible = "fsl,imx6sl-iomuxc";
724 reg = <0x020e0000 0x4000>;
728 reg = <0x020e4000 0x4000>;
729 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
733 reg = <0x020e8000 0x4000>;
734 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
738 compatible = "fsl,imx6sl-sdma", "fsl,imx6q-sdma";
739 reg = <0x020ec000 0x4000>;
740 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
741 clocks = <&clks IMX6SL_CLK_SDMA>,
742 <&clks IMX6SL_CLK_SDMA>;
743 clock-names = "ipg", "ahb";
745 /* imx6sl reuses imx6q sdma firmware */
746 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
750 reg = <0x020f0000 0x4000>;
751 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
755 reg = <0x020f4000 0x4000>;
756 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
759 lcdif: lcdif@20f8000 {
760 compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif";
761 reg = <0x020f8000 0x4000>;
762 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
763 clocks = <&clks IMX6SL_CLK_LCDIF_PIX>,
764 <&clks IMX6SL_CLK_LCDIF_AXI>,
765 <&clks IMX6SL_CLK_DUMMY>;
766 clock-names = "pix", "axi", "disp_axi";
768 power-domains = <&pd_disp>;
772 compatible = "fsl,imx6sl-dcp", "fsl,imx28-dcp";
773 reg = <0x020fc000 0x4000>;
774 interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>,
775 <0 100 IRQ_TYPE_LEVEL_HIGH>,
776 <0 101 IRQ_TYPE_LEVEL_HIGH>;
780 aips2: aips-bus@2100000 {
781 compatible = "fsl,aips-bus", "simple-bus";
782 #address-cells = <1>;
784 reg = <0x02100000 0x100000>;
787 usbotg1: usb@2184000 {
788 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
789 reg = <0x02184000 0x200>;
790 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
791 clocks = <&clks IMX6SL_CLK_USBOH3>;
792 fsl,usbphy = <&usbphy1>;
793 fsl,usbmisc = <&usbmisc 0>;
794 ahb-burst-config = <0x0>;
795 tx-burst-size-dword = <0x10>;
796 rx-burst-size-dword = <0x10>;
800 usbotg2: usb@2184200 {
801 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
802 reg = <0x02184200 0x200>;
803 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
804 clocks = <&clks IMX6SL_CLK_USBOH3>;
805 fsl,usbphy = <&usbphy2>;
806 fsl,usbmisc = <&usbmisc 1>;
807 ahb-burst-config = <0x0>;
808 tx-burst-size-dword = <0x10>;
809 rx-burst-size-dword = <0x10>;
814 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
815 reg = <0x02184400 0x200>;
816 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
817 clocks = <&clks IMX6SL_CLK_USBOH3>;
818 fsl,usbmisc = <&usbmisc 2>;
820 ahb-burst-config = <0x0>;
821 tx-burst-size-dword = <0x10>;
822 rx-burst-size-dword = <0x10>;
826 usbmisc: usbmisc@2184800 {
828 compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
829 reg = <0x02184800 0x200>;
830 clocks = <&clks IMX6SL_CLK_USBOH3>;
833 fec: ethernet@2188000 {
834 compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
835 reg = <0x02188000 0x4000>;
836 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
837 clocks = <&clks IMX6SL_CLK_ENET>,
838 <&clks IMX6SL_CLK_ENET_REF>;
839 clock-names = "ipg", "ahb";
843 usdhc1: usdhc@2190000 {
844 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
845 reg = <0x02190000 0x4000>;
846 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
847 clocks = <&clks IMX6SL_CLK_USDHC1>,
848 <&clks IMX6SL_CLK_USDHC1>,
849 <&clks IMX6SL_CLK_USDHC1>;
850 clock-names = "ipg", "ahb", "per";
855 usdhc2: usdhc@2194000 {
856 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
857 reg = <0x02194000 0x4000>;
858 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
859 clocks = <&clks IMX6SL_CLK_USDHC2>,
860 <&clks IMX6SL_CLK_USDHC2>,
861 <&clks IMX6SL_CLK_USDHC2>;
862 clock-names = "ipg", "ahb", "per";
867 usdhc3: usdhc@2198000 {
868 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
869 reg = <0x02198000 0x4000>;
870 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
871 clocks = <&clks IMX6SL_CLK_USDHC3>,
872 <&clks IMX6SL_CLK_USDHC3>,
873 <&clks IMX6SL_CLK_USDHC3>;
874 clock-names = "ipg", "ahb", "per";
879 usdhc4: usdhc@219c000 {
880 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
881 reg = <0x0219c000 0x4000>;
882 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
883 clocks = <&clks IMX6SL_CLK_USDHC4>,
884 <&clks IMX6SL_CLK_USDHC4>,
885 <&clks IMX6SL_CLK_USDHC4>;
886 clock-names = "ipg", "ahb", "per";
892 #address-cells = <1>;
894 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
895 reg = <0x021a0000 0x4000>;
896 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
897 clocks = <&clks IMX6SL_CLK_I2C1>;
902 #address-cells = <1>;
904 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
905 reg = <0x021a4000 0x4000>;
906 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
907 clocks = <&clks IMX6SL_CLK_I2C2>;
912 #address-cells = <1>;
914 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
915 reg = <0x021a8000 0x4000>;
916 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
917 clocks = <&clks IMX6SL_CLK_I2C3>;
922 compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
923 reg = <0x021b0000 0x4000>;
927 reg = <0x021b4000 0x4000>;
928 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
932 #address-cells = <2>;
934 reg = <0x021b8000 0x4000>;
935 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
936 fsl,weim-cs-gpr = <&gpr>;
940 ocotp: ocotp@21bc000 {
941 compatible = "fsl,imx6sl-ocotp", "syscon";
942 reg = <0x021bc000 0x4000>;
943 clocks = <&clks IMX6SL_CLK_OCOTP>;
946 audmux: audmux@21d8000 {
947 compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux";
948 reg = <0x021d8000 0x4000>;
953 gpu_2d: gpu@2200000 {
954 compatible = "vivante,gc";
955 reg = <0x02200000 0x4000>;
956 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
957 clocks = <&clks IMX6SL_CLK_MMDC_ROOT>,
958 <&clks IMX6SL_CLK_GPU2D_OVG>;
959 clock-names = "bus", "core";
960 power-domains = <&pd_pu>;
963 gpu_vg: gpu@2204000 {
964 compatible = "vivante,gc";
965 reg = <0x02204000 0x4000>;
966 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
967 clocks = <&clks IMX6SL_CLK_MMDC_ROOT>,
968 <&clks IMX6SL_CLK_GPU2D_OVG>;
969 clock-names = "bus", "core";
970 power-domains = <&pd_pu>;