1 // SPDX-License-Identifier: GPL-2.0
3 // Copyright 2013 Freescale Semiconductor, Inc.
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include "imx6sl-pinfunc.h"
7 #include <dt-bindings/clock/imx6sl-clock.h>
13 * The decompressor and also some bootloaders rely on a
14 * pre-existing /chosen node to be available to insert the
15 * command line and merge other ATAGS info.
51 compatible = "arm,cortex-a9";
54 next-level-cache = <&L2>;
61 fsl,soc-operating-points = <
62 /* ARM kHz SOC-PU uV */
67 clock-latency = <61036>; /* two CLK32 periods */
69 clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
70 <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
71 <&clks IMX6SL_CLK_PLL1_SYS>;
72 clock-names = "arm", "pll2_pfd2_396m", "step",
73 "pll1_sw", "pll1_sys";
74 arm-supply = <®_arm>;
75 pu-supply = <®_pu>;
76 soc-supply = <®_soc>;
77 nvmem-cells = <&cpu_speed_grade>;
78 nvmem-cell-names = "speed_grade";
84 compatible = "fixed-clock";
86 clock-frequency = <32768>;
90 compatible = "fixed-clock";
92 clock-frequency = <24000000>;
97 compatible = "fsl,imx6q-tempmon";
98 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
99 interrupt-parent = <&gpc>;
100 fsl,tempmon = <&anatop>;
101 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
102 nvmem-cell-names = "calib", "temp_grade";
103 clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>;
107 compatible = "arm,cortex-a9-pmu";
108 interrupt-parent = <&gpc>;
109 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
112 usbphynop1: usbphynop1 {
113 compatible = "usb-nop-xceiv";
118 #address-cells = <1>;
120 compatible = "simple-bus";
121 interrupt-parent = <&gpc>;
125 compatible = "mmio-sram";
126 reg = <0x00900000 0x20000>;
127 clocks = <&clks IMX6SL_CLK_OCRAM>;
130 intc: interrupt-controller@a01000 {
131 compatible = "arm,cortex-a9-gic";
132 #interrupt-cells = <3>;
133 interrupt-controller;
134 reg = <0x00a01000 0x1000>,
136 interrupt-parent = <&intc>;
139 L2: l2-cache@a02000 {
140 compatible = "arm,pl310-cache";
141 reg = <0x00a02000 0x1000>;
142 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
145 arm,tag-latency = <4 2 3>;
146 arm,data-latency = <4 2 3>;
150 compatible = "fsl,aips-bus", "simple-bus";
151 #address-cells = <1>;
153 reg = <0x02000000 0x100000>;
156 spba: spba-bus@2000000 {
157 compatible = "fsl,spba-bus", "simple-bus";
158 #address-cells = <1>;
160 reg = <0x02000000 0x40000>;
163 spdif: spdif@2004000 {
164 compatible = "fsl,imx6sl-spdif",
166 reg = <0x02004000 0x4000>;
167 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
168 dmas = <&sdma 14 18 0>,
170 dma-names = "rx", "tx";
171 clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>,
172 <&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_DUMMY>,
173 <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_DUMMY>,
174 <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_DUMMY>,
175 <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_SPBA>;
176 clock-names = "core", "rxtx0",
184 ecspi1: spi@2008000 {
185 #address-cells = <1>;
187 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
188 reg = <0x02008000 0x4000>;
189 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
190 clocks = <&clks IMX6SL_CLK_ECSPI1>,
191 <&clks IMX6SL_CLK_ECSPI1>;
192 clock-names = "ipg", "per";
196 ecspi2: spi@200c000 {
197 #address-cells = <1>;
199 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
200 reg = <0x0200c000 0x4000>;
201 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
202 clocks = <&clks IMX6SL_CLK_ECSPI2>,
203 <&clks IMX6SL_CLK_ECSPI2>;
204 clock-names = "ipg", "per";
208 ecspi3: spi@2010000 {
209 #address-cells = <1>;
211 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
212 reg = <0x02010000 0x4000>;
213 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
214 clocks = <&clks IMX6SL_CLK_ECSPI3>,
215 <&clks IMX6SL_CLK_ECSPI3>;
216 clock-names = "ipg", "per";
220 ecspi4: spi@2014000 {
221 #address-cells = <1>;
223 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
224 reg = <0x02014000 0x4000>;
225 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
226 clocks = <&clks IMX6SL_CLK_ECSPI4>,
227 <&clks IMX6SL_CLK_ECSPI4>;
228 clock-names = "ipg", "per";
232 uart5: serial@2018000 {
233 compatible = "fsl,imx6sl-uart",
234 "fsl,imx6q-uart", "fsl,imx21-uart";
235 reg = <0x02018000 0x4000>;
236 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
237 clocks = <&clks IMX6SL_CLK_UART>,
238 <&clks IMX6SL_CLK_UART_SERIAL>;
239 clock-names = "ipg", "per";
240 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
241 dma-names = "rx", "tx";
245 uart1: serial@2020000 {
246 compatible = "fsl,imx6sl-uart",
247 "fsl,imx6q-uart", "fsl,imx21-uart";
248 reg = <0x02020000 0x4000>;
249 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
250 clocks = <&clks IMX6SL_CLK_UART>,
251 <&clks IMX6SL_CLK_UART_SERIAL>;
252 clock-names = "ipg", "per";
253 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
254 dma-names = "rx", "tx";
258 uart2: serial@2024000 {
259 compatible = "fsl,imx6sl-uart",
260 "fsl,imx6q-uart", "fsl,imx21-uart";
261 reg = <0x02024000 0x4000>;
262 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
263 clocks = <&clks IMX6SL_CLK_UART>,
264 <&clks IMX6SL_CLK_UART_SERIAL>;
265 clock-names = "ipg", "per";
266 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
267 dma-names = "rx", "tx";
272 #sound-dai-cells = <0>;
273 compatible = "fsl,imx6sl-ssi",
275 reg = <0x02028000 0x4000>;
276 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
277 clocks = <&clks IMX6SL_CLK_SSI1_IPG>,
278 <&clks IMX6SL_CLK_SSI1>;
279 clock-names = "ipg", "baud";
280 dmas = <&sdma 37 1 0>,
282 dma-names = "rx", "tx";
283 fsl,fifo-depth = <15>;
288 #sound-dai-cells = <0>;
289 compatible = "fsl,imx6sl-ssi",
291 reg = <0x0202c000 0x4000>;
292 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
293 clocks = <&clks IMX6SL_CLK_SSI2_IPG>,
294 <&clks IMX6SL_CLK_SSI2>;
295 clock-names = "ipg", "baud";
296 dmas = <&sdma 41 1 0>,
298 dma-names = "rx", "tx";
299 fsl,fifo-depth = <15>;
304 #sound-dai-cells = <0>;
305 compatible = "fsl,imx6sl-ssi",
307 reg = <0x02030000 0x4000>;
308 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
309 clocks = <&clks IMX6SL_CLK_SSI3_IPG>,
310 <&clks IMX6SL_CLK_SSI3>;
311 clock-names = "ipg", "baud";
312 dmas = <&sdma 45 1 0>,
314 dma-names = "rx", "tx";
315 fsl,fifo-depth = <15>;
319 uart3: serial@2034000 {
320 compatible = "fsl,imx6sl-uart",
321 "fsl,imx6q-uart", "fsl,imx21-uart";
322 reg = <0x02034000 0x4000>;
323 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
324 clocks = <&clks IMX6SL_CLK_UART>,
325 <&clks IMX6SL_CLK_UART_SERIAL>;
326 clock-names = "ipg", "per";
327 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
328 dma-names = "rx", "tx";
332 uart4: serial@2038000 {
333 compatible = "fsl,imx6sl-uart",
334 "fsl,imx6q-uart", "fsl,imx21-uart";
335 reg = <0x02038000 0x4000>;
336 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
337 clocks = <&clks IMX6SL_CLK_UART>,
338 <&clks IMX6SL_CLK_UART_SERIAL>;
339 clock-names = "ipg", "per";
340 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
341 dma-names = "rx", "tx";
348 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
349 reg = <0x02080000 0x4000>;
350 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
351 clocks = <&clks IMX6SL_CLK_PERCLK>,
352 <&clks IMX6SL_CLK_PWM1>;
353 clock-names = "ipg", "per";
358 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
359 reg = <0x02084000 0x4000>;
360 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
361 clocks = <&clks IMX6SL_CLK_PERCLK>,
362 <&clks IMX6SL_CLK_PWM2>;
363 clock-names = "ipg", "per";
368 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
369 reg = <0x02088000 0x4000>;
370 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
371 clocks = <&clks IMX6SL_CLK_PERCLK>,
372 <&clks IMX6SL_CLK_PWM3>;
373 clock-names = "ipg", "per";
378 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
379 reg = <0x0208c000 0x4000>;
380 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
381 clocks = <&clks IMX6SL_CLK_PERCLK>,
382 <&clks IMX6SL_CLK_PWM4>;
383 clock-names = "ipg", "per";
387 compatible = "fsl,imx6sl-gpt";
388 reg = <0x02098000 0x4000>;
389 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
390 clocks = <&clks IMX6SL_CLK_GPT>,
391 <&clks IMX6SL_CLK_GPT_SERIAL>;
392 clock-names = "ipg", "per";
395 gpio1: gpio@209c000 {
396 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
397 reg = <0x0209c000 0x4000>;
398 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
399 <0 67 IRQ_TYPE_LEVEL_HIGH>;
402 interrupt-controller;
403 #interrupt-cells = <2>;
404 gpio-ranges = <&iomuxc 0 22 1>, <&iomuxc 1 20 2>,
405 <&iomuxc 3 23 1>, <&iomuxc 4 25 1>,
406 <&iomuxc 5 24 1>, <&iomuxc 6 19 1>,
407 <&iomuxc 7 36 2>, <&iomuxc 9 44 8>,
408 <&iomuxc 17 38 6>, <&iomuxc 23 68 4>,
409 <&iomuxc 27 64 4>, <&iomuxc 31 52 1>;
412 gpio2: gpio@20a0000 {
413 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
414 reg = <0x020a0000 0x4000>;
415 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
416 <0 69 IRQ_TYPE_LEVEL_HIGH>;
419 interrupt-controller;
420 #interrupt-cells = <2>;
421 gpio-ranges = <&iomuxc 0 53 3>, <&iomuxc 3 72 2>,
422 <&iomuxc 5 34 2>, <&iomuxc 7 57 4>,
423 <&iomuxc 11 56 1>, <&iomuxc 12 61 3>,
424 <&iomuxc 15 107 1>, <&iomuxc 16 132 2>,
425 <&iomuxc 18 135 1>, <&iomuxc 19 134 1>,
426 <&iomuxc 20 108 2>, <&iomuxc 22 120 1>,
427 <&iomuxc 23 125 7>, <&iomuxc 30 110 2>;
430 gpio3: gpio@20a4000 {
431 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
432 reg = <0x020a4000 0x4000>;
433 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
434 <0 71 IRQ_TYPE_LEVEL_HIGH>;
437 interrupt-controller;
438 #interrupt-cells = <2>;
439 gpio-ranges = <&iomuxc 0 112 8>, <&iomuxc 8 121 4>,
440 <&iomuxc 12 97 4>, <&iomuxc 16 166 3>,
441 <&iomuxc 19 85 2>, <&iomuxc 21 137 2>,
442 <&iomuxc 23 136 1>, <&iomuxc 24 91 1>,
443 <&iomuxc 25 99 1>, <&iomuxc 26 92 1>,
444 <&iomuxc 27 100 1>, <&iomuxc 28 93 1>,
445 <&iomuxc 29 101 1>, <&iomuxc 30 94 1>,
449 gpio4: gpio@20a8000 {
450 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
451 reg = <0x020a8000 0x4000>;
452 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
453 <0 73 IRQ_TYPE_LEVEL_HIGH>;
456 interrupt-controller;
457 #interrupt-cells = <2>;
458 gpio-ranges = <&iomuxc 0 95 1>, <&iomuxc 1 103 1>,
459 <&iomuxc 2 96 1>, <&iomuxc 3 104 1>,
460 <&iomuxc 4 97 1>, <&iomuxc 5 105 1>,
461 <&iomuxc 6 98 1>, <&iomuxc 7 106 1>,
462 <&iomuxc 8 28 1>, <&iomuxc 9 27 1>,
463 <&iomuxc 10 26 1>, <&iomuxc 11 29 1>,
464 <&iomuxc 12 32 1>, <&iomuxc 13 31 1>,
465 <&iomuxc 14 30 1>, <&iomuxc 15 33 1>,
466 <&iomuxc 16 84 1>, <&iomuxc 17 79 2>,
467 <&iomuxc 19 78 1>, <&iomuxc 20 76 1>,
468 <&iomuxc 21 81 2>, <&iomuxc 23 75 1>,
469 <&iomuxc 24 83 1>, <&iomuxc 25 74 1>,
470 <&iomuxc 26 77 1>, <&iomuxc 27 159 1>,
471 <&iomuxc 28 154 1>, <&iomuxc 29 157 1>,
472 <&iomuxc 30 152 1>, <&iomuxc 31 156 1>;
475 gpio5: gpio@20ac000 {
476 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
477 reg = <0x020ac000 0x4000>;
478 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
479 <0 75 IRQ_TYPE_LEVEL_HIGH>;
482 interrupt-controller;
483 #interrupt-cells = <2>;
484 gpio-ranges = <&iomuxc 0 158 1>, <&iomuxc 1 151 1>,
485 <&iomuxc 2 155 1>, <&iomuxc 3 153 1>,
486 <&iomuxc 4 150 1>, <&iomuxc 5 149 1>,
487 <&iomuxc 6 144 1>, <&iomuxc 7 147 1>,
488 <&iomuxc 8 142 1>, <&iomuxc 9 146 1>,
489 <&iomuxc 10 148 1>, <&iomuxc 11 141 1>,
490 <&iomuxc 12 145 1>, <&iomuxc 13 143 1>,
491 <&iomuxc 14 140 1>, <&iomuxc 15 139 1>,
492 <&iomuxc 16 164 2>, <&iomuxc 18 160 1>,
493 <&iomuxc 19 162 1>, <&iomuxc 20 163 1>,
497 kpp: keypad@20b8000 {
498 compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp";
499 reg = <0x020b8000 0x4000>;
500 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
501 clocks = <&clks IMX6SL_CLK_IPG>;
505 wdog1: watchdog@20bc000 {
506 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
507 reg = <0x020bc000 0x4000>;
508 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
509 clocks = <&clks IMX6SL_CLK_IPG>;
512 wdog2: watchdog@20c0000 {
513 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
514 reg = <0x020c0000 0x4000>;
515 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
516 clocks = <&clks IMX6SL_CLK_IPG>;
520 clks: clock-controller@20c4000 {
521 compatible = "fsl,imx6sl-ccm";
522 reg = <0x020c4000 0x4000>;
523 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
524 <0 88 IRQ_TYPE_LEVEL_HIGH>;
528 anatop: anatop@20c8000 {
529 compatible = "fsl,imx6sl-anatop",
531 "syscon", "simple-mfd";
532 reg = <0x020c8000 0x1000>;
533 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
534 <0 54 IRQ_TYPE_LEVEL_HIGH>,
535 <0 127 IRQ_TYPE_LEVEL_HIGH>;
537 reg_vdd1p1: regulator-1p1 {
538 compatible = "fsl,anatop-regulator";
539 regulator-name = "vdd1p1";
540 regulator-min-microvolt = <1000000>;
541 regulator-max-microvolt = <1200000>;
543 anatop-reg-offset = <0x110>;
544 anatop-vol-bit-shift = <8>;
545 anatop-vol-bit-width = <5>;
546 anatop-min-bit-val = <4>;
547 anatop-min-voltage = <800000>;
548 anatop-max-voltage = <1375000>;
549 anatop-enable-bit = <0>;
552 reg_vdd3p0: regulator-3p0 {
553 compatible = "fsl,anatop-regulator";
554 regulator-name = "vdd3p0";
555 regulator-min-microvolt = <2800000>;
556 regulator-max-microvolt = <3150000>;
558 anatop-reg-offset = <0x120>;
559 anatop-vol-bit-shift = <8>;
560 anatop-vol-bit-width = <5>;
561 anatop-min-bit-val = <0>;
562 anatop-min-voltage = <2625000>;
563 anatop-max-voltage = <3400000>;
564 anatop-enable-bit = <0>;
567 reg_vdd2p5: regulator-2p5 {
568 compatible = "fsl,anatop-regulator";
569 regulator-name = "vdd2p5";
570 regulator-min-microvolt = <2250000>;
571 regulator-max-microvolt = <2750000>;
573 anatop-reg-offset = <0x130>;
574 anatop-vol-bit-shift = <8>;
575 anatop-vol-bit-width = <5>;
576 anatop-min-bit-val = <0>;
577 anatop-min-voltage = <2100000>;
578 anatop-max-voltage = <2850000>;
579 anatop-enable-bit = <0>;
582 reg_arm: regulator-vddcore {
583 compatible = "fsl,anatop-regulator";
584 regulator-name = "vddarm";
585 regulator-min-microvolt = <725000>;
586 regulator-max-microvolt = <1450000>;
588 anatop-reg-offset = <0x140>;
589 anatop-vol-bit-shift = <0>;
590 anatop-vol-bit-width = <5>;
591 anatop-delay-reg-offset = <0x170>;
592 anatop-delay-bit-shift = <24>;
593 anatop-delay-bit-width = <2>;
594 anatop-min-bit-val = <1>;
595 anatop-min-voltage = <725000>;
596 anatop-max-voltage = <1450000>;
599 reg_pu: regulator-vddpu {
600 compatible = "fsl,anatop-regulator";
601 regulator-name = "vddpu";
602 regulator-min-microvolt = <725000>;
603 regulator-max-microvolt = <1450000>;
604 anatop-reg-offset = <0x140>;
605 anatop-vol-bit-shift = <9>;
606 anatop-vol-bit-width = <5>;
607 anatop-delay-reg-offset = <0x170>;
608 anatop-delay-bit-shift = <26>;
609 anatop-delay-bit-width = <2>;
610 anatop-min-bit-val = <1>;
611 anatop-min-voltage = <725000>;
612 anatop-max-voltage = <1450000>;
615 reg_soc: regulator-vddsoc {
616 compatible = "fsl,anatop-regulator";
617 regulator-name = "vddsoc";
618 regulator-min-microvolt = <725000>;
619 regulator-max-microvolt = <1450000>;
621 anatop-reg-offset = <0x140>;
622 anatop-vol-bit-shift = <18>;
623 anatop-vol-bit-width = <5>;
624 anatop-delay-reg-offset = <0x170>;
625 anatop-delay-bit-shift = <28>;
626 anatop-delay-bit-width = <2>;
627 anatop-min-bit-val = <1>;
628 anatop-min-voltage = <725000>;
629 anatop-max-voltage = <1450000>;
633 usbphy1: usbphy@20c9000 {
634 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
635 reg = <0x020c9000 0x1000>;
636 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
637 clocks = <&clks IMX6SL_CLK_USBPHY1>;
638 fsl,anatop = <&anatop>;
641 usbphy2: usbphy@20ca000 {
642 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
643 reg = <0x020ca000 0x1000>;
644 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
645 clocks = <&clks IMX6SL_CLK_USBPHY2>;
646 fsl,anatop = <&anatop>;
650 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
651 reg = <0x020cc000 0x4000>;
653 snvs_rtc: snvs-rtc-lp {
654 compatible = "fsl,sec-v4.0-mon-rtc-lp";
657 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
658 <0 20 IRQ_TYPE_LEVEL_HIGH>;
661 snvs_poweroff: snvs-poweroff {
662 compatible = "syscon-poweroff";
671 epit1: epit@20d0000 {
672 reg = <0x020d0000 0x4000>;
673 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
676 epit2: epit@20d4000 {
677 reg = <0x020d4000 0x4000>;
678 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
681 src: reset-controller@20d8000 {
682 compatible = "fsl,imx6sl-src", "fsl,imx51-src";
683 reg = <0x020d8000 0x4000>;
684 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
685 <0 96 IRQ_TYPE_LEVEL_HIGH>;
690 compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
691 reg = <0x020dc000 0x4000>;
692 interrupt-controller;
693 #interrupt-cells = <3>;
694 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
695 interrupt-parent = <&intc>;
696 clocks = <&clks IMX6SL_CLK_IPG>;
700 #address-cells = <1>;
705 #power-domain-cells = <0>;
708 pd_pu: power-domain@1 {
710 #power-domain-cells = <0>;
711 power-supply = <®_pu>;
712 clocks = <&clks IMX6SL_CLK_GPU2D_OVG>,
713 <&clks IMX6SL_CLK_GPU2D_PODF>;
716 pd_disp: power-domain@2 {
718 #power-domain-cells = <0>;
719 clocks = <&clks IMX6SL_CLK_LCDIF_AXI>,
720 <&clks IMX6SL_CLK_LCDIF_PIX>,
721 <&clks IMX6SL_CLK_EPDC_AXI>,
722 <&clks IMX6SL_CLK_EPDC_PIX>,
723 <&clks IMX6SL_CLK_PXP_AXI>;
728 gpr: iomuxc-gpr@20e0000 {
729 compatible = "fsl,imx6sl-iomuxc-gpr",
730 "fsl,imx6q-iomuxc-gpr", "syscon";
731 reg = <0x020e0000 0x38>;
734 iomuxc: pinctrl@20e0000 {
735 compatible = "fsl,imx6sl-iomuxc";
736 reg = <0x020e0000 0x4000>;
740 reg = <0x020e4000 0x4000>;
741 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
745 reg = <0x020e8000 0x4000>;
746 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
750 compatible = "fsl,imx6sl-sdma", "fsl,imx6q-sdma";
751 reg = <0x020ec000 0x4000>;
752 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
753 clocks = <&clks IMX6SL_CLK_SDMA>,
754 <&clks IMX6SL_CLK_AHB>;
755 clock-names = "ipg", "ahb";
757 /* imx6sl reuses imx6q sdma firmware */
758 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
762 reg = <0x020f0000 0x4000>;
763 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
767 reg = <0x020f4000 0x4000>;
768 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
771 lcdif: lcdif@20f8000 {
772 compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif";
773 reg = <0x020f8000 0x4000>;
774 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
775 clocks = <&clks IMX6SL_CLK_LCDIF_PIX>,
776 <&clks IMX6SL_CLK_LCDIF_AXI>,
777 <&clks IMX6SL_CLK_DUMMY>;
778 clock-names = "pix", "axi", "disp_axi";
780 power-domains = <&pd_disp>;
783 dcp: crypto@20fc000 {
784 compatible = "fsl,imx6sl-dcp", "fsl,imx28-dcp";
785 reg = <0x020fc000 0x4000>;
786 interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>,
787 <0 100 IRQ_TYPE_LEVEL_HIGH>,
788 <0 101 IRQ_TYPE_LEVEL_HIGH>;
793 compatible = "fsl,aips-bus", "simple-bus";
794 #address-cells = <1>;
796 reg = <0x02100000 0x100000>;
799 usbotg1: usb@2184000 {
800 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
801 reg = <0x02184000 0x200>;
802 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
803 clocks = <&clks IMX6SL_CLK_USBOH3>;
804 fsl,usbphy = <&usbphy1>;
805 fsl,usbmisc = <&usbmisc 0>;
806 ahb-burst-config = <0x0>;
807 tx-burst-size-dword = <0x10>;
808 rx-burst-size-dword = <0x10>;
812 usbotg2: usb@2184200 {
813 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
814 reg = <0x02184200 0x200>;
815 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
816 clocks = <&clks IMX6SL_CLK_USBOH3>;
817 fsl,usbphy = <&usbphy2>;
818 fsl,usbmisc = <&usbmisc 1>;
819 ahb-burst-config = <0x0>;
820 tx-burst-size-dword = <0x10>;
821 rx-burst-size-dword = <0x10>;
826 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
827 reg = <0x02184400 0x200>;
828 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
829 clocks = <&clks IMX6SL_CLK_USBOH3>;
830 fsl,usbphy = <&usbphynop1>;
832 fsl,usbmisc = <&usbmisc 2>;
834 ahb-burst-config = <0x0>;
835 tx-burst-size-dword = <0x10>;
836 rx-burst-size-dword = <0x10>;
840 usbmisc: usbmisc@2184800 {
842 compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
843 reg = <0x02184800 0x200>;
844 clocks = <&clks IMX6SL_CLK_USBOH3>;
847 fec: ethernet@2188000 {
848 compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
849 reg = <0x02188000 0x4000>;
850 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
851 clocks = <&clks IMX6SL_CLK_ENET>,
852 <&clks IMX6SL_CLK_ENET_REF>;
853 clock-names = "ipg", "ahb";
857 usdhc1: usdhc@2190000 {
858 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
859 reg = <0x02190000 0x4000>;
860 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
861 clocks = <&clks IMX6SL_CLK_USDHC1>,
862 <&clks IMX6SL_CLK_USDHC1>,
863 <&clks IMX6SL_CLK_USDHC1>;
864 clock-names = "ipg", "ahb", "per";
869 usdhc2: usdhc@2194000 {
870 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
871 reg = <0x02194000 0x4000>;
872 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
873 clocks = <&clks IMX6SL_CLK_USDHC2>,
874 <&clks IMX6SL_CLK_USDHC2>,
875 <&clks IMX6SL_CLK_USDHC2>;
876 clock-names = "ipg", "ahb", "per";
881 usdhc3: usdhc@2198000 {
882 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
883 reg = <0x02198000 0x4000>;
884 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
885 clocks = <&clks IMX6SL_CLK_USDHC3>,
886 <&clks IMX6SL_CLK_USDHC3>,
887 <&clks IMX6SL_CLK_USDHC3>;
888 clock-names = "ipg", "ahb", "per";
893 usdhc4: usdhc@219c000 {
894 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
895 reg = <0x0219c000 0x4000>;
896 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
897 clocks = <&clks IMX6SL_CLK_USDHC4>,
898 <&clks IMX6SL_CLK_USDHC4>,
899 <&clks IMX6SL_CLK_USDHC4>;
900 clock-names = "ipg", "ahb", "per";
906 #address-cells = <1>;
908 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
909 reg = <0x021a0000 0x4000>;
910 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
911 clocks = <&clks IMX6SL_CLK_I2C1>;
916 #address-cells = <1>;
918 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
919 reg = <0x021a4000 0x4000>;
920 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
921 clocks = <&clks IMX6SL_CLK_I2C2>;
926 #address-cells = <1>;
928 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
929 reg = <0x021a8000 0x4000>;
930 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
931 clocks = <&clks IMX6SL_CLK_I2C3>;
935 memory-controller@21b0000 {
936 compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
937 reg = <0x021b0000 0x4000>;
938 clocks = <&clks IMX6SL_CLK_MMDC_P0_IPG>;
942 reg = <0x021b4000 0x4000>;
943 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
947 #address-cells = <2>;
949 reg = <0x021b8000 0x4000>;
950 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
951 fsl,weim-cs-gpr = <&gpr>;
955 ocotp: ocotp-ctrl@21bc000 {
956 compatible = "fsl,imx6sl-ocotp", "syscon";
957 reg = <0x021bc000 0x4000>;
958 clocks = <&clks IMX6SL_CLK_OCOTP>;
959 #address-cells = <1>;
962 cpu_speed_grade: speed-grade@10 {
966 tempmon_calib: calib@38 {
970 tempmon_temp_grade: temp-grade@20 {
975 audmux: audmux@21d8000 {
976 compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux";
977 reg = <0x021d8000 0x4000>;
982 gpu_2d: gpu@2200000 {
983 compatible = "vivante,gc";
984 reg = <0x02200000 0x4000>;
985 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
986 clocks = <&clks IMX6SL_CLK_MMDC_ROOT>,
987 <&clks IMX6SL_CLK_GPU2D_OVG>;
988 clock-names = "bus", "core";
989 power-domains = <&pd_pu>;
992 gpu_vg: gpu@2204000 {
993 compatible = "vivante,gc";
994 reg = <0x02204000 0x4000>;
995 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
996 clocks = <&clks IMX6SL_CLK_MMDC_ROOT>,
997 <&clks IMX6SL_CLK_GPU2D_OVG>;
998 clock-names = "bus", "core";
999 power-domains = <&pd_pu>;