1 // SPDX-License-Identifier: GPL-2.0
3 // Copyright 2014 Freescale Semiconductor, Inc.
5 #include <dt-bindings/clock/imx6sx-clock.h>
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include "imx6sx-pinfunc.h"
15 * The decompressor and also some bootloaders rely on a
16 * pre-existing /chosen node to be available to insert the
17 * command line and merge other ATAGS info.
61 compatible = "arm,cortex-a9";
64 next-level-cache = <&L2>;
72 fsl,soc-operating-points = <
79 clock-latency = <61036>; /* two CLK32 periods */
81 clocks = <&clks IMX6SX_CLK_ARM>,
82 <&clks IMX6SX_CLK_PLL2_PFD2>,
83 <&clks IMX6SX_CLK_STEP>,
84 <&clks IMX6SX_CLK_PLL1_SW>,
85 <&clks IMX6SX_CLK_PLL1_SYS>;
86 clock-names = "arm", "pll2_pfd2_396m", "step",
87 "pll1_sw", "pll1_sys";
88 arm-supply = <®_arm>;
89 soc-supply = <®_soc>;
93 intc: interrupt-controller@a01000 {
94 compatible = "arm,cortex-a9-gic";
95 #interrupt-cells = <3>;
97 reg = <0x00a01000 0x1000>,
99 interrupt-parent = <&intc>;
103 compatible = "fixed-clock";
105 clock-frequency = <32768>;
106 clock-output-names = "ckil";
110 compatible = "fixed-clock";
112 clock-frequency = <24000000>;
113 clock-output-names = "osc";
116 ipp_di0: clock-ipp-di0 {
117 compatible = "fixed-clock";
119 clock-frequency = <0>;
120 clock-output-names = "ipp_di0";
123 ipp_di1: clock-ipp-di1 {
124 compatible = "fixed-clock";
126 clock-frequency = <0>;
127 clock-output-names = "ipp_di1";
130 anaclk1: clock-anaclk1 {
131 compatible = "fixed-clock";
133 clock-frequency = <0>;
134 clock-output-names = "anaclk1";
137 anaclk2: clock-anaclk2 {
138 compatible = "fixed-clock";
140 clock-frequency = <0>;
141 clock-output-names = "anaclk2";
145 compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon";
146 interrupt-parent = <&gpc>;
147 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
148 fsl,tempmon = <&anatop>;
149 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
150 nvmem-cell-names = "calib", "temp_grade";
151 clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
155 compatible = "arm,cortex-a9-pmu";
156 interrupt-parent = <&gpc>;
157 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
160 usbphynop1: usbphynop1 {
161 compatible = "usb-nop-xceiv";
166 #address-cells = <1>;
168 compatible = "simple-bus";
169 interrupt-parent = <&gpc>;
172 ocram_s: sram@8f8000 {
173 compatible = "mmio-sram";
174 reg = <0x008f8000 0x4000>;
175 clocks = <&clks IMX6SX_CLK_OCRAM_S>;
179 compatible = "mmio-sram";
180 reg = <0x00900000 0x20000>;
181 clocks = <&clks IMX6SX_CLK_OCRAM>;
184 L2: l2-cache@a02000 {
185 compatible = "arm,pl310-cache";
186 reg = <0x00a02000 0x1000>;
187 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
190 arm,tag-latency = <4 2 3>;
191 arm,data-latency = <4 2 3>;
195 compatible = "vivante,gc";
196 reg = <0x01800000 0x4000>;
197 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
198 clocks = <&clks IMX6SX_CLK_GPU>,
199 <&clks IMX6SX_CLK_GPU>,
200 <&clks IMX6SX_CLK_GPU>;
201 clock-names = "bus", "core", "shader";
202 power-domains = <&pd_pu>;
205 dma_apbh: dma-apbh@1804000 {
206 compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh";
207 reg = <0x01804000 0x2000>;
208 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
209 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
210 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
211 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
212 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
215 clocks = <&clks IMX6SX_CLK_APBH_DMA>;
218 gpmi: gpmi-nand@1806000{
219 compatible = "fsl,imx6sx-gpmi-nand";
220 #address-cells = <1>;
222 reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
223 reg-names = "gpmi-nand", "bch";
224 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
225 interrupt-names = "bch";
226 clocks = <&clks IMX6SX_CLK_GPMI_IO>,
227 <&clks IMX6SX_CLK_GPMI_APB>,
228 <&clks IMX6SX_CLK_GPMI_BCH>,
229 <&clks IMX6SX_CLK_GPMI_BCH_APB>,
230 <&clks IMX6SX_CLK_PER1_BCH>;
231 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
232 "gpmi_bch_apb", "per1_bch";
233 dmas = <&dma_apbh 0>;
238 aips1: aips-bus@2000000 {
239 compatible = "fsl,aips-bus", "simple-bus";
240 #address-cells = <1>;
242 reg = <0x02000000 0x100000>;
246 compatible = "fsl,spba-bus", "simple-bus";
247 #address-cells = <1>;
249 reg = <0x02000000 0x40000>;
252 spdif: spdif@2004000 {
253 compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif";
254 reg = <0x02004000 0x4000>;
255 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
256 dmas = <&sdma 14 18 0>,
258 dma-names = "rx", "tx";
259 clocks = <&clks IMX6SX_CLK_SPDIF_GCLK>,
260 <&clks IMX6SX_CLK_OSC>,
261 <&clks IMX6SX_CLK_SPDIF>,
262 <&clks 0>, <&clks 0>, <&clks 0>,
263 <&clks IMX6SX_CLK_IPG>,
264 <&clks 0>, <&clks 0>,
265 <&clks IMX6SX_CLK_SPBA>;
266 clock-names = "core", "rxtx0",
274 ecspi1: spi@2008000 {
275 #address-cells = <1>;
277 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
278 reg = <0x02008000 0x4000>;
279 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
280 clocks = <&clks IMX6SX_CLK_ECSPI1>,
281 <&clks IMX6SX_CLK_ECSPI1>;
282 clock-names = "ipg", "per";
286 ecspi2: spi@200c000 {
287 #address-cells = <1>;
289 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
290 reg = <0x0200c000 0x4000>;
291 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
292 clocks = <&clks IMX6SX_CLK_ECSPI2>,
293 <&clks IMX6SX_CLK_ECSPI2>;
294 clock-names = "ipg", "per";
298 ecspi3: spi@2010000 {
299 #address-cells = <1>;
301 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
302 reg = <0x02010000 0x4000>;
303 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&clks IMX6SX_CLK_ECSPI3>,
305 <&clks IMX6SX_CLK_ECSPI3>;
306 clock-names = "ipg", "per";
310 ecspi4: spi@2014000 {
311 #address-cells = <1>;
313 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
314 reg = <0x02014000 0x4000>;
315 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
316 clocks = <&clks IMX6SX_CLK_ECSPI4>,
317 <&clks IMX6SX_CLK_ECSPI4>;
318 clock-names = "ipg", "per";
322 uart1: serial@2020000 {
323 compatible = "fsl,imx6sx-uart",
324 "fsl,imx6q-uart", "fsl,imx21-uart";
325 reg = <0x02020000 0x4000>;
326 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
327 clocks = <&clks IMX6SX_CLK_UART_IPG>,
328 <&clks IMX6SX_CLK_UART_SERIAL>;
329 clock-names = "ipg", "per";
330 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
331 dma-names = "rx", "tx";
336 reg = <0x02024000 0x4000>;
337 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
338 clocks = <&clks IMX6SX_CLK_ESAI_IPG>,
339 <&clks IMX6SX_CLK_ESAI_MEM>,
340 <&clks IMX6SX_CLK_ESAI_EXTAL>,
341 <&clks IMX6SX_CLK_ESAI_IPG>,
342 <&clks IMX6SX_CLK_SPBA>;
343 clock-names = "core", "mem", "extal",
349 #sound-dai-cells = <0>;
350 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
351 reg = <0x02028000 0x4000>;
352 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
353 clocks = <&clks IMX6SX_CLK_SSI1_IPG>,
354 <&clks IMX6SX_CLK_SSI1>;
355 clock-names = "ipg", "baud";
356 dmas = <&sdma 37 1 0>, <&sdma 38 1 0>;
357 dma-names = "rx", "tx";
358 fsl,fifo-depth = <15>;
363 #sound-dai-cells = <0>;
364 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
365 reg = <0x0202c000 0x4000>;
366 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
367 clocks = <&clks IMX6SX_CLK_SSI2_IPG>,
368 <&clks IMX6SX_CLK_SSI2>;
369 clock-names = "ipg", "baud";
370 dmas = <&sdma 41 1 0>, <&sdma 42 1 0>;
371 dma-names = "rx", "tx";
372 fsl,fifo-depth = <15>;
377 #sound-dai-cells = <0>;
378 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
379 reg = <0x02030000 0x4000>;
380 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
381 clocks = <&clks IMX6SX_CLK_SSI3_IPG>,
382 <&clks IMX6SX_CLK_SSI3>;
383 clock-names = "ipg", "baud";
384 dmas = <&sdma 45 1 0>, <&sdma 46 1 0>;
385 dma-names = "rx", "tx";
386 fsl,fifo-depth = <15>;
391 reg = <0x02034000 0x4000>;
392 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
393 clocks = <&clks IMX6SX_CLK_ASRC_MEM>,
394 <&clks IMX6SX_CLK_ASRC_IPG>,
395 <&clks IMX6SX_CLK_SPDIF>,
396 <&clks IMX6SX_CLK_SPBA>;
397 clock-names = "mem", "ipg", "asrck", "spba";
398 dmas = <&sdma 17 20 1>, <&sdma 18 20 1>,
399 <&sdma 19 20 1>, <&sdma 20 20 1>,
400 <&sdma 21 20 1>, <&sdma 22 20 1>;
401 dma-names = "rxa", "rxb", "rxc",
408 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
409 reg = <0x02080000 0x4000>;
410 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
411 clocks = <&clks IMX6SX_CLK_PWM1>,
412 <&clks IMX6SX_CLK_PWM1>;
413 clock-names = "ipg", "per";
418 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
419 reg = <0x02084000 0x4000>;
420 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
421 clocks = <&clks IMX6SX_CLK_PWM2>,
422 <&clks IMX6SX_CLK_PWM2>;
423 clock-names = "ipg", "per";
428 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
429 reg = <0x02088000 0x4000>;
430 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
431 clocks = <&clks IMX6SX_CLK_PWM3>,
432 <&clks IMX6SX_CLK_PWM3>;
433 clock-names = "ipg", "per";
438 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
439 reg = <0x0208c000 0x4000>;
440 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
441 clocks = <&clks IMX6SX_CLK_PWM4>,
442 <&clks IMX6SX_CLK_PWM4>;
443 clock-names = "ipg", "per";
447 flexcan1: can@2090000 {
448 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
449 reg = <0x02090000 0x4000>;
450 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
451 clocks = <&clks IMX6SX_CLK_CAN1_IPG>,
452 <&clks IMX6SX_CLK_CAN1_SERIAL>;
453 clock-names = "ipg", "per";
454 fsl,stop-mode = <&gpr 0x10 1 0x10 17>;
458 flexcan2: can@2094000 {
459 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
460 reg = <0x02094000 0x4000>;
461 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
462 clocks = <&clks IMX6SX_CLK_CAN2_IPG>,
463 <&clks IMX6SX_CLK_CAN2_SERIAL>;
464 clock-names = "ipg", "per";
465 fsl,stop-mode = <&gpr 0x10 2 0x10 18>;
470 compatible = "fsl,imx6sx-gpt", "fsl,imx6dl-gpt";
471 reg = <0x02098000 0x4000>;
472 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
473 clocks = <&clks IMX6SX_CLK_GPT_BUS>,
474 <&clks IMX6SX_CLK_GPT_3M>;
475 clock-names = "ipg", "per";
478 gpio1: gpio@209c000 {
479 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
480 reg = <0x0209c000 0x4000>;
481 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
482 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
485 interrupt-controller;
486 #interrupt-cells = <2>;
487 gpio-ranges = <&iomuxc 0 5 26>;
490 gpio2: gpio@20a0000 {
491 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
492 reg = <0x020a0000 0x4000>;
493 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
494 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
497 interrupt-controller;
498 #interrupt-cells = <2>;
499 gpio-ranges = <&iomuxc 0 31 20>;
502 gpio3: gpio@20a4000 {
503 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
504 reg = <0x020a4000 0x4000>;
505 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
506 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
509 interrupt-controller;
510 #interrupt-cells = <2>;
511 gpio-ranges = <&iomuxc 0 51 29>;
514 gpio4: gpio@20a8000 {
515 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
516 reg = <0x020a8000 0x4000>;
517 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
518 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
521 interrupt-controller;
522 #interrupt-cells = <2>;
523 gpio-ranges = <&iomuxc 0 80 32>;
526 gpio5: gpio@20ac000 {
527 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
528 reg = <0x020ac000 0x4000>;
529 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
530 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
533 interrupt-controller;
534 #interrupt-cells = <2>;
535 gpio-ranges = <&iomuxc 0 112 24>;
538 gpio6: gpio@20b0000 {
539 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
540 reg = <0x020b0000 0x4000>;
541 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
542 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
545 interrupt-controller;
546 #interrupt-cells = <2>;
547 gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>;
550 gpio7: gpio@20b4000 {
551 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
552 reg = <0x020b4000 0x4000>;
553 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
554 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
557 interrupt-controller;
558 #interrupt-cells = <2>;
559 gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>;
563 compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp";
564 reg = <0x020b8000 0x4000>;
565 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
566 clocks = <&clks IMX6SX_CLK_IPG>;
570 wdog1: wdog@20bc000 {
571 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
572 reg = <0x020bc000 0x4000>;
573 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
574 clocks = <&clks IMX6SX_CLK_IPG>;
577 wdog2: wdog@20c0000 {
578 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
579 reg = <0x020c0000 0x4000>;
580 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
581 clocks = <&clks IMX6SX_CLK_IPG>;
586 compatible = "fsl,imx6sx-ccm";
587 reg = <0x020c4000 0x4000>;
588 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
589 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
591 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>, <&anaclk1>, <&anaclk2>;
592 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1", "anaclk1", "anaclk2";
595 anatop: anatop@20c8000 {
596 compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
597 "syscon", "simple-bus";
598 reg = <0x020c8000 0x1000>;
599 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
600 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
601 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
604 compatible = "fsl,anatop-regulator";
605 regulator-name = "vdd1p1";
606 regulator-min-microvolt = <1000000>;
607 regulator-max-microvolt = <1200000>;
609 anatop-reg-offset = <0x110>;
610 anatop-vol-bit-shift = <8>;
611 anatop-vol-bit-width = <5>;
612 anatop-min-bit-val = <4>;
613 anatop-min-voltage = <800000>;
614 anatop-max-voltage = <1375000>;
615 anatop-enable-bit = <0>;
619 compatible = "fsl,anatop-regulator";
620 regulator-name = "vdd3p0";
621 regulator-min-microvolt = <2800000>;
622 regulator-max-microvolt = <3150000>;
624 anatop-reg-offset = <0x120>;
625 anatop-vol-bit-shift = <8>;
626 anatop-vol-bit-width = <5>;
627 anatop-min-bit-val = <0>;
628 anatop-min-voltage = <2625000>;
629 anatop-max-voltage = <3400000>;
630 anatop-enable-bit = <0>;
634 compatible = "fsl,anatop-regulator";
635 regulator-name = "vdd2p5";
636 regulator-min-microvolt = <2250000>;
637 regulator-max-microvolt = <2750000>;
639 anatop-reg-offset = <0x130>;
640 anatop-vol-bit-shift = <8>;
641 anatop-vol-bit-width = <5>;
642 anatop-min-bit-val = <0>;
643 anatop-min-voltage = <2100000>;
644 anatop-max-voltage = <2875000>;
645 anatop-enable-bit = <0>;
648 reg_arm: regulator-vddcore {
649 compatible = "fsl,anatop-regulator";
650 regulator-name = "vddarm";
651 regulator-min-microvolt = <725000>;
652 regulator-max-microvolt = <1450000>;
654 anatop-reg-offset = <0x140>;
655 anatop-vol-bit-shift = <0>;
656 anatop-vol-bit-width = <5>;
657 anatop-delay-reg-offset = <0x170>;
658 anatop-delay-bit-shift = <24>;
659 anatop-delay-bit-width = <2>;
660 anatop-min-bit-val = <1>;
661 anatop-min-voltage = <725000>;
662 anatop-max-voltage = <1450000>;
665 reg_pcie: regulator-vddpcie {
666 compatible = "fsl,anatop-regulator";
667 regulator-name = "vddpcie";
668 regulator-min-microvolt = <725000>;
669 regulator-max-microvolt = <1450000>;
670 anatop-reg-offset = <0x140>;
671 anatop-vol-bit-shift = <9>;
672 anatop-vol-bit-width = <5>;
673 anatop-delay-reg-offset = <0x170>;
674 anatop-delay-bit-shift = <26>;
675 anatop-delay-bit-width = <2>;
676 anatop-min-bit-val = <1>;
677 anatop-min-voltage = <725000>;
678 anatop-max-voltage = <1450000>;
681 reg_soc: regulator-vddsoc {
682 compatible = "fsl,anatop-regulator";
683 regulator-name = "vddsoc";
684 regulator-min-microvolt = <725000>;
685 regulator-max-microvolt = <1450000>;
687 anatop-reg-offset = <0x140>;
688 anatop-vol-bit-shift = <18>;
689 anatop-vol-bit-width = <5>;
690 anatop-delay-reg-offset = <0x170>;
691 anatop-delay-bit-shift = <28>;
692 anatop-delay-bit-width = <2>;
693 anatop-min-bit-val = <1>;
694 anatop-min-voltage = <725000>;
695 anatop-max-voltage = <1450000>;
699 usbphy1: usbphy@20c9000 {
700 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
701 reg = <0x020c9000 0x1000>;
702 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
703 clocks = <&clks IMX6SX_CLK_USBPHY1>;
704 fsl,anatop = <&anatop>;
707 usbphy2: usbphy@20ca000 {
708 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
709 reg = <0x020ca000 0x1000>;
710 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
711 clocks = <&clks IMX6SX_CLK_USBPHY2>;
712 fsl,anatop = <&anatop>;
716 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
717 reg = <0x020cc000 0x4000>;
719 snvs_rtc: snvs-rtc-lp {
720 compatible = "fsl,sec-v4.0-mon-rtc-lp";
723 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
726 snvs_poweroff: snvs-poweroff {
727 compatible = "syscon-poweroff";
735 snvs_pwrkey: snvs-powerkey {
736 compatible = "fsl,sec-v4.0-pwrkey";
738 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
739 linux,keycode = <KEY_POWER>;
744 epit1: epit@20d0000 {
745 reg = <0x020d0000 0x4000>;
746 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
749 epit2: epit@20d4000 {
750 reg = <0x020d4000 0x4000>;
751 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
755 compatible = "fsl,imx6sx-src", "fsl,imx51-src";
756 reg = <0x020d8000 0x4000>;
757 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
758 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
763 compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
764 reg = <0x020dc000 0x4000>;
765 interrupt-controller;
766 #interrupt-cells = <3>;
767 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
768 interrupt-parent = <&intc>;
769 clocks = <&clks IMX6SX_CLK_IPG>;
773 #address-cells = <1>;
778 #power-domain-cells = <0>;
781 pd_pu: power-domain@1 {
783 #power-domain-cells = <0>;
784 power-supply = <®_soc>;
785 clocks = <&clks IMX6SX_CLK_GPU>;
788 pd_pci: power-domain@3 {
790 #power-domain-cells = <0>;
791 power-supply = <®_pcie>;
796 iomuxc: iomuxc@20e0000 {
797 compatible = "fsl,imx6sx-iomuxc";
798 reg = <0x020e0000 0x4000>;
801 gpr: iomuxc-gpr@20e4000 {
802 compatible = "fsl,imx6sx-iomuxc-gpr",
803 "fsl,imx6q-iomuxc-gpr", "syscon";
804 reg = <0x020e4000 0x4000>;
808 compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma";
809 reg = <0x020ec000 0x4000>;
810 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
811 clocks = <&clks IMX6SX_CLK_SDMA>,
812 <&clks IMX6SX_CLK_SDMA>;
813 clock-names = "ipg", "ahb";
815 /* imx6sx reuses imx6q sdma firmware */
816 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
820 aips2: aips-bus@2100000 {
821 compatible = "fsl,aips-bus", "simple-bus";
822 #address-cells = <1>;
824 reg = <0x02100000 0x100000>;
827 crypto: caam@2100000 {
828 compatible = "fsl,sec-v4.0";
829 #address-cells = <1>;
831 reg = <0x2100000 0x10000>;
832 ranges = <0 0x2100000 0x10000>;
833 interrupt-parent = <&intc>;
834 clocks = <&clks IMX6SX_CLK_CAAM_MEM>,
835 <&clks IMX6SX_CLK_CAAM_ACLK>,
836 <&clks IMX6SX_CLK_CAAM_IPG>,
837 <&clks IMX6SX_CLK_EIM_SLOW>;
838 clock-names = "mem", "aclk", "ipg", "emi_slow";
841 compatible = "fsl,sec-v4.0-job-ring";
842 reg = <0x1000 0x1000>;
843 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
847 compatible = "fsl,sec-v4.0-job-ring";
848 reg = <0x2000 0x1000>;
849 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
853 usbotg1: usb@2184000 {
854 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
855 reg = <0x02184000 0x200>;
856 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
857 clocks = <&clks IMX6SX_CLK_USBOH3>;
858 fsl,usbphy = <&usbphy1>;
859 fsl,usbmisc = <&usbmisc 0>;
860 fsl,anatop = <&anatop>;
861 ahb-burst-config = <0x0>;
862 tx-burst-size-dword = <0x10>;
863 rx-burst-size-dword = <0x10>;
867 usbotg2: usb@2184200 {
868 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
869 reg = <0x02184200 0x200>;
870 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
871 clocks = <&clks IMX6SX_CLK_USBOH3>;
872 fsl,usbphy = <&usbphy2>;
873 fsl,usbmisc = <&usbmisc 1>;
874 ahb-burst-config = <0x0>;
875 tx-burst-size-dword = <0x10>;
876 rx-burst-size-dword = <0x10>;
881 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
882 reg = <0x02184400 0x200>;
883 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
884 clocks = <&clks IMX6SX_CLK_USBOH3>;
885 fsl,usbphy = <&usbphynop1>;
886 fsl,usbmisc = <&usbmisc 2>;
888 fsl,anatop = <&anatop>;
890 ahb-burst-config = <0x0>;
891 tx-burst-size-dword = <0x10>;
892 rx-burst-size-dword = <0x10>;
896 usbmisc: usbmisc@2184800 {
898 compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc";
899 reg = <0x02184800 0x200>;
900 clocks = <&clks IMX6SX_CLK_USBOH3>;
903 fec1: ethernet@2188000 {
904 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
905 reg = <0x02188000 0x4000>;
906 interrupt-names = "int0", "pps";
907 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
908 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
909 clocks = <&clks IMX6SX_CLK_ENET>,
910 <&clks IMX6SX_CLK_ENET_AHB>,
911 <&clks IMX6SX_CLK_ENET_PTP>,
912 <&clks IMX6SX_CLK_ENET_REF>,
913 <&clks IMX6SX_CLK_ENET_PTP>;
914 clock-names = "ipg", "ahb", "ptp",
915 "enet_clk_ref", "enet_out";
916 fsl,num-tx-queues=<3>;
917 fsl,num-rx-queues=<3>;
922 reg = <0x0218c000 0x4000>;
923 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
924 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
925 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
926 clocks = <&clks IMX6SX_CLK_MLB>;
930 usdhc1: usdhc@2190000 {
931 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
932 reg = <0x02190000 0x4000>;
933 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
934 clocks = <&clks IMX6SX_CLK_USDHC1>,
935 <&clks IMX6SX_CLK_USDHC1>,
936 <&clks IMX6SX_CLK_USDHC1>;
937 clock-names = "ipg", "ahb", "per";
942 usdhc2: usdhc@2194000 {
943 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
944 reg = <0x02194000 0x4000>;
945 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
946 clocks = <&clks IMX6SX_CLK_USDHC2>,
947 <&clks IMX6SX_CLK_USDHC2>,
948 <&clks IMX6SX_CLK_USDHC2>;
949 clock-names = "ipg", "ahb", "per";
954 usdhc3: usdhc@2198000 {
955 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
956 reg = <0x02198000 0x4000>;
957 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
958 clocks = <&clks IMX6SX_CLK_USDHC3>,
959 <&clks IMX6SX_CLK_USDHC3>,
960 <&clks IMX6SX_CLK_USDHC3>;
961 clock-names = "ipg", "ahb", "per";
966 usdhc4: usdhc@219c000 {
967 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
968 reg = <0x0219c000 0x4000>;
969 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
970 clocks = <&clks IMX6SX_CLK_USDHC4>,
971 <&clks IMX6SX_CLK_USDHC4>,
972 <&clks IMX6SX_CLK_USDHC4>;
973 clock-names = "ipg", "ahb", "per";
979 #address-cells = <1>;
981 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
982 reg = <0x021a0000 0x4000>;
983 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
984 clocks = <&clks IMX6SX_CLK_I2C1>;
989 #address-cells = <1>;
991 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
992 reg = <0x021a4000 0x4000>;
993 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
994 clocks = <&clks IMX6SX_CLK_I2C2>;
999 #address-cells = <1>;
1001 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1002 reg = <0x021a8000 0x4000>;
1003 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1004 clocks = <&clks IMX6SX_CLK_I2C3>;
1005 status = "disabled";
1008 mmdc: mmdc@21b0000 {
1009 compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
1010 reg = <0x021b0000 0x4000>;
1011 clocks = <&clks IMX6SX_CLK_MMDC_P0_IPG>;
1014 fec2: ethernet@21b4000 {
1015 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
1016 reg = <0x021b4000 0x4000>;
1017 interrupt-names = "int0", "pps";
1018 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1019 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1020 clocks = <&clks IMX6SX_CLK_ENET>,
1021 <&clks IMX6SX_CLK_ENET_AHB>,
1022 <&clks IMX6SX_CLK_ENET_PTP>,
1023 <&clks IMX6SX_CLK_ENET2_REF_125M>,
1024 <&clks IMX6SX_CLK_ENET_PTP>;
1025 clock-names = "ipg", "ahb", "ptp",
1026 "enet_clk_ref", "enet_out";
1027 status = "disabled";
1030 weim: weim@21b8000 {
1031 #address-cells = <2>;
1033 compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim";
1034 reg = <0x021b8000 0x4000>;
1035 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1036 clocks = <&clks IMX6SX_CLK_EIM_SLOW>;
1037 fsl,weim-cs-gpr = <&gpr>;
1038 status = "disabled";
1041 ocotp: ocotp@21bc000 {
1042 #address-cells = <1>;
1044 compatible = "fsl,imx6sx-ocotp", "syscon";
1045 reg = <0x021bc000 0x4000>;
1046 clocks = <&clks IMX6SX_CLK_OCOTP>;
1048 tempmon_calib: calib@38 {
1052 tempmon_temp_grade: temp-grade@20 {
1058 compatible = "fsl,imx6sx-sai";
1059 reg = <0x021d4000 0x4000>;
1060 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1061 clocks = <&clks IMX6SX_CLK_SAI1_IPG>,
1062 <&clks IMX6SX_CLK_SAI1>,
1063 <&clks 0>, <&clks 0>;
1064 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1065 dma-names = "rx", "tx";
1066 dmas = <&sdma 31 24 0>, <&sdma 32 24 0>;
1067 status = "disabled";
1070 audmux: audmux@21d8000 {
1071 compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux";
1072 reg = <0x021d8000 0x4000>;
1073 status = "disabled";
1077 compatible = "fsl,imx6sx-sai";
1078 reg = <0x021dc000 0x4000>;
1079 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1080 clocks = <&clks IMX6SX_CLK_SAI2_IPG>,
1081 <&clks IMX6SX_CLK_SAI2>,
1082 <&clks 0>, <&clks 0>;
1083 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1084 dma-names = "rx", "tx";
1085 dmas = <&sdma 33 24 0>, <&sdma 34 24 0>;
1086 status = "disabled";
1089 qspi1: spi@21e0000 {
1090 #address-cells = <1>;
1092 compatible = "fsl,imx6sx-qspi";
1093 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
1094 reg-names = "QuadSPI", "QuadSPI-memory";
1095 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1096 clocks = <&clks IMX6SX_CLK_QSPI1>,
1097 <&clks IMX6SX_CLK_QSPI1>;
1098 clock-names = "qspi_en", "qspi";
1099 status = "disabled";
1102 qspi2: spi@21e4000 {
1103 #address-cells = <1>;
1105 compatible = "fsl,imx6sx-qspi";
1106 reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>;
1107 reg-names = "QuadSPI", "QuadSPI-memory";
1108 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
1109 clocks = <&clks IMX6SX_CLK_QSPI2>,
1110 <&clks IMX6SX_CLK_QSPI2>;
1111 clock-names = "qspi_en", "qspi";
1112 status = "disabled";
1115 uart2: serial@21e8000 {
1116 compatible = "fsl,imx6sx-uart",
1117 "fsl,imx6q-uart", "fsl,imx21-uart";
1118 reg = <0x021e8000 0x4000>;
1119 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1120 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1121 <&clks IMX6SX_CLK_UART_SERIAL>;
1122 clock-names = "ipg", "per";
1123 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1124 dma-names = "rx", "tx";
1125 status = "disabled";
1128 uart3: serial@21ec000 {
1129 compatible = "fsl,imx6sx-uart",
1130 "fsl,imx6q-uart", "fsl,imx21-uart";
1131 reg = <0x021ec000 0x4000>;
1132 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1133 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1134 <&clks IMX6SX_CLK_UART_SERIAL>;
1135 clock-names = "ipg", "per";
1136 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1137 dma-names = "rx", "tx";
1138 status = "disabled";
1141 uart4: serial@21f0000 {
1142 compatible = "fsl,imx6sx-uart",
1143 "fsl,imx6q-uart", "fsl,imx21-uart";
1144 reg = <0x021f0000 0x4000>;
1145 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1146 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1147 <&clks IMX6SX_CLK_UART_SERIAL>;
1148 clock-names = "ipg", "per";
1149 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1150 dma-names = "rx", "tx";
1151 status = "disabled";
1154 uart5: serial@21f4000 {
1155 compatible = "fsl,imx6sx-uart",
1156 "fsl,imx6q-uart", "fsl,imx21-uart";
1157 reg = <0x021f4000 0x4000>;
1158 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1159 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1160 <&clks IMX6SX_CLK_UART_SERIAL>;
1161 clock-names = "ipg", "per";
1162 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1163 dma-names = "rx", "tx";
1164 status = "disabled";
1168 #address-cells = <1>;
1170 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1171 reg = <0x021f8000 0x4000>;
1172 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1173 clocks = <&clks IMX6SX_CLK_I2C4>;
1174 status = "disabled";
1178 aips3: aips-bus@2200000 {
1179 compatible = "fsl,aips-bus", "simple-bus";
1180 #address-cells = <1>;
1182 reg = <0x02200000 0x100000>;
1186 compatible = "fsl,spba-bus", "simple-bus";
1187 #address-cells = <1>;
1189 reg = <0x02240000 0x40000>;
1193 reg = <0x02214000 0x4000>;
1194 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1195 clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1196 <&clks IMX6SX_CLK_CSI>,
1197 <&clks IMX6SX_CLK_DCIC1>;
1198 clock-names = "disp-axi", "csi_mclk", "dcic";
1199 status = "disabled";
1203 compatible = "fsl,imx6sx-pxp", "fsl,imx6ull-pxp";
1204 reg = <0x02218000 0x4000>;
1205 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1206 clocks = <&clks IMX6SX_CLK_PXP_AXI>;
1207 clock-names = "axi";
1208 status = "disabled";
1212 reg = <0x0221c000 0x4000>;
1213 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1214 clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1215 <&clks IMX6SX_CLK_CSI>,
1216 <&clks IMX6SX_CLK_DCIC2>;
1217 clock-names = "disp-axi", "csi_mclk", "dcic";
1218 status = "disabled";
1221 lcdif1: lcdif@2220000 {
1222 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1223 reg = <0x02220000 0x4000>;
1224 interrupts = <GIC_SPI 5 IRQ_TYPE_EDGE_RISING>;
1225 clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
1226 <&clks IMX6SX_CLK_LCDIF_APB>,
1227 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1228 clock-names = "pix", "axi", "disp_axi";
1229 status = "disabled";
1232 lcdif2: lcdif@2224000 {
1233 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1234 reg = <0x02224000 0x4000>;
1235 interrupts = <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>;
1236 clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>,
1237 <&clks IMX6SX_CLK_LCDIF_APB>,
1238 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1239 clock-names = "pix", "axi", "disp_axi";
1240 status = "disabled";
1243 vadc: vadc@2228000 {
1244 reg = <0x02228000 0x4000>, <0x0222c000 0x4000>;
1245 reg-names = "vadc-vafe", "vadc-vdec";
1246 clocks = <&clks IMX6SX_CLK_VADC>,
1247 <&clks IMX6SX_CLK_CSI>;
1248 clock-names = "vadc", "csi";
1249 status = "disabled";
1254 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1255 reg = <0x02280000 0x4000>;
1256 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1257 clocks = <&clks IMX6SX_CLK_IPG>;
1258 clock-names = "adc";
1259 fsl,adck-max-frequency = <30000000>, <40000000>,
1261 status = "disabled";
1265 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1266 reg = <0x02284000 0x4000>;
1267 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1268 clocks = <&clks IMX6SX_CLK_IPG>;
1269 clock-names = "adc";
1270 fsl,adck-max-frequency = <30000000>, <40000000>,
1272 status = "disabled";
1275 wdog3: wdog@2288000 {
1276 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
1277 reg = <0x02288000 0x4000>;
1278 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1279 clocks = <&clks IMX6SX_CLK_IPG>;
1280 status = "disabled";
1283 ecspi5: spi@228c000 {
1284 #address-cells = <1>;
1286 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
1287 reg = <0x0228c000 0x4000>;
1288 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1289 clocks = <&clks IMX6SX_CLK_ECSPI5>,
1290 <&clks IMX6SX_CLK_ECSPI5>;
1291 clock-names = "ipg", "per";
1292 status = "disabled";
1295 uart6: serial@22a0000 {
1296 compatible = "fsl,imx6sx-uart",
1297 "fsl,imx6q-uart", "fsl,imx21-uart";
1298 reg = <0x022a0000 0x4000>;
1299 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1300 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1301 <&clks IMX6SX_CLK_UART_SERIAL>;
1302 clock-names = "ipg", "per";
1303 dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
1304 dma-names = "rx", "tx";
1305 status = "disabled";
1309 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1310 reg = <0x022a4000 0x4000>;
1311 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1312 clocks = <&clks IMX6SX_CLK_PWM5>,
1313 <&clks IMX6SX_CLK_PWM5>;
1314 clock-names = "ipg", "per";
1319 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1320 reg = <0x022a8000 0x4000>;
1321 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1322 clocks = <&clks IMX6SX_CLK_PWM6>,
1323 <&clks IMX6SX_CLK_PWM6>;
1324 clock-names = "ipg", "per";
1329 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1330 reg = <0x022ac000 0x4000>;
1331 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1332 clocks = <&clks IMX6SX_CLK_PWM7>,
1333 <&clks IMX6SX_CLK_PWM7>;
1334 clock-names = "ipg", "per";
1339 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1340 reg = <0x0022b0000 0x4000>;
1341 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1342 clocks = <&clks IMX6SX_CLK_PWM8>,
1343 <&clks IMX6SX_CLK_PWM8>;
1344 clock-names = "ipg", "per";
1349 pcie: pcie@8ffc000 {
1350 compatible = "fsl,imx6sx-pcie", "snps,dw-pcie";
1351 reg = <0x08ffc000 0x04000>, <0x08f00000 0x80000>;
1352 reg-names = "dbi", "config";
1353 #address-cells = <3>;
1355 device_type = "pci";
1356 bus-range = <0x00 0xff>;
1357 ranges = <0x81000000 0 0 0x08f80000 0 0x00010000 /* downstream I/O */
1358 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */
1360 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1361 interrupt-names = "msi";
1362 #interrupt-cells = <1>;
1363 interrupt-map-mask = <0 0 0 0x7>;
1364 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1365 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1366 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1367 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1368 clocks = <&clks IMX6SX_CLK_PCIE_AXI>,
1369 <&clks IMX6SX_CLK_LVDS1_OUT>,
1370 <&clks IMX6SX_CLK_PCIE_REF_125M>,
1371 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1372 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi";
1373 power-domains = <&pd_pci>;
1374 status = "disabled";